[PATCH v1 00/10] provide ethernet support for ar9344 and TP-LINK TL-WDR4300

[PATCH v1 00/10] provide ethernet support for ar9344 and TP-LINK TL-WDR4300

[Oleksij Rempel]

This patches should go on top of my previous set "[PATCH v1 1/3] net: ath79: add ag71xx Ethernet driver"
It is enabling networking support for ar9344 on TP-LINK TL-WDR4300 router.

Oleksij Rempel (10):
  net: ath79: add ar9344 support
  MIPS: dts: ar9331: update compatible for mac0 node
  MIPS: dts: ar9344: add mac0 node
  MIPS: dts: tl_wdr4300: enable mac0
  MIPS: dts: tl_wdr4300: add alias for spiflash
  MIPS: dts: tl_wdr4300: remove RO flag from barebox partition
  add phy: ar8327 driver
  rename tplink devicetree
  MIPS: tplink-wdr4300_defconfig: add network support
  MIPS: dts: ar9344: add APB bus

 arch/mips/configs/tplink-wdr4300_defconfig         |  12 +-
 arch/mips/dts/ar9331.dtsi                          |   2 +-
 ...4_tl_wdr4300.dts => ar9344-tl-wdr4300-v1.7.dts} |  10 +-
 arch/mips/dts/ar9344.dtsi                          |  44 +++-
 drivers/net/ag71xx.c                               | 192 ++++++++++++--
 drivers/net/phy/Kconfig                            |   5 +
 drivers/net/phy/Makefile                           |   1 +
 drivers/net/phy/ar8327.c                           | 276 +++++++++++++++++++++
 8 files changed, 494 insertions(+), 48 deletions(-)
 rename arch/mips/dts/{ar9344_tl_wdr4300.dts => ar9344-tl-wdr4300-v1.7.dts} (85%)
 create mode 100644 drivers/net/phy/ar8327.c

-- 
2.11.0


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[PATCH v1 01/10] net: ath79: add ar9344 support

[Oleksij Rempel]

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 drivers/net/ag71xx.c | 192 +++++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 165 insertions(+), 27 deletions(-)

diff --git a/drivers/net/ag71xx.c b/drivers/net/ag71xx.c
index d13bf9171..b8bd12bc3 100644
--- a/drivers/net/ag71xx.c
+++ b/drivers/net/ag71xx.c
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <driver.h>
 #include <net.h>
 #include <dma.h>
 #include <init.h>
@@ -185,6 +186,11 @@
 #define AG71XX_ETH_CFG_RGMII_GE0        (1<<0)
 #define AG71XX_ETH_CFG_MII_GE0_SLAVE    (1<<4)
 
+enum ag71xx_type {
+	AG71XX_TYPE_AR9331_GE0,
+	AG71XX_TYPE_AR9344_GMAC0,
+};
+
 /*
  * h/w descriptor
  */
@@ -213,23 +219,31 @@ struct ag71xx {
 	void __iomem *regs;
 	void __iomem *regs_gmac;
 	struct mii_bus miibus;
+	const struct ag71xx_cfg *cfg;
 
 	void *rx_buffer;
 
 	unsigned char *rx_pkt[NO_OF_RX_FIFOS];
 	ag7240_desc_t *fifo_tx;
 	ag7240_desc_t *fifo_rx;
+	dma_addr_t addr_tx;
+	dma_addr_t addr_rx;
 
 	int next_tx;
 	int next_rx;
 };
 
+struct ag71xx_cfg {
+	enum ag71xx_type type;
+	void (*init_mii)(struct ag71xx *priv);
+};
+
 static inline void ag71xx_check_reg_offset(struct ag71xx *priv, int reg)
 {
 	switch (reg) {
 	case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
 	case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
-	case AG71XX_REG_MII_CFG:
+	case AG71XX_REG_MII_CFG ... AG71XX_REG_MII_IND:
 		break;
 
 	default:
@@ -237,6 +251,16 @@ static inline void ag71xx_check_reg_offset(struct ag71xx *priv, int reg)
 	}
 }
 
+static inline u32 ar7240_reg_rd(u32 reg)
+{
+	return __raw_readl(KSEG1ADDR(reg));
+}
+
+static inline void ar7240_reg_wr(u32 reg, u32 val)
+{
+	__raw_writel(val, KSEG1ADDR(reg));
+}
+
 static inline u32 ag71xx_gmac_rr(struct ag71xx *dev, int reg)
 {
 	return __raw_readl(dev->regs_gmac + reg);
@@ -263,13 +287,81 @@ static inline void ag71xx_wr(struct ag71xx *priv, int reg, u32 val)
 	(void)__raw_readl(priv->regs + reg);
 }
 
-static int ag71xx_ether_mii_read(struct mii_bus *miidev, int addr, int reg)
+static int ag71xx_ether_mii_read(struct mii_bus *miidev, int phy_addr, int reg)
 {
-	return 0xffff;
+	struct ag71xx *priv = miidev->priv;
+	const struct ag71xx_cfg *cfg = priv->cfg;
+	volatile int rddata;
+	u16 addr = (phy_addr << MII_ADDR_SHIFT) | reg, val;
+	u16 ii = 0xFFFF;
+
+	if (AG71XX_TYPE_AR9331_GE0 == cfg->type)
+		return 0xffff;
+	/*
+	 * Check for previous transactions are complete. Added to avoid
+	 * race condition while running at higher frequencies.
+	 */
+	do {
+		udelay(5);
+		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
+	} while (rddata && --ii);
+
+	if (ii == 0)
+		printk("ERROR:%s:%d transaction failed\n",__func__,__LINE__);
+
+
+	ag71xx_wr(priv, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+	ag71xx_wr(priv, AG71XX_REG_MII_ADDR, addr);
+	ag71xx_wr(priv, AG71XX_REG_MII_CMD, MII_CMD_READ);
+
+	do {
+		udelay(5);
+		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
+	} while (rddata && --ii);
+
+	if (ii == 0)
+		printk("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
+
+	val = ag71xx_rr(priv, AG71XX_REG_MII_STATUS);
+	ag71xx_wr(priv, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
+
+	return val;
 }
 
-static int ag71xx_ether_mii_write(struct mii_bus *miidev, int addr, int reg, u16 val)
+static int ag71xx_ether_mii_write(struct mii_bus *miidev, int phy_addr,
+				  int reg, u16 val)
 {
+	struct ag71xx *priv = miidev->priv;
+	const struct ag71xx_cfg *cfg = priv->cfg;
+	u16 addr = (phy_addr << MII_ADDR_SHIFT) | reg;
+	u16 ii = 0xFFFF;
+	volatile int rddata;
+
+	if (AG71XX_TYPE_AR9331_GE0 == cfg->type)
+		return 0;
+
+	/*
+	 * Check for previous transactions are complete. Added to avoid
+	 * race condition while running at higher frequencies.
+	 */
+	do {
+		udelay(5);
+		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
+	} while (rddata && --ii);
+
+	if (ii == 0)
+		printk("ERROR:%s:%d transaction failed\n", __func__, __LINE__);
+
+	ag71xx_wr(priv, AG71XX_REG_MII_ADDR, addr);
+	ag71xx_wr(priv, AG71XX_REG_MII_CTRL, val);
+
+	do {
+		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
+	} while (rddata && --ii);
+
+	if (ii == 0)
+		printk("Error!!! Leave ag7240_miiphy_write without polling correct status!\n");
+
 	return 0;
 }
 
@@ -372,6 +464,13 @@ static int ag71xx_ether_send(struct eth_device *edev, void *packet, int length)
 
 static int ag71xx_ether_open(struct eth_device *edev)
 {
+	struct ag71xx *priv = edev->priv;
+	const struct ag71xx_cfg *cfg = priv->cfg;
+
+	if (AG71XX_TYPE_AR9344_GMAC0 == cfg->type)
+		return phy_device_connect(edev, &priv->miibus, 0,
+			NULL, 0, PHY_INTERFACE_MODE_RGMII_TXID);
+
 	return 0;
 }
 
@@ -408,25 +507,63 @@ static int ag71xx_ether_init(struct eth_device *edev)
 	return 1;
 }
 
-static int ag71xx_mii_setup(struct ag71xx *priv)
+static void ag71xx_ar9331_ge0_mii_init(struct ag71xx *priv)
 {
 	u32 rd;
 
-	rd = ag71xx_gmac_rr(priv, 0);
+	rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
+	rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_10_100);
+	ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
+
+	/* config FIFOs */
+	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
+
+	rd = ag71xx_gmac_rr(priv, AG71XX_REG_MAC_CFG1);
 	rd |= AG71XX_ETH_CFG_MII_GE0_SLAVE;
 	ag71xx_gmac_wr(priv, 0, rd);
+}
 
-	return 0;
+static void ag71xx_ar9344_gmac0_mii_init(struct ag71xx *priv)
+{
+	u32 rd;
+
+	rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
+	rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_1000);
+	ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
+
+	/* config FIFOs */
+	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
+
+	ag71xx_gmac_wr(priv, AG71XX_REG_MAC_CFG1, 1);
+	udelay(1000);
+	ag71xx_wr(priv, AG71XX_REG_MII_CFG, 4 | (1 << 31));
+	ag71xx_wr(priv, AG71XX_REG_MII_CFG, 4);
 }
 
+static struct ag71xx_cfg ag71xx_cfg_ar9331_ge0 = {
+	.type = AG71XX_TYPE_AR9331_GE0,
+	.init_mii = ag71xx_ar9331_ge0_mii_init,
+};
+
+static struct ag71xx_cfg ag71xx_cfg_ar9344_gmac0 = {
+	.type = AG71XX_TYPE_AR9344_GMAC0,
+	.init_mii = ag71xx_ar9344_gmac0_mii_init,
+};
+
 static int ag71xx_probe(struct device_d *dev)
 {
 	void __iomem *regs, *regs_gmac;
 	struct mii_bus *miibus;
 	struct eth_device *edev;
+	struct ag71xx_cfg *cfg;
 	struct ag71xx *priv;
 	u32 mac_h, mac_l;
-	u32 rd;
+	u32 rd, mask;
+	int ret;
+
+	ret = dev_get_drvdata(dev, (const void **)&cfg);
+	if (ret)
+		return ret;
 
 	regs_gmac = dev_request_mem_region_by_name(dev, "gmac");
 	if (IS_ERR(regs_gmac))
@@ -452,41 +589,42 @@ static int ag71xx_probe(struct device_d *dev)
 	priv->dev = dev;
 	priv->regs = regs;
 	priv->regs_gmac = regs_gmac;
+	priv->cfg = cfg;
 
 	miibus->read = ag71xx_ether_mii_read;
 	miibus->write = ag71xx_ether_mii_write;
 	miibus->priv = priv;
 
 	/* enable switch core */
-	rd = __raw_readl((char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG)) & ~(0x1f);
+	rd = ar7240_reg_rd(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG);
+	rd &= ~(0x1f);
 	rd |= 0x10;
-	__raw_writel(rd, (char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG));
+	if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0)
+		rd |= 0x1;
+	ar7240_reg_wr((AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG), rd);
 
 	if (ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE) != 0)
 		ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, 0);
 
 	/* reset GE0 MAC and MDIO */
+	mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO
+		| AR933X_RESET_SWITCH;
+
 	rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
-	rd |= AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH;
+	rd |= mask;
 	ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
 	mdelay(100);
 
 	rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
-	rd &= ~(AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH);
+	rd &= ~(mask);
 	ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
 	mdelay(100);
 
 	ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_SR | MAC_CFG1_TX_RST | MAC_CFG1_RX_RST));
 	ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
 
-	rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
-	rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_10_100);
-	ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
-
-	/* config FIFOs */
-	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
-
-	ag71xx_mii_setup(priv);
+	if (cfg->init_mii)
+		cfg->init_mii(priv);
 
 	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG1, 0x10ffff);
 	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG2, 0xAAA0555);
@@ -497,8 +635,10 @@ static int ag71xx_probe(struct device_d *dev)
 	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG3, 0x1f00140);
 
 	priv->rx_buffer = xmemalign(PAGE_SIZE, NO_OF_RX_FIFOS * MAX_RBUFF_SZ);
-	priv->fifo_tx = dma_alloc_coherent(NO_OF_TX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
-	priv->fifo_rx = dma_alloc_coherent(NO_OF_RX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
+	priv->fifo_tx = dma_alloc_coherent(NO_OF_TX_FIFOS * sizeof(ag7240_desc_t),
+					   &priv->addr_tx);
+	priv->fifo_rx = dma_alloc_coherent(NO_OF_RX_FIFOS * sizeof(ag7240_desc_t),
+					   &priv->addr_rx);
 	priv->next_tx = 0;
 
 	mac_l = 0x3344;
@@ -516,11 +656,9 @@ static int ag71xx_probe(struct device_d *dev)
 }
 
 static __maybe_unused struct of_device_id ag71xx_dt_ids[] = {
-	{
-		.compatible = "qca,ar7100-gmac",
-	}, {
-		/* sentinel */
-	}
+	{ .compatible = "qca,ar9331-ge0", .data = &ag71xx_cfg_ar9331_ge0, },
+	{ .compatible = "qca,ar9344-gmac0", .data = &ag71xx_cfg_ar9344_gmac0, },
+	{ /* sentinel */ }
 };
 
 static struct driver_d ag71xx_driver = {
-- 
2.11.0


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[PATCH v1 02/10] MIPS: dts: ar9331: update compatible for mac0 node

[Oleksij Rempel]

MACs on same chip are too different to have one common compatible

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/dts/ar9331.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi
index 109af8664..b4b8b766b 100644
--- a/arch/mips/dts/ar9331.dtsi
+++ b/arch/mips/dts/ar9331.dtsi
@@ -1,7 +1,7 @@
 / {
 	ahb {
 		mac0: mac@19000000 {
-			compatible = "qca,ar7100-gmac", "qca,ar9331-gmac";
+			compatible = "qca,ar9331-ge0";
 			reg = <0x18070000 0x00000100>,
 			      <0x19000000 0x01000000>;
 			reg-names = "gmac", "ge0";
-- 
2.11.0


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[PATCH v1 03/10] MIPS: dts: ar9344: add mac0 node

[Oleksij Rempel]

this node is supported by ag71xx driver

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/dts/ar9344.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/mips/dts/ar9344.dtsi b/arch/mips/dts/ar9344.dtsi
index 0838e8d7f..858751112 100644
--- a/arch/mips/dts/ar9344.dtsi
+++ b/arch/mips/dts/ar9344.dtsi
@@ -40,6 +40,16 @@
 			status = "disabled";
 		};
 
+		mac0: mac@19000000 {
+			compatible = "qca,ar9344-gmac0";
+			reg = <0x18070000 0x00000100>,
+			      <0x19000000 0x01000000>;
+			reg-names = "gmac", "ge0";
+			phy-mode = "rgmii";
+
+			status = "disabled";
+		};
+
 		spi: spi@1f000000 {
 			compatible = "qca,ar7100-spi", "qca,ar9344-spi";
 			reg = <0x1f000000 0x1c>;
-- 
2.11.0


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[PATCH v1 04/10] MIPS: dts: tl_wdr4300: enable mac0

[Oleksij Rempel]

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/dts/ar9344_tl_wdr4300.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344_tl_wdr4300.dts
index b02c1d730..5a4a6f379 100644
--- a/arch/mips/dts/ar9344_tl_wdr4300.dts
+++ b/arch/mips/dts/ar9344_tl_wdr4300.dts
@@ -61,3 +61,7 @@
 		};
 	};
 };
+
+&mac0 {
+	status = "okay";
+};
-- 
2.11.0


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[PATCH v1 05/10] MIPS: dts: tl_wdr4300: add alias for spiflash

[Oleksij Rempel]

to unify the naming with TP-Link TL-MR3020.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/dts/ar9344_tl_wdr4300.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344_tl_wdr4300.dts
index 5a4a6f379..c784e6cb4 100644
--- a/arch/mips/dts/ar9344_tl_wdr4300.dts
+++ b/arch/mips/dts/ar9344_tl_wdr4300.dts
@@ -11,6 +11,7 @@
 
 	aliases {
 		serial0 = &uart0;
+		spiflash = &spiflash;
 	};
 
 	memory@0 {
-- 
2.11.0


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[PATCH v1 06/10] MIPS: dts: tl_wdr4300: remove RO flag from barebox partition

[Oleksij Rempel]

we need it RW for barebox updates.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/dts/ar9344_tl_wdr4300.dts | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344_tl_wdr4300.dts
index c784e6cb4..139717a6b 100644
--- a/arch/mips/dts/ar9344_tl_wdr4300.dts
+++ b/arch/mips/dts/ar9344_tl_wdr4300.dts
@@ -53,7 +53,6 @@
 		partition@0 {
 			label = "barebox";
 			reg = <0 0x80000>;
-			read-only;
 		};
 
 		partition@80000 {
-- 
2.11.0


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[PATCH v1 07/10] add phy: ar8327 driver

[Oleksij Rempel]

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 drivers/net/phy/Kconfig  |   5 +
 drivers/net/phy/Makefile |   1 +
 drivers/net/phy/ar8327.c | 276 +++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 282 insertions(+)
 create mode 100644 drivers/net/phy/ar8327.c

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d30f65b8e..ea2e06265 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -8,6 +8,11 @@ if PHYLIB
 
 comment "MII PHY device drivers"
 
+config AR8327N_PHY
+	bool "Driver for QCA AR8327N PHYs"
+	---help---
+	  Currently supports the AR8327N PHY.
+
 config AT803X_PHY
 	bool "Driver for Atheros AT803X PHYs"
 	---help---
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 10732f807..13b8f6545 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -1,4 +1,5 @@
 obj-y += phy.o mdio_bus.o
+obj-$(CONFIG_AR8327N_PHY)	+= ar8327.o
 obj-$(CONFIG_AT803X_PHY)	+= at803x.o
 obj-$(CONFIG_LXT_PHY)		+= lxt.o
 obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
diff --git a/drivers/net/phy/ar8327.c b/drivers/net/phy/ar8327.c
new file mode 100644
index 000000000..647871283
--- /dev/null
+++ b/drivers/net/phy/ar8327.c
@@ -0,0 +1,276 @@
+/*
+ * Copyright (C) 2017 Oleksij Rempel <linux@rempel-privat.de>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <common.h>
+#include <init.h>
+#include <linux/phy.h>
+#include <linux/string.h>
+
+#define ATHR_PHY_MAX	5
+
+/*****************/
+/* PHY Registers */
+/*****************/
+#define ATHR_PHY_CONTROL			0x00
+#define ATHR_PHY_STATUS				0x01
+#define ATHR_PHY_ID1				0x02
+#define ATHR_PHY_ID2				0x03
+#define ATHR_AUTONEG_ADVERT			0x04
+#define ATHR_LINK_PARTNER_ABILITY		0x05
+#define ATHR_AUTONEG_EXPANSION			0x06
+#define ATHR_NEXT_PAGE_TRANSMIT			0x07
+#define ATHR_LINK_PARTNER_NEXT_PAGE		0x08
+#define ATHR_1000BASET_CONTROL			0x09
+#define ATHR_1000BASET_STATUS			0x0a
+#define ATHR_PHY_SPEC_CONTROL			0x10
+#define ATHR_PHY_SPEC_STATUS			0x11
+#define ATHR_DEBUG_PORT_ADDRESS			0x1d
+#define ATHR_DEBUG_PORT_DATA			0x1e
+
+/* Advertisement register. */
+#define ATHR_ADVERTISE_ASYM_PAUSE		0x0800
+#define ATHR_ADVERTISE_PAUSE			0x0400
+#define ATHR_ADVERTISE_100FULL			0x0100
+#define ATHR_ADVERTISE_100HALF			0x0080
+#define ATHR_ADVERTISE_10FULL			0x0040
+#define ATHR_ADVERTISE_10HALF			0x0020
+
+#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \
+                            ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
+                            ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
+
+/* ATHR_PHY_CONTROL fields */
+#define ATHR_CTRL_SOFTWARE_RESET		0x8000
+#define ATHR_CTRL_AUTONEGOTIATION_ENABLE	0x1000
+
+/* 1000BASET_CONTROL */
+#define ATHR_ADVERTISE_1000FULL			0x0200
+
+/* Phy Specific status fields */
+#define ATHR_STATUS_LINK_PASS			0x0400
+
+static u32 ar8327n_reg_read(struct phy_device *phydev, u32 reg_addr)
+{
+	u32 reg_word_addr;
+	u32 phy_addr, tmp_val, reg_val;
+	u16 phy_val;
+	u8 phy_reg;
+
+	/* change reg_addr to 16-bit word address, 32-bit aligned */
+	reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+	/* configure register high address */
+	phy_addr = 0x18;
+	phy_reg = 0x0;
+	phy_val = (u16) ((reg_word_addr >> 8) & 0x1ff);  /* bit16-8 of reg address */
+	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
+
+	/* For some registers such as MIBs, since it is read/clear, we should */
+	/* read the lower 16-bit register then the higher one */
+
+	/* read register in lower address */
+	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+	reg_val = (u32) mdiobus_read(phydev->bus, phy_addr, phy_reg);
+
+	/* read register in higher address */
+	reg_word_addr++;
+	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+	reg_val = (u32) mdiobus_read(phydev->bus, phy_addr, phy_reg);
+	reg_val |= (tmp_val << 16);
+
+	return reg_val;
+}
+
+static void ar8327n_reg_write(struct phy_device *phydev, u32 reg_addr,
+			      u32 reg_val)
+{
+	u32 reg_word_addr;
+	u32 phy_addr;
+	u16 phy_val;
+	u8 phy_reg;
+
+	/* change reg_addr to 16-bit word address, 32-bit aligned */
+	reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
+
+	/* configure register high address */
+	phy_addr = 0x18;
+	phy_reg = 0x0;
+	phy_val = (u16) ((reg_word_addr >> 8) & 0x1ff);  /* bit16-8 of reg address */
+	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
+
+	/* For some registers such as ARL and VLAN, since they include BUSY bit */
+	/* in lower address, we should write the higher 16-bit register then the */
+	/* lower one */
+
+	/* read register in higher address */
+	reg_word_addr++;
+	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+	phy_val = (u16) ((reg_val >> 16) & 0xffff);
+	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
+
+	/* write register in lower address */
+	reg_word_addr--;
+	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
+	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
+	phy_val = (u16) (reg_val & 0xffff);
+	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
+}
+
+static int ar8327n_phy_is_link_alive(struct phy_device *phydev, int phy_addr)
+{
+	u16 val;
+
+	val = mdiobus_read(phydev->bus, phy_addr, ATHR_PHY_SPEC_STATUS);
+
+	return !!(val & ATHR_STATUS_LINK_PASS);
+}
+
+static int ar8327n_phy_setup(struct phy_device *phydev)
+{
+	int phy_addr;
+
+	/* start auto negotiation on each phy */
+	for (phy_addr = 0; phy_addr < ATHR_PHY_MAX; phy_addr++) {
+		mdiobus_write(phydev->bus, phy_addr, ATHR_AUTONEG_ADVERT,
+			      ATHR_ADVERTISE_ALL);
+
+		mdiobus_write(phydev->bus, phy_addr, ATHR_1000BASET_CONTROL,
+			      ATHR_ADVERTISE_1000FULL);
+
+		/* Reset PHYs*/
+		mdiobus_write(phydev->bus, phy_addr, ATHR_PHY_CONTROL,
+			      ATHR_CTRL_AUTONEGOTIATION_ENABLE
+			      | ATHR_CTRL_SOFTWARE_RESET);
+	}
+
+	/*
+	 * After the phy is reset, it takes a little while before
+	 * it can respond properly.
+	 */
+	mdelay(1000);
+
+	for (phy_addr = 0; phy_addr < ATHR_PHY_MAX; phy_addr++) {
+		int count;
+
+		for (count = 20; count > 0; count--) {
+			u16 val;
+			val = mdiobus_read(phydev->bus, phy_addr,
+					   ATHR_PHY_CONTROL);
+
+			if (!(val & ATHR_CTRL_SOFTWARE_RESET))
+				break;
+
+			mdelay(150);
+		}
+
+		if (!count)
+			printk("Port %d, Negotiation timeout\n", phy_addr);
+	}
+
+	return 0;
+}
+
+static int ar8327n_get_link(struct phy_device *phydev)
+{
+	int phy_addr;
+	int live_links = 0;
+
+	for (phy_addr = 0; phy_addr < ATHR_PHY_MAX; phy_addr++) {
+		if (ar8327n_phy_is_link_alive(phydev, phy_addr))
+			live_links++;
+	}
+
+	return (live_links > 0);
+}
+
+static int ar8327n_config_init(struct phy_device *phydev)
+{
+	int phy_addr = 0;
+
+	if (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)
+		return 0;
+
+	/* if using header for register configuration, we have to     */
+	/* configure s17 register after frame transmission is enabled */
+
+	/* configure the RGMII */
+	ar8327n_reg_write(phydev, 0x624, 0x7f7f7f7f);
+	ar8327n_reg_write(phydev, 0x10, 0x40000000);
+	ar8327n_reg_write(phydev, 0x4, 0x07600000);
+	ar8327n_reg_write(phydev, 0xc, 0x01000000);
+	ar8327n_reg_write(phydev, 0x7c, 0x0000007e);
+
+	/* AR8327/AR8328 v1.0 fixup */
+	if ((ar8327n_reg_read(phydev, 0x0) & 0xffff) == 0x1201) {
+		/* TODO v1.0 seems to be something special. Currently not tested */
+		printk("!!! phy versio v1.0 is detected!! \n");
+		for (phy_addr = 0x0; phy_addr <= ATHR_PHY_MAX; phy_addr++) {
+			/* For 100M waveform */
+			mdiobus_write(phydev->bus, phy_addr, 0x1d, 0x0);
+			mdiobus_write(phydev->bus, phy_addr, 0x1e, 0x02ea);
+			/* Turn On Gigabit Clock */
+			mdiobus_write(phydev->bus, phy_addr, 0x1d, 0x3d);
+			mdiobus_write(phydev->bus, phy_addr, 0x1e, 0x68a0);
+		}
+	}
+
+	/*
+	 * set the WAN Port(Port1) Disable Mode so
+	 * it can not receive or transmit any frames.
+	 */
+	ar8327n_reg_write(phydev, 0x066c,
+			  ar8327n_reg_read(phydev, 0x066c) & 0xfff8ffff);
+
+	ar8327n_phy_setup(phydev);
+
+	return 0;
+}
+
+static int ar8327n_read_status(struct phy_device *phydev)
+{
+	/* for GMAC0 we have only one static mode */
+	phydev->speed = SPEED_1000;
+	phydev->duplex = DUPLEX_FULL;
+	phydev->pause = phydev->asym_pause = 0;
+	phydev->link = ar8327n_get_link(phydev);
+	return 0;
+}
+
+static int ar8327n_config_aneg(struct phy_device *phydev)
+{
+	return 0;
+}
+
+static int ar8327n_aneg_done(struct phy_device *phydev)
+{
+	return BMSR_ANEGCOMPLETE;
+}
+
+static struct phy_driver ar8327n_driver[] = {
+{
+	/* QCA AR8327N */
+	.phy_id		= 0x004dd034,
+	.phy_id_mask	= 0xffffffef,
+	.drv.name	= "QCA AR8327N switch",
+	.config_init	= ar8327n_config_init,
+	.features	= PHY_GBIT_FEATURES,
+	.config_aneg	= &ar8327n_config_aneg,
+	.read_status	= &ar8327n_read_status,
+	.aneg_done	= &ar8327n_aneg_done,
+}};
+
+static int atheros_phy_init(void)
+{
+	return phy_drivers_register(ar8327n_driver,
+				    ARRAY_SIZE(ar8327n_driver));
+}
+fs_initcall(atheros_phy_init);
-- 
2.11.0


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[PATCH v1 08/10] rename tplink devicetree

[Oleksij Rempel]

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/configs/tplink-wdr4300_defconfig                          | 2 +-
 arch/mips/dts/{ar9344_tl_wdr4300.dts => ar9344-tl-wdr4300-v1.7.dts} | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)
 rename arch/mips/dts/{ar9344_tl_wdr4300.dts => ar9344-tl-wdr4300-v1.7.dts} (91%)

diff --git a/arch/mips/configs/tplink-wdr4300_defconfig b/arch/mips/configs/tplink-wdr4300_defconfig
index 63189b754..b5be221f6 100644
--- a/arch/mips/configs/tplink-wdr4300_defconfig
+++ b/arch/mips/configs/tplink-wdr4300_defconfig
@@ -1,5 +1,5 @@
 CONFIG_BUILTIN_DTB=y
-CONFIG_BUILTIN_DTB_NAME="ar9344_tl_wdr4300"
+CONFIG_BUILTIN_DTB_NAME="ar9344-tl-wdr4300-v1.7"
 CONFIG_MACH_MIPS_ATH79=y
 CONFIG_BOARD_TPLINK_WDR4300=y
 CONFIG_PBL_IMAGE=y
diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
similarity index 91%
rename from arch/mips/dts/ar9344_tl_wdr4300.dts
rename to arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
index 139717a6b..d16cab005 100644
--- a/arch/mips/dts/ar9344_tl_wdr4300.dts
+++ b/arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
@@ -6,8 +6,8 @@
 #include "ar9344.dtsi"
 
 / {
-	model = "TP-Link WDR4300";
-	compatible = "tplink,tl-wdr4300";
+	model = "TP-Link WDR4300 v1.7";
+	compatible = "tplink,tl-wdr4300", "tplink,tl-wdr4300-v1.7";
 
 	aliases {
 		serial0 = &uart0;
-- 
2.11.0


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[PATCH v1 09/10] MIPS: tplink-wdr4300_defconfig: add network support

[Oleksij Rempel]

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/configs/tplink-wdr4300_defconfig | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/arch/mips/configs/tplink-wdr4300_defconfig b/arch/mips/configs/tplink-wdr4300_defconfig
index b5be221f6..46093d243 100644
--- a/arch/mips/configs/tplink-wdr4300_defconfig
+++ b/arch/mips/configs/tplink-wdr4300_defconfig
@@ -32,6 +32,10 @@ CONFIG_CMD_LET=y
 CONFIG_CMD_MSLEEP=y
 CONFIG_CMD_READF=y
 CONFIG_CMD_SLEEP=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_HOST=y
+CONFIG_CMD_MIITOOL=y
+CONFIG_CMD_PING=y
 CONFIG_CMD_ECHO_E=y
 CONFIG_CMD_EDIT=y
 CONFIG_CMD_READLINE=y
@@ -55,15 +59,13 @@ CONFIG_CMD_TIME=y
 CONFIG_NET=y
 CONFIG_NET_NFS=y
 CONFIG_NET_NETCONSOLE=y
-CONFIG_NET_RESOLV=y
-CONFIG_NET_DHCP=y
 CONFIG_NET_SNTP=y
 CONFIG_OFDEVICE=y
 CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_OF_BAREBOX_ENV_IN_FS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_DRIVER_NET_AG71XX=y
-CONFIG_AT803X_PHY=y
+CONFIG_AR8327N_PHY=y
 CONFIG_MDIO_BITBANG=y
 CONFIG_MDIO_GPIO=y
 CONFIG_DRIVER_SPI_ATH79=y
@@ -74,5 +76,7 @@ CONFIG_LED=y
 CONFIG_LED_GPIO=y
 CONFIG_LED_GPIO_OF=y
 CONFIG_LED_TRIGGERS=y
+CONFIG_FS_TFTP=y
+CONFIG_FS_NFS=y
 CONFIG_DIGEST_SHA224_GENERIC=y
 CONFIG_DIGEST_SHA256_GENERIC=y
-- 
2.11.0


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[PATCH v1 10/10] MIPS: dts: ar9344: add APB bus

[Oleksij Rempel]

and move nodes which belong to APB.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
---
 arch/mips/dts/ar9344.dtsi | 42 +++++++++++++++++++++++++-----------------
 1 file changed, 25 insertions(+), 17 deletions(-)

diff --git a/arch/mips/dts/ar9344.dtsi b/arch/mips/dts/ar9344.dtsi
index 858751112..3e105174d 100644
--- a/arch/mips/dts/ar9344.dtsi
+++ b/arch/mips/dts/ar9344.dtsi
@@ -29,15 +29,33 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		uart0: uart@18020000 {
-			compatible = "ns16550a", "qca,ar9344-uart0";
-			reg = <0x18020000 0x20>;
+		apb {
+			compatible = "simple-bus";
+			ranges;
 
-			reg-shift = <2>;
-			reg-io-width = <4>;
-			big-endian;
+			#address-cells = <1>;
+			#size-cells = <1>;
 
-			status = "disabled";
+			uart0: uart@18020000 {
+				compatible = "ns16550a", "qca,ar9344-uart0";
+				reg = <0x18020000 0x20>;
+
+				reg-shift = <2>;
+				reg-io-width = <4>;
+				big-endian;
+
+				status = "disabled";
+			};
+
+			spi: spi@1f000000 {
+				compatible = "qca,ar7100-spi", "qca,ar9344-spi";
+				reg = <0x1f000000 0x1c>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				status = "disabled";
+			};
 		};
 
 		mac0: mac@19000000 {
@@ -49,15 +67,5 @@
 
 			status = "disabled";
 		};
-
-		spi: spi@1f000000 {
-			compatible = "qca,ar7100-spi", "qca,ar9344-spi";
-			reg = <0x1f000000 0x1c>;
-
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			status = "disabled";
-		};
 	};
 };
-- 
2.11.0


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Re: [PATCH v1 01/10] net: ath79: add ar9344 support

[Sascha Hauer]

On Sun, Aug 27, 2017 at 09:02:21AM +0200, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
> ---
>  drivers/net/ag71xx.c | 192 +++++++++++++++++++++++++++++++++++++++++++--------
>  1 file changed, 165 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/net/ag71xx.c b/drivers/net/ag71xx.c
> index d13bf9171..b8bd12bc3 100644
> --- a/drivers/net/ag71xx.c
> +++ b/drivers/net/ag71xx.c
> @@ -12,6 +12,7 @@
>   */
>  
>  #include <common.h>
> +#include <driver.h>
>  #include <net.h>
>  #include <dma.h>
>  #include <init.h>
> @@ -185,6 +186,11 @@
>  #define AG71XX_ETH_CFG_RGMII_GE0        (1<<0)
>  #define AG71XX_ETH_CFG_MII_GE0_SLAVE    (1<<4)
>  
> +enum ag71xx_type {
> +	AG71XX_TYPE_AR9331_GE0,
> +	AG71XX_TYPE_AR9344_GMAC0,
> +};
> +
>  /*
>   * h/w descriptor
>   */
> @@ -213,23 +219,31 @@ struct ag71xx {
>  	void __iomem *regs;
>  	void __iomem *regs_gmac;
>  	struct mii_bus miibus;
> +	const struct ag71xx_cfg *cfg;
>  
>  	void *rx_buffer;
>  
>  	unsigned char *rx_pkt[NO_OF_RX_FIFOS];
>  	ag7240_desc_t *fifo_tx;
>  	ag7240_desc_t *fifo_rx;
> +	dma_addr_t addr_tx;
> +	dma_addr_t addr_rx;
>  
>  	int next_tx;
>  	int next_rx;
>  };
>  
> +struct ag71xx_cfg {
> +	enum ag71xx_type type;
> +	void (*init_mii)(struct ag71xx *priv);
> +};
> +
>  static inline void ag71xx_check_reg_offset(struct ag71xx *priv, int reg)
>  {
>  	switch (reg) {
>  	case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
>  	case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
> -	case AG71XX_REG_MII_CFG:
> +	case AG71XX_REG_MII_CFG ... AG71XX_REG_MII_IND:
>  		break;
>  
>  	default:
> @@ -237,6 +251,16 @@ static inline void ag71xx_check_reg_offset(struct ag71xx *priv, int reg)
>  	}
>  }
>  
> +static inline u32 ar7240_reg_rd(u32 reg)
> +{
> +	return __raw_readl(KSEG1ADDR(reg));
> +}
> +
> +static inline void ar7240_reg_wr(u32 reg, u32 val)
> +{
> +	__raw_writel(val, KSEG1ADDR(reg));
> +}
> +
>  static inline u32 ag71xx_gmac_rr(struct ag71xx *dev, int reg)
>  {
>  	return __raw_readl(dev->regs_gmac + reg);
> @@ -263,13 +287,81 @@ static inline void ag71xx_wr(struct ag71xx *priv, int reg, u32 val)
>  	(void)__raw_readl(priv->regs + reg);
>  }
>  
> -static int ag71xx_ether_mii_read(struct mii_bus *miidev, int addr, int reg)
> +static int ag71xx_ether_mii_read(struct mii_bus *miidev, int phy_addr, int reg)
>  {
> -	return 0xffff;
> +	struct ag71xx *priv = miidev->priv;
> +	const struct ag71xx_cfg *cfg = priv->cfg;
> +	volatile int rddata;

The 'volatile' looks rather unnecessary.

> +	u16 addr = (phy_addr << MII_ADDR_SHIFT) | reg, val;
> +	u16 ii = 0xFFFF;

lowercase letters for hex numbers please.

This is a loop counter, no need to specify the width of the variable,
plain 'int' looks better here.

> +
> +	if (AG71XX_TYPE_AR9331_GE0 == cfg->type)
> +		return 0xffff;
> +	/*
> +	 * Check for previous transactions are complete. Added to avoid
> +	 * race condition while running at higher frequencies.
> +	 */
> +	do {
> +		udelay(5);
> +		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
> +	} while (rddata && --ii);
> +
> +	if (ii == 0)
> +		printk("ERROR:%s:%d transaction failed\n",__func__,__LINE__);

Please use dev_err when printing device specific messages.

Shouldn't you return an error here instead of continuing?

> +
> +
> +	ag71xx_wr(priv, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
> +	ag71xx_wr(priv, AG71XX_REG_MII_ADDR, addr);
> +	ag71xx_wr(priv, AG71XX_REG_MII_CMD, MII_CMD_READ);
> +
> +	do {
> +		udelay(5);
> +		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
> +	} while (rddata && --ii);
> +
> +	if (ii == 0)
> +		printk("Error!!! Leave ag7240_miiphy_read without polling correct status!\n");
> +
> +	val = ag71xx_rr(priv, AG71XX_REG_MII_STATUS);
> +	ag71xx_wr(priv, AG71XX_REG_MII_CMD, MII_CMD_WRITE);
> +
> +	return val;
>  }
>  
> -static int ag71xx_ether_mii_write(struct mii_bus *miidev, int addr, int reg, u16 val)
> +static int ag71xx_ether_mii_write(struct mii_bus *miidev, int phy_addr,
> +				  int reg, u16 val)
>  {
> +	struct ag71xx *priv = miidev->priv;
> +	const struct ag71xx_cfg *cfg = priv->cfg;
> +	u16 addr = (phy_addr << MII_ADDR_SHIFT) | reg;
> +	u16 ii = 0xFFFF;
> +	volatile int rddata;

volatile?

> +
> +	if (AG71XX_TYPE_AR9331_GE0 == cfg->type)
> +		return 0;
> +
> +	/*
> +	 * Check for previous transactions are complete. Added to avoid
> +	 * race condition while running at higher frequencies.
> +	 */
> +	do {
> +		udelay(5);
> +		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
> +	} while (rddata && --ii);
> +
> +	if (ii == 0)
> +		printk("ERROR:%s:%d transaction failed\n", __func__, __LINE__);
> +
> +	ag71xx_wr(priv, AG71XX_REG_MII_ADDR, addr);
> +	ag71xx_wr(priv, AG71XX_REG_MII_CTRL, val);
> +
> +	do {
> +		rddata = ag71xx_rr(priv, AG71XX_REG_MII_IND) & MII_IND_BUSY;
> +	} while (rddata && --ii);
> +
> +	if (ii == 0)
> +		printk("Error!!! Leave ag7240_miiphy_write without polling correct status!\n");
> +
>  	return 0;
>  }
>  
> @@ -372,6 +464,13 @@ static int ag71xx_ether_send(struct eth_device *edev, void *packet, int length)
>  
>  static int ag71xx_ether_open(struct eth_device *edev)
>  {
> +	struct ag71xx *priv = edev->priv;
> +	const struct ag71xx_cfg *cfg = priv->cfg;
> +
> +	if (AG71XX_TYPE_AR9344_GMAC0 == cfg->type)
> +		return phy_device_connect(edev, &priv->miibus, 0,
> +			NULL, 0, PHY_INTERFACE_MODE_RGMII_TXID);
> +
>  	return 0;
>  }
>  
> @@ -408,25 +507,63 @@ static int ag71xx_ether_init(struct eth_device *edev)
>  	return 1;
>  }
>  
> -static int ag71xx_mii_setup(struct ag71xx *priv)
> +static void ag71xx_ar9331_ge0_mii_init(struct ag71xx *priv)
>  {
>  	u32 rd;
>  
> -	rd = ag71xx_gmac_rr(priv, 0);
> +	rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
> +	rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_10_100);
> +	ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
> +
> +	/* config FIFOs */
> +	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
> +
> +	rd = ag71xx_gmac_rr(priv, AG71XX_REG_MAC_CFG1);
>  	rd |= AG71XX_ETH_CFG_MII_GE0_SLAVE;
>  	ag71xx_gmac_wr(priv, 0, rd);
> +}
>  
> -	return 0;
> +static void ag71xx_ar9344_gmac0_mii_init(struct ag71xx *priv)
> +{
> +	u32 rd;
> +
> +	rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
> +	rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_1000);
> +	ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
> +
> +	/* config FIFOs */
> +	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
> +
> +	ag71xx_gmac_wr(priv, AG71XX_REG_MAC_CFG1, 1);
> +	udelay(1000);
> +	ag71xx_wr(priv, AG71XX_REG_MII_CFG, 4 | (1 << 31));
> +	ag71xx_wr(priv, AG71XX_REG_MII_CFG, 4);
>  }
>  
> +static struct ag71xx_cfg ag71xx_cfg_ar9331_ge0 = {
> +	.type = AG71XX_TYPE_AR9331_GE0,
> +	.init_mii = ag71xx_ar9331_ge0_mii_init,
> +};
> +
> +static struct ag71xx_cfg ag71xx_cfg_ar9344_gmac0 = {
> +	.type = AG71XX_TYPE_AR9344_GMAC0,
> +	.init_mii = ag71xx_ar9344_gmac0_mii_init,
> +};
> +
>  static int ag71xx_probe(struct device_d *dev)
>  {
>  	void __iomem *regs, *regs_gmac;
>  	struct mii_bus *miibus;
>  	struct eth_device *edev;
> +	struct ag71xx_cfg *cfg;
>  	struct ag71xx *priv;
>  	u32 mac_h, mac_l;
> -	u32 rd;
> +	u32 rd, mask;
> +	int ret;
> +
> +	ret = dev_get_drvdata(dev, (const void **)&cfg);
> +	if (ret)
> +		return ret;
>  
>  	regs_gmac = dev_request_mem_region_by_name(dev, "gmac");
>  	if (IS_ERR(regs_gmac))
> @@ -452,41 +589,42 @@ static int ag71xx_probe(struct device_d *dev)
>  	priv->dev = dev;
>  	priv->regs = regs;
>  	priv->regs_gmac = regs_gmac;
> +	priv->cfg = cfg;
>  
>  	miibus->read = ag71xx_ether_mii_read;
>  	miibus->write = ag71xx_ether_mii_write;
>  	miibus->priv = priv;
>  
>  	/* enable switch core */
> -	rd = __raw_readl((char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG)) & ~(0x1f);
> +	rd = ar7240_reg_rd(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG);
> +	rd &= ~(0x1f);
>  	rd |= 0x10;
> -	__raw_writel(rd, (char *)KSEG1ADDR(AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG));
> +	if ((ar7240_reg_rd(WASP_BOOTSTRAP_REG) & WASP_REF_CLK_25) == 0)
> +		rd |= 0x1;
> +	ar7240_reg_wr((AR71XX_PLL_BASE + AR933X_ETHSW_CLOCK_CONTROL_REG), rd);
>  
>  	if (ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE) != 0)
>  		ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, 0);
>  
>  	/* reset GE0 MAC and MDIO */
> +	mask = AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO
> +		| AR933X_RESET_SWITCH;
> +
>  	rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
> -	rd |= AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH;
> +	rd |= mask;
>  	ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
>  	mdelay(100);
>  
>  	rd = ath79_reset_rr(AR933X_RESET_REG_RESET_MODULE);
> -	rd &= ~(AR933X_RESET_GE0_MAC | AR933X_RESET_GE0_MDIO | AR933X_RESET_SWITCH);
> +	rd &= ~(mask);

This mask handling looks like a cleanup that should be in another patch.

>  	ath79_reset_wr(AR933X_RESET_REG_RESET_MODULE, rd);
>  	mdelay(100);
>  
>  	ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_SR | MAC_CFG1_TX_RST | MAC_CFG1_RX_RST));
>  	ag71xx_wr(priv, AG71XX_REG_MAC_CFG1, (MAC_CFG1_RXE | MAC_CFG1_TXE));
>  
> -	rd = ag71xx_rr(priv, AG71XX_REG_MAC_CFG2);
> -	rd |= (MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK | MAC_CFG2_IF_10_100);
> -	ag71xx_wr(priv, AG71XX_REG_MAC_CFG2, rd);
> -
> -	/* config FIFOs */
> -	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG0, 0x1f00);
> -
> -	ag71xx_mii_setup(priv);
> +	if (cfg->init_mii)
> +		cfg->init_mii(priv);
>  
>  	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG1, 0x10ffff);
>  	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG2, 0xAAA0555);
> @@ -497,8 +635,10 @@ static int ag71xx_probe(struct device_d *dev)
>  	ag71xx_wr(priv, AG71XX_REG_FIFO_CFG3, 0x1f00140);
>  
>  	priv->rx_buffer = xmemalign(PAGE_SIZE, NO_OF_RX_FIFOS * MAX_RBUFF_SZ);
> -	priv->fifo_tx = dma_alloc_coherent(NO_OF_TX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
> -	priv->fifo_rx = dma_alloc_coherent(NO_OF_RX_FIFOS * sizeof(ag7240_desc_t), DMA_ADDRESS_BROKEN);
> +	priv->fifo_tx = dma_alloc_coherent(NO_OF_TX_FIFOS * sizeof(ag7240_desc_t),
> +					   &priv->addr_tx);
> +	priv->fifo_rx = dma_alloc_coherent(NO_OF_RX_FIFOS * sizeof(ag7240_desc_t),
> +					   &priv->addr_rx);

I think this change deserves an extra patch.

>  	priv->next_tx = 0;
>  
>  	mac_l = 0x3344;
> @@ -516,11 +656,9 @@ static int ag71xx_probe(struct device_d *dev)
>  }
>  
>  static __maybe_unused struct of_device_id ag71xx_dt_ids[] = {
> -	{
> -		.compatible = "qca,ar7100-gmac",
> -	}, {
> -		/* sentinel */
> -	}
> +	{ .compatible = "qca,ar9331-ge0", .data = &ag71xx_cfg_ar9331_ge0, },
> +	{ .compatible = "qca,ar9344-gmac0", .data = &ag71xx_cfg_ar9344_gmac0, },

Why do you remove the original compatible string here?

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH v1 02/10] MIPS: dts: ar9331: update compatible for mac0 node

[Sascha Hauer]

On Sun, Aug 27, 2017 at 09:02:22AM +0200, Oleksij Rempel wrote:
> MACs on same chip are too different to have one common compatible

I see. Please put the driver change into this patch for bisectability.

Sascha

> 
> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
> ---
>  arch/mips/dts/ar9331.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/dts/ar9331.dtsi b/arch/mips/dts/ar9331.dtsi
> index 109af8664..b4b8b766b 100644
> --- a/arch/mips/dts/ar9331.dtsi
> +++ b/arch/mips/dts/ar9331.dtsi
> @@ -1,7 +1,7 @@
>  / {
>  	ahb {
>  		mac0: mac@19000000 {
> -			compatible = "qca,ar7100-gmac", "qca,ar9331-gmac";
> +			compatible = "qca,ar9331-ge0";
>  			reg = <0x18070000 0x00000100>,
>  			      <0x19000000 0x01000000>;
>  			reg-names = "gmac", "ge0";
> -- 
> 2.11.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH v1 07/10] add phy: ar8327 driver

[Sascha Hauer]

On Sun, Aug 27, 2017 at 09:02:27AM +0200, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
> ---
>  drivers/net/phy/Kconfig  |   5 +
>  drivers/net/phy/Makefile |   1 +
>  drivers/net/phy/ar8327.c | 276 +++++++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 282 insertions(+)
>  create mode 100644 drivers/net/phy/ar8327.c
> 
> diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
> index d30f65b8e..ea2e06265 100644
> --- a/drivers/net/phy/Kconfig
> +++ b/drivers/net/phy/Kconfig
> @@ -8,6 +8,11 @@ if PHYLIB
>  
>  comment "MII PHY device drivers"
>  
> +config AR8327N_PHY
> +	bool "Driver for QCA AR8327N PHYs"
> +	---help---
> +	  Currently supports the AR8327N PHY.
> +
>  config AT803X_PHY
>  	bool "Driver for Atheros AT803X PHYs"
>  	---help---
> diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
> index 10732f807..13b8f6545 100644
> --- a/drivers/net/phy/Makefile
> +++ b/drivers/net/phy/Makefile
> @@ -1,4 +1,5 @@
>  obj-y += phy.o mdio_bus.o
> +obj-$(CONFIG_AR8327N_PHY)	+= ar8327.o
>  obj-$(CONFIG_AT803X_PHY)	+= at803x.o
>  obj-$(CONFIG_LXT_PHY)		+= lxt.o
>  obj-$(CONFIG_MARVELL_PHY)	+= marvell.o
> diff --git a/drivers/net/phy/ar8327.c b/drivers/net/phy/ar8327.c
> new file mode 100644
> index 000000000..647871283
> --- /dev/null
> +++ b/drivers/net/phy/ar8327.c
> @@ -0,0 +1,276 @@
> +/*
> + * Copyright (C) 2017 Oleksij Rempel <linux@rempel-privat.de>
> + *
> + * This program is free software; you can redistribute  it and/or modify it
> + * under  the terms of  the GNU General  Public License as published by the
> + * Free Software Foundation;  either version 2 of the  License, or (at your
> + * option) any later version.
> + */
> +
> +#include <common.h>
> +#include <init.h>
> +#include <linux/phy.h>
> +#include <linux/string.h>
> +
> +#define ATHR_PHY_MAX	5
> +
> +/*****************/
> +/* PHY Registers */
> +/*****************/
> +#define ATHR_PHY_CONTROL			0x00
> +#define ATHR_PHY_STATUS				0x01
> +#define ATHR_PHY_ID1				0x02
> +#define ATHR_PHY_ID2				0x03
> +#define ATHR_AUTONEG_ADVERT			0x04
> +#define ATHR_LINK_PARTNER_ABILITY		0x05
> +#define ATHR_AUTONEG_EXPANSION			0x06
> +#define ATHR_NEXT_PAGE_TRANSMIT			0x07
> +#define ATHR_LINK_PARTNER_NEXT_PAGE		0x08
> +#define ATHR_1000BASET_CONTROL			0x09
> +#define ATHR_1000BASET_STATUS			0x0a
> +#define ATHR_PHY_SPEC_CONTROL			0x10
> +#define ATHR_PHY_SPEC_STATUS			0x11
> +#define ATHR_DEBUG_PORT_ADDRESS			0x1d
> +#define ATHR_DEBUG_PORT_DATA			0x1e
> +
> +/* Advertisement register. */
> +#define ATHR_ADVERTISE_ASYM_PAUSE		0x0800
> +#define ATHR_ADVERTISE_PAUSE			0x0400
> +#define ATHR_ADVERTISE_100FULL			0x0100
> +#define ATHR_ADVERTISE_100HALF			0x0080
> +#define ATHR_ADVERTISE_10FULL			0x0040
> +#define ATHR_ADVERTISE_10HALF			0x0020
> +
> +#define ATHR_ADVERTISE_ALL (ATHR_ADVERTISE_ASYM_PAUSE | ATHR_ADVERTISE_PAUSE | \
> +                            ATHR_ADVERTISE_10HALF | ATHR_ADVERTISE_10FULL | \
> +                            ATHR_ADVERTISE_100HALF | ATHR_ADVERTISE_100FULL)
> +
> +/* ATHR_PHY_CONTROL fields */
> +#define ATHR_CTRL_SOFTWARE_RESET		0x8000
> +#define ATHR_CTRL_AUTONEGOTIATION_ENABLE	0x1000
> +
> +/* 1000BASET_CONTROL */
> +#define ATHR_ADVERTISE_1000FULL			0x0200
> +
> +/* Phy Specific status fields */
> +#define ATHR_STATUS_LINK_PASS			0x0400
> +
> +static u32 ar8327n_reg_read(struct phy_device *phydev, u32 reg_addr)
> +{
> +	u32 reg_word_addr;
> +	u32 phy_addr, tmp_val, reg_val;
> +	u16 phy_val;
> +	u8 phy_reg;
> +
> +	/* change reg_addr to 16-bit word address, 32-bit aligned */
> +	reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
> +
> +	/* configure register high address */
> +	phy_addr = 0x18;
> +	phy_reg = 0x0;
> +	phy_val = (u16) ((reg_word_addr >> 8) & 0x1ff);  /* bit16-8 of reg address */
> +	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
> +
> +	/* For some registers such as MIBs, since it is read/clear, we should */
> +	/* read the lower 16-bit register then the higher one */
> +
> +	/* read register in lower address */
> +	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
> +	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
> +	reg_val = (u32) mdiobus_read(phydev->bus, phy_addr, phy_reg);
> +
> +	/* read register in higher address */
> +	reg_word_addr++;
> +	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
> +	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
> +	reg_val = (u32) mdiobus_read(phydev->bus, phy_addr, phy_reg);
> +	reg_val |= (tmp_val << 16);
> +
> +	return reg_val;
> +}
> +
> +static void ar8327n_reg_write(struct phy_device *phydev, u32 reg_addr,
> +			      u32 reg_val)
> +{
> +	u32 reg_word_addr;
> +	u32 phy_addr;
> +	u16 phy_val;
> +	u8 phy_reg;
> +
> +	/* change reg_addr to 16-bit word address, 32-bit aligned */
> +	reg_word_addr = (reg_addr & 0xfffffffc) >> 1;
> +
> +	/* configure register high address */
> +	phy_addr = 0x18;
> +	phy_reg = 0x0;
> +	phy_val = (u16) ((reg_word_addr >> 8) & 0x1ff);  /* bit16-8 of reg address */
> +	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
> +
> +	/* For some registers such as ARL and VLAN, since they include BUSY bit */
> +	/* in lower address, we should write the higher 16-bit register then the */
> +	/* lower one */
> +
> +	/* read register in higher address */
> +	reg_word_addr++;
> +	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
> +	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
> +	phy_val = (u16) ((reg_val >> 16) & 0xffff);
> +	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
> +
> +	/* write register in lower address */
> +	reg_word_addr--;
> +	phy_addr = 0x10 | ((reg_word_addr >> 5) & 0x7); /* bit7-5 of reg address */
> +	phy_reg = (u8) (reg_word_addr & 0x1f);   /* bit4-0 of reg address */
> +	phy_val = (u16) (reg_val & 0xffff);
> +	mdiobus_write(phydev->bus,  phy_addr, phy_reg, phy_val);
> +}
> +
> +static int ar8327n_phy_is_link_alive(struct phy_device *phydev, int phy_addr)
> +{
> +	u16 val;
> +
> +	val = mdiobus_read(phydev->bus, phy_addr, ATHR_PHY_SPEC_STATUS);
> +
> +	return !!(val & ATHR_STATUS_LINK_PASS);
> +}
> +
> +static int ar8327n_phy_setup(struct phy_device *phydev)
> +{
> +	int phy_addr;
> +
> +	/* start auto negotiation on each phy */
> +	for (phy_addr = 0; phy_addr < ATHR_PHY_MAX; phy_addr++) {
> +		mdiobus_write(phydev->bus, phy_addr, ATHR_AUTONEG_ADVERT,
> +			      ATHR_ADVERTISE_ALL);
> +
> +		mdiobus_write(phydev->bus, phy_addr, ATHR_1000BASET_CONTROL,
> +			      ATHR_ADVERTISE_1000FULL);
> +
> +		/* Reset PHYs*/
> +		mdiobus_write(phydev->bus, phy_addr, ATHR_PHY_CONTROL,
> +			      ATHR_CTRL_AUTONEGOTIATION_ENABLE
> +			      | ATHR_CTRL_SOFTWARE_RESET);
> +	}
> +
> +	/*
> +	 * After the phy is reset, it takes a little while before
> +	 * it can respond properly.
> +	 */
> +	mdelay(1000);
> +
> +	for (phy_addr = 0; phy_addr < ATHR_PHY_MAX; phy_addr++) {
> +		int count;
> +
> +		for (count = 20; count > 0; count--) {
> +			u16 val;
> +			val = mdiobus_read(phydev->bus, phy_addr,
> +					   ATHR_PHY_CONTROL);
> +
> +			if (!(val & ATHR_CTRL_SOFTWARE_RESET))
> +				break;
> +
> +			mdelay(150);
> +		}
> +
> +		if (!count)
> +			printk("Port %d, Negotiation timeout\n", phy_addr);

Port %d of what device?? dev_* functions really make it easy to add
helpful context to such messages.

> +	}
> +
> +	return 0;
> +}
> +
> +static int ar8327n_get_link(struct phy_device *phydev)
> +{
> +	int phy_addr;
> +	int live_links = 0;
> +
> +	for (phy_addr = 0; phy_addr < ATHR_PHY_MAX; phy_addr++) {
> +		if (ar8327n_phy_is_link_alive(phydev, phy_addr))
> +			live_links++;
> +	}
> +
> +	return (live_links > 0);
> +}
> +
> +static int ar8327n_config_init(struct phy_device *phydev)
> +{
> +	int phy_addr = 0;
> +
> +	if (phydev->interface != PHY_INTERFACE_MODE_RGMII_TXID)
> +		return 0;
> +
> +	/* if using header for register configuration, we have to     */
> +	/* configure s17 register after frame transmission is enabled */
> +
> +	/* configure the RGMII */
> +	ar8327n_reg_write(phydev, 0x624, 0x7f7f7f7f);
> +	ar8327n_reg_write(phydev, 0x10, 0x40000000);
> +	ar8327n_reg_write(phydev, 0x4, 0x07600000);
> +	ar8327n_reg_write(phydev, 0xc, 0x01000000);
> +	ar8327n_reg_write(phydev, 0x7c, 0x0000007e);
> +
> +	/* AR8327/AR8328 v1.0 fixup */
> +	if ((ar8327n_reg_read(phydev, 0x0) & 0xffff) == 0x1201) {
> +		/* TODO v1.0 seems to be something special. Currently not tested */
> +		printk("!!! phy versio v1.0 is detected!! \n");

s/versio/version/. Also the usual printk/dev_* beefing. It would be nice
if you could give the user a hint that this path is untested.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [PATCH v1 08/10] rename tplink devicetree

[Sascha Hauer]

On Sun, Aug 27, 2017 at 09:02:28AM +0200, Oleksij Rempel wrote:
> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
> ---
>  arch/mips/configs/tplink-wdr4300_defconfig                          | 2 +-
>  arch/mips/dts/{ar9344_tl_wdr4300.dts => ar9344-tl-wdr4300-v1.7.dts} | 4 ++--
>  2 files changed, 3 insertions(+), 3 deletions(-)
>  rename arch/mips/dts/{ar9344_tl_wdr4300.dts => ar9344-tl-wdr4300-v1.7.dts} (91%)

Why do you rename it? The answer should be in the commit message.

Sascha

> 
> diff --git a/arch/mips/configs/tplink-wdr4300_defconfig b/arch/mips/configs/tplink-wdr4300_defconfig
> index 63189b754..b5be221f6 100644
> --- a/arch/mips/configs/tplink-wdr4300_defconfig
> +++ b/arch/mips/configs/tplink-wdr4300_defconfig
> @@ -1,5 +1,5 @@
>  CONFIG_BUILTIN_DTB=y
> -CONFIG_BUILTIN_DTB_NAME="ar9344_tl_wdr4300"
> +CONFIG_BUILTIN_DTB_NAME="ar9344-tl-wdr4300-v1.7"
>  CONFIG_MACH_MIPS_ATH79=y
>  CONFIG_BOARD_TPLINK_WDR4300=y
>  CONFIG_PBL_IMAGE=y
> diff --git a/arch/mips/dts/ar9344_tl_wdr4300.dts b/arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
> similarity index 91%
> rename from arch/mips/dts/ar9344_tl_wdr4300.dts
> rename to arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
> index 139717a6b..d16cab005 100644
> --- a/arch/mips/dts/ar9344_tl_wdr4300.dts
> +++ b/arch/mips/dts/ar9344-tl-wdr4300-v1.7.dts
> @@ -6,8 +6,8 @@
>  #include "ar9344.dtsi"
>  
>  / {
> -	model = "TP-Link WDR4300";
> -	compatible = "tplink,tl-wdr4300";
> +	model = "TP-Link WDR4300 v1.7";
> +	compatible = "tplink,tl-wdr4300", "tplink,tl-wdr4300-v1.7";
>  
>  	aliases {
>  		serial0 = &uart0;
> -- 
> 2.11.0
> 
> 
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-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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