From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v2 03/19] include: Port linux/bitfield.h from Linux kernel
Date: Mon, 16 Apr 2018 12:31:41 -0700 [thread overview]
Message-ID: <20180416193157.16094-4-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180416193157.16094-1-andrew.smirnov@gmail.com>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
include/linux/bitfield.h | 152 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 152 insertions(+)
create mode 100644 include/linux/bitfield.h
diff --git a/include/linux/bitfield.h b/include/linux/bitfield.h
new file mode 100644
index 000000000..cf2588d81
--- /dev/null
+++ b/include/linux/bitfield.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (C) 2014 Felix Fietkau <nbd@nbd.name>
+ * Copyright (C) 2004 - 2009 Ivo van Doorn <IvDoorn@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _LINUX_BITFIELD_H
+#define _LINUX_BITFIELD_H
+
+#include <linux/build_bug.h>
+#include <asm/byteorder.h>
+
+/*
+ * Bitfield access macros
+ *
+ * FIELD_{GET,PREP} macros take as first parameter shifted mask
+ * from which they extract the base mask and shift amount.
+ * Mask must be a compilation time constant.
+ *
+ * Example:
+ *
+ * #define REG_FIELD_A GENMASK(6, 0)
+ * #define REG_FIELD_B BIT(7)
+ * #define REG_FIELD_C GENMASK(15, 8)
+ * #define REG_FIELD_D GENMASK(31, 16)
+ *
+ * Get:
+ * a = FIELD_GET(REG_FIELD_A, reg);
+ * b = FIELD_GET(REG_FIELD_B, reg);
+ *
+ * Set:
+ * reg = FIELD_PREP(REG_FIELD_A, 1) |
+ * FIELD_PREP(REG_FIELD_B, 0) |
+ * FIELD_PREP(REG_FIELD_C, c) |
+ * FIELD_PREP(REG_FIELD_D, 0x40);
+ *
+ * Modify:
+ * reg &= ~REG_FIELD_C;
+ * reg |= FIELD_PREP(REG_FIELD_C, c);
+ */
+
+#define __bf_shf(x) (__builtin_ffsll(x) - 1)
+
+#define __BF_FIELD_CHECK(_mask, _reg, _val, _pfx) \
+ ({ \
+ BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
+ _pfx "mask is not constant"); \
+ BUILD_BUG_ON_MSG(!(_mask), _pfx "mask is zero"); \
+ BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
+ ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
+ _pfx "value too large for the field"); \
+ BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
+ _pfx "type of reg too small for mask"); \
+ __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
+ (1ULL << __bf_shf(_mask))); \
+ })
+
+/**
+ * FIELD_FIT() - check if value fits in the field
+ * @_mask: shifted mask defining the field's length and position
+ * @_val: value to test against the field
+ *
+ * Return: true if @_val can fit inside @_mask, false if @_val is too big.
+ */
+#define FIELD_FIT(_mask, _val) \
+ ({ \
+ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_FIT: "); \
+ !((((typeof(_mask))_val) << __bf_shf(_mask)) & ~(_mask)); \
+ })
+
+/**
+ * FIELD_PREP() - prepare a bitfield element
+ * @_mask: shifted mask defining the field's length and position
+ * @_val: value to put in the field
+ *
+ * FIELD_PREP() masks and shifts up the value. The result should
+ * be combined with other fields of the bitfield using logical OR.
+ */
+#define FIELD_PREP(_mask, _val) \
+ ({ \
+ __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \
+ ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \
+ })
+
+/**
+ * FIELD_GET() - extract a bitfield element
+ * @_mask: shifted mask defining the field's length and position
+ * @_reg: value of entire bitfield
+ *
+ * FIELD_GET() extracts the field specified by @_mask from the
+ * bitfield passed in as @_reg by masking and shifting it down.
+ */
+#define FIELD_GET(_mask, _reg) \
+ ({ \
+ __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
+ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
+ })
+
+extern void __compiletime_warning("value doesn't fit into mask")
+__field_overflow(void);
+extern void __compiletime_error("bad bitfield mask")
+__bad_mask(void);
+static __always_inline u64 field_multiplier(u64 field)
+{
+ if ((field | (field - 1)) & ((field | (field - 1)) + 1))
+ __bad_mask();
+ return field & -field;
+}
+static __always_inline u64 field_mask(u64 field)
+{
+ return field / field_multiplier(field);
+}
+#define ____MAKE_OP(type,base,to,from) \
+static __always_inline __##type type##_encode_bits(base v, base field) \
+{ \
+ if (__builtin_constant_p(v) && (v & ~field_multiplier(field))) \
+ __field_overflow(); \
+ return to((v & field_mask(field)) * field_multiplier(field)); \
+} \
+static __always_inline __##type type##_replace_bits(__##type old, \
+ base val, base field) \
+{ \
+ return (old & ~to(field)) | type##_encode_bits(val, field); \
+} \
+static __always_inline void type##p_replace_bits(__##type *p, \
+ base val, base field) \
+{ \
+ *p = (*p & ~to(field)) | type##_encode_bits(val, field); \
+} \
+static __always_inline base type##_get_bits(__##type v, base field) \
+{ \
+ return (from(v) & field)/field_multiplier(field); \
+}
+#define __MAKE_OP(size) \
+ ____MAKE_OP(le##size,u##size,cpu_to_le##size,le##size##_to_cpu) \
+ ____MAKE_OP(be##size,u##size,cpu_to_be##size,be##size##_to_cpu) \
+ ____MAKE_OP(u##size,u##size,,)
+__MAKE_OP(16)
+__MAKE_OP(32)
+__MAKE_OP(64)
+#undef __MAKE_OP
+#undef ____MAKE_OP
+
+#endif
--
2.14.3
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next prev parent reply other threads:[~2018-04-16 19:32 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-04-16 19:31 [PATCH v2 00/19] i.MX bootsource bugfixes, refactoring and VFxxx support Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 01/19] ARM: i.MX: boot: Coalesce copy-pasted code Andrey Smirnov
2018-04-17 6:58 ` Sascha Hauer
2018-04-17 15:20 ` Andrey Smirnov
2018-04-18 8:15 ` Sascha Hauer
2018-04-19 22:26 ` Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 02/19] include: Port linux/build_bug.h from Linux kernel Andrey Smirnov
2018-04-16 19:31 ` Andrey Smirnov [this message]
2018-04-16 19:31 ` [PATCH v2 04/19] ARM: i.MX: Add a function to extract BMOD value Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 05/19] ARM: i.MX: Simplify serial bootsource detection for i.MX6 and 7 Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 06/19] ARM: i.MX: Account for unprogrammed fuses on i.MX6 and i.MX7 Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 07/19] ARM: i.MX7: boot: Add code to handle SD/MMC manufacture mode Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 08/19] ARM: i.MX7: boot: Remove incorrect NAND bootsource detection Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 09/19] ARM: i.MX7: boot: Fix SPI-NOR/QSPI boot source mixup Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 10/19] ARM: i.MX: boot: Remove unnecessary returns Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 11/19] ARM: i.MX: boot: Move magic values into small functions Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 12/19] ARM: i.MX: boot: Share code to detect NAND as a boot source Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 13/19] ARM: i.MX: boot: Check for NAND boot only if necessary on i.MX53, 6 Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 14/19] ARM: i.MX53: boot: Move magic numbers info utility functions Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 15/19] ARM: i.MX6: boot: Move magic numbers into " Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 16/19] ARM: i.MX7: " Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 17/19] bootsource: Add BOOTSOURCE_CAN Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 18/19] ARM: VFxxx: Implement code to detect bootsource Andrey Smirnov
2018-04-16 19:31 ` [PATCH v2 19/19] ARM: i.MX6: boot: Return BOOTSOURCE_SPI_NOR, not BOOTSOURCE_SPI Andrey Smirnov
2018-04-17 7:24 ` [PATCH v2 00/19] i.MX bootsource bugfixes, refactoring and VFxxx support Sascha Hauer
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