[RFC PATCH 00/15] MIPS64 support

[RFC PATCH 00/15] MIPS64 support

[Peter Mamonov]

Hi,

Recently I've resolved a couple of issues that prevented 64bit Barebox from 
running on MIPS64 CPUs. By the way, 32bit Barebox runs on MIPS64 without any 
issues, since MIPS64 supports 32 bit addressing mode. Here is a relevant patch 
series.  This is mostly for discussion, yet some patches can be applied as is.  
Please, give your comments.

Regards,
Peter

Peter Mamonov (15):
  FIXME: add t4..t7 definitions for MIPS64
  MIPS: use CKSEG1 instead of KSEG1
  FIXME: mips: fix copy_to_link_location for 64 bit mode
  mips: fix warnings from CPHYSADDR() macro
  mips: fix dma_sync_* stuff for MIPS64
  common/Kconfig: add PHYS_ADDR_T_64BIT option
  mips: 64BIT selects PHYS_ADDR_T_64BIT
  fixup! MIPS: import optimized string functions from Linux
  MIPS: import 64-bit address conversion macros
  common.h: fix IOMEM() for MIPS64
  resource: fix iomem root resource for 64 bit
  FIXME: commands/mem: fix /dev/mem size
  FIXME: fs: fix memory access for 64bit MIPS
  mtd: cfi-flash: fix write_buff() for 64BIT
  i2c/muxes/i2c-mux-pca954x: fix private data retrieval for 64bit mode

 arch/mips/Kconfig                   |  2 ++
 arch/mips/boot/dtb.c                |  4 ++--
 arch/mips/include/asm/addrspace.h   | 25 +++++++++++++++++++++++++
 arch/mips/include/asm/dma-mapping.h |  2 +-
 arch/mips/include/asm/io.h          |  4 ++--
 arch/mips/include/asm/pbl_macros.h  | 24 ++++++++++++++++--------
 arch/mips/include/asm/regdef.h      |  4 ++++
 arch/mips/lib/c-r4k.c               | 26 +++++++++++++-------------
 arch/mips/lib/dma-default.c         |  6 ++++--
 commands/mem.c                      |  2 +-
 common/Kconfig                      |  3 +++
 common/resource.c                   |  4 ++++
 drivers/i2c/muxes/i2c-mux-pca954x.c |  4 +++-
 drivers/mtd/nor/cfi_flash.c         |  2 +-
 fs/fs.c                             |  6 ------
 include/common.h                    |  4 ++++
 16 files changed, 85 insertions(+), 37 deletions(-)

-- 
2.17.0


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[RFC PATCH 01/15] FIXME: add t4..t7 definitions for MIPS64

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/include/asm/regdef.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/mips/include/asm/regdef.h b/arch/mips/include/asm/regdef.h
index 7c8ecb6b9..5a31ea022 100644
--- a/arch/mips/include/asm/regdef.h
+++ b/arch/mips/include/asm/regdef.h
@@ -66,12 +66,16 @@
 #define a3	$7
 #define a4	$8	/* arg reg 64 bit; caller saved in 32 bit */
 #define ta0	$8
+#define t4	$8
 #define a5	$9
 #define ta1	$9
+#define t5	$9
 #define a6	$10
 #define ta2	$10
+#define t6	$10
 #define a7	$11
 #define ta3	$11
+#define t7	$11
 #define t0	$12	/* caller saved */
 #define t1	$13
 #define t2	$14
-- 
2.17.0


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[RFC PATCH 02/15] MIPS: use CKSEG1 instead of KSEG1

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/boot/dtb.c  | 4 ++--
 arch/mips/lib/c-r4k.c | 8 ++++----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/mips/boot/dtb.c b/arch/mips/boot/dtb.c
index e7633a5af..3f7f46641 100644
--- a/arch/mips/boot/dtb.c
+++ b/arch/mips/boot/dtb.c
@@ -30,10 +30,10 @@ void of_add_memory_bank(struct device_node *node, bool dump, int r,
 
 	if (IS_ENABLED(CONFIG_MMU)) {
 		sprintf(str, "kseg0_ram%d", r);
-		barebox_add_memory_bank(str, KSEG0 | base, size);
+		barebox_add_memory_bank(str, CKSEG0 | base, size);
 	} else {
 		sprintf(str, "kseg1_ram%d", r);
-		barebox_add_memory_bank(str, KSEG1 | base, size);
+		barebox_add_memory_bank(str, CKSEG1 | base, size);
 	}
 
 	if (dump)
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index 150205840..cb0544a53 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -58,14 +58,14 @@ void flush_cache_all(void)
 
 	dcache_size = c->dcache.waysize * c->dcache.ways;
 	lsize = c->dcache.linesz;
-	aend = (KSEG0 + dcache_size - 1) & ~(lsize - 1);
-	for (addr = KSEG0; addr <= aend; addr += lsize)
+	aend = (CKSEG0 + dcache_size - 1) & ~(lsize - 1);
+	for (addr = CKSEG0; addr <= aend; addr += lsize)
 		cache_op(Index_Writeback_Inv_D, addr);
 
 	icache_size = c->icache.waysize * c->icache.ways;
 	lsize = c->icache.linesz;
-	aend = (KSEG0 + icache_size - 1) & ~(lsize - 1);
-	for (addr = KSEG0; addr <= aend; addr += lsize)
+	aend = (CKSEG0 + icache_size - 1) & ~(lsize - 1);
+	for (addr = CKSEG0; addr <= aend; addr += lsize)
 		cache_op(Index_Invalidate_I, addr);
 
 	/* secondatory cache skipped */
-- 
2.17.0


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[RFC PATCH 03/15] FIXME: mips: fix copy_to_link_location for 64 bit mode

[Peter Mamonov]

A better solution: use 4 instead of LONGSIZE

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/include/asm/pbl_macros.h | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/arch/mips/include/asm/pbl_macros.h b/arch/mips/include/asm/pbl_macros.h
index 37b150ac2..8950b400d 100644
--- a/arch/mips/include/asm/pbl_macros.h
+++ b/arch/mips/include/asm/pbl_macros.h
@@ -134,17 +134,25 @@
 	subu	t2, t1, t0	/* t2 <- size of pbl */
 	addu	a2, a0, t2	/* a2 <- source end address */
 
+#if (LONGSIZE == 4)
+#define LW	lw
+#define SW	sw
+#endif
+#if (LONGSIZE == 8)
+#define LW	ld
+#define SW	sd
+#endif
 copy_loop:
 	/* copy from source address [a0] */
-	lw	t4, LONGSIZE * 0(a0)
-	lw	t5, LONGSIZE * 1(a0)
-	lw	t6, LONGSIZE * 2(a0)
-	lw	t7, LONGSIZE * 3(a0)
+	LW	t4, LONGSIZE * 0(a0)
+	LW	t5, LONGSIZE * 1(a0)
+	LW	t6, LONGSIZE * 2(a0)
+	LW	t7, LONGSIZE * 3(a0)
 	/* copy to target address [a1] */
-	sw	t4, LONGSIZE * 0(a1)
-	sw	t5, LONGSIZE * 1(a1)
-	sw	t6, LONGSIZE * 2(a1)
-	sw	t7, LONGSIZE * 3(a1)
+	SW	t4, LONGSIZE * 0(a1)
+	SW	t5, LONGSIZE * 1(a1)
+	SW	t6, LONGSIZE * 2(a1)
+	SW	t7, LONGSIZE * 3(a1)
 	addi	a0, LONGSIZE * 4
 	subu	t3, a0, a2
 	blez	t3, copy_loop
-- 
2.17.0


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[RFC PATCH 04/15] mips: fix warnings from CPHYSADDR() macro

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/include/asm/addrspace.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 17d480d08..04d0f95db 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -48,7 +48,12 @@
 /*
  * Returns the physical address of a CKSEGx / XKPHYS address
  */
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+#define CPHYSADDR(a)		((_ACAST64_(a)) & 0x1fffffff)
+#else
 #define CPHYSADDR(a)		((_ACAST32_(a)) & 0x1fffffff)
+#endif
+
 #define XPHYSADDR(a)            ((_ACAST64_(a)) &			\
 				 _CONST64_(0x000000ffffffffff))
 
-- 
2.17.0


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[RFC PATCH 05/15] mips: fix dma_sync_* stuff for MIPS64

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/include/asm/dma-mapping.h |  2 +-
 arch/mips/include/asm/io.h          |  4 ++--
 arch/mips/lib/c-r4k.c               | 26 +++++++++++++-------------
 arch/mips/lib/dma-default.c         |  6 ++++--
 4 files changed, 20 insertions(+), 18 deletions(-)

diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
index c71a08703..d4cbb3cac 100644
--- a/arch/mips/include/asm/dma-mapping.h
+++ b/arch/mips/include/asm/dma-mapping.h
@@ -19,7 +19,7 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
 	if (dma_handle)
 		*dma_handle = CPHYSADDR(ret);
 
-	dma_flush_range((unsigned long)ret, (unsigned long)(ret + size));
+	dma_flush_range(ret, ret + size);
 
 	return (void *)CKSEG1ADDR(ret);
 }
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 5a4cbf564..07b337e76 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -15,8 +15,8 @@
 #include <asm/addrspace.h>
 #include <asm/byteorder.h>
 
-void dma_flush_range(unsigned long, unsigned long);
-void dma_inv_range(unsigned long, unsigned long);
+void dma_flush_range(void *, void *);
+void dma_inv_range(void *, void *);
 
 /*
  *     virt_to_phys - map virtual addresses to physical
diff --git a/arch/mips/lib/c-r4k.c b/arch/mips/lib/c-r4k.c
index cb0544a53..2d652be61 100644
--- a/arch/mips/lib/c-r4k.c
+++ b/arch/mips/lib/c-r4k.c
@@ -27,12 +27,12 @@
 	: "i" (op), "R" (*(unsigned char *)(addr)))
 
 #define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop)			\
-static inline void blast_##pfx##cache##_range(unsigned long start,	\
-					      unsigned long end)	\
+static inline void blast_##pfx##cache##_range(void *start,		\
+					      void *end)		\
 {									\
-	unsigned long lsize = current_cpu_data.desc.linesz;		\
-	unsigned long addr = start & ~(lsize - 1);			\
-	unsigned long aend = (end - 1) & ~(lsize - 1);			\
+	uintptr_t lsize = current_cpu_data.desc.linesz;			\
+	void *addr = (void *)((uintptr_t)start & ~(lsize - 1));		\
+	void *aend = (void *)(((uintptr_t)end - 1) & ~(lsize - 1));	\
 									\
 	if (current_cpu_data.desc.flags & MIPS_CACHE_NOT_PRESENT)	\
 		return;							\
@@ -52,33 +52,33 @@ void flush_cache_all(void)
 {
 	struct cpuinfo_mips *c = &current_cpu_data;
 	unsigned long lsize;
-	unsigned long addr;
-	unsigned long aend;
+	void *addr;
+	void *aend;
 	unsigned int icache_size, dcache_size;
 
 	dcache_size = c->dcache.waysize * c->dcache.ways;
 	lsize = c->dcache.linesz;
-	aend = (CKSEG0 + dcache_size - 1) & ~(lsize - 1);
-	for (addr = CKSEG0; addr <= aend; addr += lsize)
+	aend = (void *)((CKSEG0 + dcache_size - 1) & ~(lsize - 1));
+	for (addr = (void *)CKSEG0; addr <= aend; addr += lsize)
 		cache_op(Index_Writeback_Inv_D, addr);
 
 	icache_size = c->icache.waysize * c->icache.ways;
 	lsize = c->icache.linesz;
-	aend = (CKSEG0 + icache_size - 1) & ~(lsize - 1);
-	for (addr = CKSEG0; addr <= aend; addr += lsize)
+	aend = (void *)((CKSEG0 + icache_size - 1) & ~(lsize - 1));
+	for (addr = (void *)CKSEG0; addr <= aend; addr += lsize)
 		cache_op(Index_Invalidate_I, addr);
 
 	/* secondatory cache skipped */
 }
 
-void dma_flush_range(unsigned long start, unsigned long end)
+void dma_flush_range(void *start, void *end)
 {
 	blast_dcache_range(start, end);
 
 	/* secondatory cache skipped */
 }
 
-void dma_inv_range(unsigned long start, unsigned long end)
+void dma_inv_range(void *start, void *end)
 {
 	blast_inv_dcache_range(start, end);
 
diff --git a/arch/mips/lib/dma-default.c b/arch/mips/lib/dma-default.c
index 71c1e423b..79d61afd8 100644
--- a/arch/mips/lib/dma-default.c
+++ b/arch/mips/lib/dma-default.c
@@ -17,9 +17,11 @@
 
 #if defined(CONFIG_CPU_MIPS32) || \
 	defined(CONFIG_CPU_MIPS64)
-static inline void __dma_sync_mips(unsigned long addr, size_t size,
+static inline void __dma_sync_mips(dma_addr_t _addr, size_t size,
 				   enum dma_data_direction direction)
 {
+	void *addr = (void *)CKSEG0ADDR(_addr);
+
 	switch (direction) {
 	case DMA_TO_DEVICE:
 		dma_flush_range(addr, addr + size);
@@ -38,7 +40,7 @@ static inline void __dma_sync_mips(unsigned long addr, size_t size,
 	}
 }
 #else
-static inline void __dma_sync_mips(void *addr, size_t size,
+static inline void __dma_sync_mips(dma_addr_t _addr, size_t size,
 	enum dma_data_direction direction)
 {
 }
-- 
2.17.0


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Re: [RFC PATCH 05/15] mips: fix dma_sync_* stuff for MIPS64

[Sascha Hauer]

On Thu, May 17, 2018 at 04:58:48PM +0300, Peter Mamonov wrote:
> Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> ---
>  arch/mips/include/asm/dma-mapping.h |  2 +-
>  arch/mips/include/asm/io.h          |  4 ++--
>  arch/mips/lib/c-r4k.c               | 26 +++++++++++++-------------
>  arch/mips/lib/dma-default.c         |  6 ++++--
>  4 files changed, 20 insertions(+), 18 deletions(-)
> 
> diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
> index c71a08703..d4cbb3cac 100644
> --- a/arch/mips/include/asm/dma-mapping.h
> +++ b/arch/mips/include/asm/dma-mapping.h
> @@ -19,7 +19,7 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
>  	if (dma_handle)
>  		*dma_handle = CPHYSADDR(ret);
>  
> -	dma_flush_range((unsigned long)ret, (unsigned long)(ret + size));
> +	dma_flush_range(ret, ret + size);
>  
>  	return (void *)CKSEG1ADDR(ret);
>  }
> diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> index 5a4cbf564..07b337e76 100644
> --- a/arch/mips/include/asm/io.h
> +++ b/arch/mips/include/asm/io.h
> @@ -15,8 +15,8 @@
>  #include <asm/addrspace.h>
>  #include <asm/byteorder.h>
>  
> -void dma_flush_range(unsigned long, unsigned long);
> -void dma_inv_range(unsigned long, unsigned long);
> +void dma_flush_range(void *, void *);
> +void dma_inv_range(void *, void *);

Why is this changed? unsigned long should normally be wide enough to
hold an address.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
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Re: [RFC PATCH 05/15] mips: fix dma_sync_* stuff for MIPS64

[Peter Mamonov]

Hi, Sascha,

On Fri, May 18, 2018 at 07:57:34AM +0200, Sascha Hauer wrote:
> On Thu, May 17, 2018 at 04:58:48PM +0300, Peter Mamonov wrote:
> > Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> > ---
> >  arch/mips/include/asm/dma-mapping.h |  2 +-
> >  arch/mips/include/asm/io.h          |  4 ++--
> >  arch/mips/lib/c-r4k.c               | 26 +++++++++++++-------------
> >  arch/mips/lib/dma-default.c         |  6 ++++--
> >  4 files changed, 20 insertions(+), 18 deletions(-)
> > 
> > diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h
> > index c71a08703..d4cbb3cac 100644
> > --- a/arch/mips/include/asm/dma-mapping.h
> > +++ b/arch/mips/include/asm/dma-mapping.h
> > @@ -19,7 +19,7 @@ static inline void *dma_alloc_coherent(size_t size, dma_addr_t *dma_handle)
> >  	if (dma_handle)
> >  		*dma_handle = CPHYSADDR(ret);
> >  
> > -	dma_flush_range((unsigned long)ret, (unsigned long)(ret + size));
> > +	dma_flush_range(ret, ret + size);
> >  
> >  	return (void *)CKSEG1ADDR(ret);
> >  }
> > diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
> > index 5a4cbf564..07b337e76 100644
> > --- a/arch/mips/include/asm/io.h
> > +++ b/arch/mips/include/asm/io.h
> > @@ -15,8 +15,8 @@
> >  #include <asm/addrspace.h>
> >  #include <asm/byteorder.h>
> >  
> > -void dma_flush_range(unsigned long, unsigned long);
> > -void dma_inv_range(unsigned long, unsigned long);
> > +void dma_flush_range(void *, void *);
> > +void dma_inv_range(void *, void *);
> 
> Why is this changed? unsigned long should normally be wide enough to
> hold an address.

You are right, it doesn't fix anything. I've made these changes after taking a 
look at __dma_sync_virtual in linux/arch/mips/mm/dma-default.c, which accepts 
void* argument. So, I decided to change call signature of __dma_sync_mips() and 
this decision triggered the rest of the edits :). Sorry for misleading commit 
message.

Regards,
Peter

> 
> Sascha
> 
> 
> -- 
> Pengutronix e.K.                           |                             |
> Industrial Linux Solutions                 | http://www.pengutronix.de/  |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
> Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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[RFC PATCH 06/15] common/Kconfig: add PHYS_ADDR_T_64BIT option

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 common/Kconfig | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/common/Kconfig b/common/Kconfig
index b7000c4d7..a5b53b2e4 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -95,6 +95,9 @@ config FILE_LIST
 config ARCH_DMA_ADDR_T_64BIT
 	bool
 
+config PHYS_ADDR_T_64BIT
+	bool
+
 config BAREBOX_UPDATE_IMX_NAND_FCB
 	bool
 	depends on ARCH_IMX6 || ARCH_IMX28
-- 
2.17.0


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[RFC PATCH 07/15] mips: 64BIT selects PHYS_ADDR_T_64BIT

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index c2c555dc3..deeda62ea 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -275,6 +275,7 @@ config 64BIT
 	bool "64-bit barebox"
 	depends on CPU_SUPPORTS_64BIT_KERNEL && SYS_SUPPORTS_64BIT_KERNEL
 	select ARCH_DMA_ADDR_T_64BIT
+	select PHYS_ADDR_T_64BIT
 	help
 	  Select this option if you want to build a 64-bit barebox.
 
-- 
2.17.0


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[RFC PATCH 08/15] fixup! MIPS: import optimized string functions from Linux

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index deeda62ea..9e8341e9f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -338,6 +338,7 @@ config NMON_HELP
 
 config MIPS_OPTIMIZED_STRING_FUNCTIONS
 	bool "use assembler optimized string functions"
+	depends on !64BIT
 	default y
 	help
 	  Say yes here to use assembler optimized memcpy / memset functions.
-- 
2.17.0


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[RFC PATCH 09/15] MIPS: import 64-bit address conversion macros

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 arch/mips/include/asm/addrspace.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 04d0f95db..688620472 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -78,6 +78,26 @@
 #define CKSEG2ADDR(a)		(CPHYSADDR(a) | CKSEG2)
 #define CKSEG3ADDR(a)		(CPHYSADDR(a) | CKSEG3)
 
+/*
+ * Cache modes for XKPHYS address conversion macros
+ */
+#define K_CALG_COH_EXCL1_NOL2	0
+#define K_CALG_COH_SHRL1_NOL2	1
+#define K_CALG_UNCACHED		2
+#define K_CALG_NONCOHERENT	3
+#define K_CALG_COH_EXCL		4
+#define K_CALG_COH_SHAREABLE	5
+#define K_CALG_NOTUSED		6
+#define K_CALG_UNCACHED_ACCEL	7
+
+/*
+ * 64-bit address conversions
+ */
+#define PHYS_TO_XKSEG_UNCACHED(p)	PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
+#define PHYS_TO_XKSEG_CACHED(p)		PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
+#define XKPHYS_TO_PHYS(p)		((p) & TO_PHYS_MASK)
+#define PHYS_TO_XKPHYS(cm, a)		(XKPHYS | (_ACAST64_(cm) << 59) | (a))
+
 #else
 
 #define CKSEG0ADDR(a)		(CPHYSADDR(a) | KSEG0)
-- 
2.17.0


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[RFC PATCH 10/15] common.h: fix IOMEM() for MIPS64

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 include/common.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/common.h b/include/common.h
index 60e5005b8..4b3bcae40 100644
--- a/include/common.h
+++ b/include/common.h
@@ -142,7 +142,11 @@ void barebox_set_hostname_no_overwrite(const char *);
 #if defined(CONFIG_MIPS)
 #include <asm/addrspace.h>
 
+#ifdef CONFIG_64BIT
+#define IOMEM(addr)	((void __force __iomem *)PHYS_TO_XKSEG_UNCACHED(addr))
+#else
 #define IOMEM(addr)	((void __force __iomem *)CKSEG1ADDR(addr))
+#endif
 #else
 #define IOMEM(addr)	((void __force __iomem *)(addr))
 #endif
-- 
2.17.0


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[RFC PATCH 11/15] resource: fix iomem root resource for 64 bit

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 common/resource.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/common/resource.c b/common/resource.c
index e4bbe15fd..1cf00a927 100644
--- a/common/resource.c
+++ b/common/resource.c
@@ -114,7 +114,11 @@ int release_region(struct resource *res)
 /* The root resource for the whole memory-mapped io space */
 struct resource iomem_resource = {
 	.start = 0,
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+	.end = -1ull,
+#else
 	.end = 0xffffffff,
+#endif
 	.name = "iomem",
 	.children = LIST_HEAD_INIT(iomem_resource.children),
 };
-- 
2.17.0


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Re: [RFC PATCH 11/15] resource: fix iomem root resource for 64 bit

[Andrey Smirnov]

On Thu, May 17, 2018 at 6:58 AM, Peter Mamonov <pmamonov@gmail.com> wrote:
> Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> ---
>  common/resource.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/common/resource.c b/common/resource.c
> index e4bbe15fd..1cf00a927 100644
> --- a/common/resource.c
> +++ b/common/resource.c
> @@ -114,7 +114,11 @@ int release_region(struct resource *res)
>  /* The root resource for the whole memory-mapped io space */
>  struct resource iomem_resource = {
>         .start = 0,
> +#ifdef CONFIG_PHYS_ADDR_T_64BIT
> +       .end = -1ull,
> +#else
>         .end = 0xffffffff,
> +#endif

Would ".end = ~(resource_size_t)0" work instead? This way you'd avoid
using preprocessor.

Thanks,
Andrey Smironv

>         .name = "iomem",
>         .children = LIST_HEAD_INIT(iomem_resource.children),
>  };
> --
> 2.17.0
>
>
> _______________________________________________
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> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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Re: [RFC PATCH 11/15] resource: fix iomem root resource for 64 bit

[Peter Mamonov]

Hi, Andrey,

On Thu, May 17, 2018 at 02:50:58PM -0700, Andrey Smirnov wrote:
> On Thu, May 17, 2018 at 6:58 AM, Peter Mamonov <pmamonov@gmail.com> wrote:
> > Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> > ---
> >  common/resource.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/common/resource.c b/common/resource.c
> > index e4bbe15fd..1cf00a927 100644
> > --- a/common/resource.c
> > +++ b/common/resource.c
> > @@ -114,7 +114,11 @@ int release_region(struct resource *res)
> >  /* The root resource for the whole memory-mapped io space */
> >  struct resource iomem_resource = {
> >         .start = 0,
> > +#ifdef CONFIG_PHYS_ADDR_T_64BIT
> > +       .end = -1ull,
> > +#else
> >         .end = 0xffffffff,
> > +#endif
> 
> Would ".end = ~(resource_size_t)0" work instead? This way you'd avoid
> using preprocessor.

Guess it should work. Thanks for the tip!

Regards,
Peter

> 
> Thanks,
> Andrey Smironv
> 
> >         .name = "iomem",
> >         .children = LIST_HEAD_INIT(iomem_resource.children),
> >  };
> > --
> > 2.17.0
> >
> >
> > _______________________________________________
> > barebox mailing list
> > barebox@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/barebox

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[RFC PATCH 12/15] FIXME: commands/mem: fix /dev/mem size

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 commands/mem.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/commands/mem.c b/commands/mem.c
index eb91ade05..80cf5c79d 100644
--- a/commands/mem.c
+++ b/commands/mem.c
@@ -96,7 +96,7 @@ static int mem_probe(struct device_d *dev)
 	dev->priv = cdev;
 
 	cdev->name = (char*)dev->resource[0].name;
-	cdev->size = (unsigned long)resource_size(&dev->resource[0]);
+	cdev->size = (loff_t)-1;
 	cdev->ops = &memops;
 	cdev->dev = dev;
 
-- 
2.17.0


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[RFC PATCH 13/15] FIXME: fs: fix memory access for 64bit MIPS

[Peter Mamonov]

Address 0xFFFFFFFFxxxxxxxx is a valid MIPS64 address.

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 fs/fs.c | 6 ------
 1 file changed, 6 deletions(-)

diff --git a/fs/fs.c b/fs/fs.c
index b66cc9b17..d4965c85e 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -962,8 +962,6 @@ loff_t lseek(int fildes, loff_t offset, int whence)
 	case SEEK_SET:
 		if (f->size != FILE_SIZE_STREAM && offset > f->size)
 			goto out;
-		if (offset < 0)
-			goto out;
 		pos = offset;
 		break;
 	case SEEK_CUR:
@@ -981,10 +979,6 @@ loff_t lseek(int fildes, loff_t offset, int whence)
 	}
 
 	pos = fsdrv->lseek(&f->fsdev->dev, f, pos);
-	if (pos < 0) {
-		errno = -pos;
-		return -1;
-	}
 
 	return pos;
 
-- 
2.17.0


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[RFC PATCH 14/15] mtd: cfi-flash: fix write_buff() for 64BIT

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 drivers/mtd/nor/cfi_flash.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/nor/cfi_flash.c b/drivers/mtd/nor/cfi_flash.c
index 5bdcccae1..01ab1aa27 100644
--- a/drivers/mtd/nor/cfi_flash.c
+++ b/drivers/mtd/nor/cfi_flash.c
@@ -515,7 +515,7 @@ static int write_buff(struct flash_info *info, const u8 *src,
 	int buffered_size;
 #endif
 	/* get lower aligned address */
-	wp = addr & ~(info->portwidth - 1);
+	wp = addr & ~((unsigned long)info->portwidth - 1);
 
 	/* handle unaligned start */
 	aln = addr - wp;
-- 
2.17.0


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[RFC PATCH 15/15] i2c/muxes/i2c-mux-pca954x: fix private data retrieval for 64bit mode

[Peter Mamonov]

Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
---
 drivers/i2c/muxes/i2c-mux-pca954x.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
index 0d5515b71..395254cdc 100644
--- a/drivers/i2c/muxes/i2c-mux-pca954x.c
+++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
@@ -180,6 +180,7 @@ static int pca954x_probe(struct device_d *dev)
 	struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent);
 	int num, force;
 	struct pca954x *data;
+	uintptr_t tmp;
 	int ret = -ENODEV;
 	int gpio;
 
@@ -203,7 +204,8 @@ static int pca954x_probe(struct device_d *dev)
 		goto exit_free;
 	}
 
-	ret = dev_get_drvdata(dev, (const void **)&data->type);
+	ret = dev_get_drvdata(dev, (const void **)&tmp);
+	data->type = tmp;
 	if (ret)
 		goto exit_free;
 
-- 
2.17.0


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Re: [RFC PATCH 15/15] i2c/muxes/i2c-mux-pca954x: fix private data retrieval for 64bit mode

[Andrey Smirnov]

On Thu, May 17, 2018 at 6:58 AM, Peter Mamonov <pmamonov@gmail.com> wrote:
> Signed-off-by: Peter Mamonov <pmamonov@gmail.com>
> ---
>  drivers/i2c/muxes/i2c-mux-pca954x.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c
> index 0d5515b71..395254cdc 100644
> --- a/drivers/i2c/muxes/i2c-mux-pca954x.c
> +++ b/drivers/i2c/muxes/i2c-mux-pca954x.c
> @@ -180,6 +180,7 @@ static int pca954x_probe(struct device_d *dev)
>         struct i2c_adapter *adap = to_i2c_adapter(client->dev.parent);
>         int num, force;
>         struct pca954x *data;
> +       uintptr_t tmp;
>         int ret = -ENODEV;
>         int gpio;
>
> @@ -203,7 +204,8 @@ static int pca954x_probe(struct device_d *dev)
>                 goto exit_free;
>         }
>
> -       ret = dev_get_drvdata(dev, (const void **)&data->type);
> +       ret = dev_get_drvdata(dev, (const void **)&tmp);
> +       data->type = tmp;

Upstream Linux driver doesn't store "type", but the actual pointer to
"chip_desc". I think if you convert the driver to do that instead you
can avoid type width problems and not need helper variable minutiae.

Thanks,
Andrey Smirnov

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Re: [RFC PATCH 00/15] MIPS64 support

[Sascha Hauer]

Hi Peter,

On Thu, May 17, 2018 at 04:58:43PM +0300, Peter Mamonov wrote:
> Hi,
> 
> Recently I've resolved a couple of issues that prevented 64bit Barebox from 
> running on MIPS64 CPUs. By the way, 32bit Barebox runs on MIPS64 without any 
> issues, since MIPS64 supports 32 bit addressing mode. Here is a relevant patch 
> series.  This is mostly for discussion, yet some patches can be applied as is.  
> Please, give your comments.

Please sort the patches that can be applied to the beginning of this
series so that we can get this done early.

Sascha

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