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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 09/14] VFxxx: Initialize IOMUXC_DUMMY_DDRBYTE1/2 in default DDR DCD
Date: Tue, 12 Jun 2018 11:47:55 -0700	[thread overview]
Message-ID: <20180612184800.4940-10-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180612184800.4940-1-andrew.smirnov@gmail.com>

Although upstream U-Boot does not initialize this register in
vf610-twr code (it does so in code for Phytec's PCM052) multiple
revisions of VFxxx Controller Reference Manual state:

    5.2.6.1 DUMMY PADS (DDR/QuadSPI)

    There are two dummy pads that are useful for timing calibration of
    DDR. These pads are internal only, but there corresponding IOMUX
    register need to be programmed for correct operation of DDR. These
    registers are:

              * IOMUXC_DUMMY_DDRBYTE1 (0x400482DC)
              * IOMUXC_DUMMY_DDRBYTE2 (0x400482E0)

    DDR: Dummy pads for DDR must be configured before any DDR I/O
    transactions are done. These pads simulate the input delay of the
    I/O buffers from the DRAM devices and DDR configures the delays
    accordingly.

Although current DCD works as is, add writes for those registers for
the sake of completness.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 .../include/mach/flash-header/vf610-iomux-ddr-default.imxcfg | 3 +++
 arch/arm/mach-imx/include/mach/vf610-iomux-regs.h            | 5 ++++-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
index e2ad818c6..64f97aacd 100644
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
+++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
@@ -58,3 +58,6 @@ wm 32 VF610_PAD_DDR_WE__DDR_WE_B	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_ODT1__DDR_ODT_0	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_ODT0__DDR_ODT_1	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_RESETB		VF610_DDR_PAD_CTRL
+
+wm 32 VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1 VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0 VF610_DDR_PAD_CTRL
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
index 38b3bc7da..c85f0b74b 100644
--- a/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
+++ b/arch/arm/mach-imx/include/mach/vf610-iomux-regs.h
@@ -52,4 +52,7 @@
 #define VF610_PAD_DDR_RAS__DDR_RAS_B	0x400482cc
 #define VF610_PAD_DDR_WE__DDR_WE_B	0x400482d0
 #define VF610_PAD_DDR_ODT1__DDR_ODT_0	0x400482d4
-#define VF610_PAD_DDR_ODT0__DDR_ODT_1	0x400482d8
\ No newline at end of file
+#define VF610_PAD_DDR_ODT0__DDR_ODT_1	0x400482d8
+
+#define VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	0x400482dc
+#define VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0	0x400482e0
-- 
2.17.0


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  parent reply	other threads:[~2018-06-12 18:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 18:47 [PATCH 00/14] VFxxx DCD fixes and improvements Andrey Smirnov
2018-06-12 18:47 ` [PATCH 01/14] VFxxx: Remove stale code from DCD files Andrey Smirnov
2018-06-12 18:47 ` [PATCH 02/14] VFxxx: Add common header for DDR IOMUX DCD configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 03/14] VFxxx: Add common DDR PHY DCD header Andrey Smirnov
2018-06-12 18:47 ` [PATCH 04/14] VFxxx: Add common header for DDR clock setting DCD Andrey Smirnov
2018-06-12 18:47 ` [PATCH 05/14] VFxxx: Add common DCD header for common DDR configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 06/14] VFxxx: Reconcile shared DDR DCD configuration with U-Boot Andrey Smirnov
2018-06-12 18:47 ` [PATCH 07/14] VFxxx: Reconcile shared DDR DCD with memory datasheet Andrey Smirnov
2018-06-12 18:47 ` [PATCH 08/14] VFxxx: zii-vf610-dev: Drop most custom DDRMC DCD code Andrey Smirnov
2018-06-12 18:47 ` Andrey Smirnov [this message]
2018-06-12 18:47 ` [PATCH 10/14] VFxxx: Reconcile shared DDR IOMUX DCD with schematic Andrey Smirnov
2018-06-12 18:47 ` [PATCH 11/14] VFxxx: DCD: Remove CR151 initialization Andrey Smirnov
2018-06-12 18:47 ` [PATCH 12/14] VFxxx: DCD: Drop initialization of CR139 - CR148 Andrey Smirnov
2018-06-12 18:47 ` [PATCH 13/14] VFxxx: DCD: Remove CR97, CR98 and CR99 Andrey Smirnov
2018-06-12 18:48 ` [PATCH 14/14] VFxxx: DCD: Remove read leveling and gate training delays Andrey Smirnov
2018-06-13  7:58 ` [PATCH 00/14] VFxxx DCD fixes and improvements Sascha Hauer

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