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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 10/14] VFxxx: Reconcile shared DDR IOMUX DCD with schematic
Date: Tue, 12 Jun 2018 11:47:56 -0700	[thread overview]
Message-ID: <20180612184800.4940-11-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180612184800.4940-1-andrew.smirnov@gmail.com>

The only differential signals coming out of DDRMC to the memory chip
are CLK, DQS0 and DQS1. There rest of the pins are not, so there
should be no reason to configure them as such.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 .../vf610-iomux-ddr-default.imxcfg            | 38 +++++++++----------
 1 file changed, 19 insertions(+), 19 deletions(-)

diff --git a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
index 64f97aacd..742275b92 100644
--- a/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
+++ b/arch/arm/mach-imx/include/mach/flash-header/vf610-iomux-ddr-default.imxcfg
@@ -31,26 +31,26 @@ wm 32 VF610_PAD_DDR_BA1__DDR_BA_1	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_BA0__DDR_BA_0	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_CAS__DDR_CAS_B	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_CKE__DDR_CKE_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_CLK__DDR_CLK_0	VF610_DDR_PAD_CTRL_1
 wm 32 VF610_PAD_DDR_CS__DDR_CS_B_0	VF610_DDR_PAD_CTRL
-wm 32 VF610_PAD_DDR_D15__DDR_D_15	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D14__DDR_D_14	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D13__DDR_D_13	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D12__DDR_D_12	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D11__DDR_D_11	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D10__DDR_D_10	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D9__DDR_D_9		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D8__DDR_D_8		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D7__DDR_D_7		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D6__DDR_D_6		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D5__DDR_D_5		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D4__DDR_D_4		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D3__DDR_D_3		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D2__DDR_D_2		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D1__DDR_D_1		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_D0__DDR_D_0		VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1	VF610_DDR_PAD_CTRL_1
-wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0	VF610_DDR_PAD_CTRL_1
+wm 32 VF610_PAD_DDR_D15__DDR_D_15	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D14__DDR_D_14	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D13__DDR_D_13	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D12__DDR_D_12	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D11__DDR_D_11	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D10__DDR_D_10	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D9__DDR_D_9		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D8__DDR_D_8		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D7__DDR_D_7		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D6__DDR_D_6		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D5__DDR_D_5		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D4__DDR_D_4		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D3__DDR_D_3		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D2__DDR_D_2		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D1__DDR_D_1		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_D0__DDR_D_0		VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_DQM1__DDR_DQM_1	VF610_DDR_PAD_CTRL
+wm 32 VF610_PAD_DDR_DQM0__DDR_DQM_0	VF610_DDR_PAD_CTRL
 wm 32 VF610_PAD_DDR_DQS1__DDR_DQS_1	VF610_DDR_PAD_CTRL_1
 wm 32 VF610_PAD_DDR_DQS0__DDR_DQS_0	VF610_DDR_PAD_CTRL_1
 wm 32 VF610_PAD_DDR_RAS__DDR_RAS_B	VF610_DDR_PAD_CTRL
-- 
2.17.0


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  parent reply	other threads:[~2018-06-12 18:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 18:47 [PATCH 00/14] VFxxx DCD fixes and improvements Andrey Smirnov
2018-06-12 18:47 ` [PATCH 01/14] VFxxx: Remove stale code from DCD files Andrey Smirnov
2018-06-12 18:47 ` [PATCH 02/14] VFxxx: Add common header for DDR IOMUX DCD configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 03/14] VFxxx: Add common DDR PHY DCD header Andrey Smirnov
2018-06-12 18:47 ` [PATCH 04/14] VFxxx: Add common header for DDR clock setting DCD Andrey Smirnov
2018-06-12 18:47 ` [PATCH 05/14] VFxxx: Add common DCD header for common DDR configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 06/14] VFxxx: Reconcile shared DDR DCD configuration with U-Boot Andrey Smirnov
2018-06-12 18:47 ` [PATCH 07/14] VFxxx: Reconcile shared DDR DCD with memory datasheet Andrey Smirnov
2018-06-12 18:47 ` [PATCH 08/14] VFxxx: zii-vf610-dev: Drop most custom DDRMC DCD code Andrey Smirnov
2018-06-12 18:47 ` [PATCH 09/14] VFxxx: Initialize IOMUXC_DUMMY_DDRBYTE1/2 in default DDR DCD Andrey Smirnov
2018-06-12 18:47 ` Andrey Smirnov [this message]
2018-06-12 18:47 ` [PATCH 11/14] VFxxx: DCD: Remove CR151 initialization Andrey Smirnov
2018-06-12 18:47 ` [PATCH 12/14] VFxxx: DCD: Drop initialization of CR139 - CR148 Andrey Smirnov
2018-06-12 18:47 ` [PATCH 13/14] VFxxx: DCD: Remove CR97, CR98 and CR99 Andrey Smirnov
2018-06-12 18:48 ` [PATCH 14/14] VFxxx: DCD: Remove read leveling and gate training delays Andrey Smirnov
2018-06-13  7:58 ` [PATCH 00/14] VFxxx DCD fixes and improvements Sascha Hauer

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