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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH 01/14] VFxxx: Remove stale code from DCD files
Date: Tue, 12 Jun 2018 11:47:47 -0700	[thread overview]
Message-ID: <20180612184800.4940-2-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180612184800.4940-1-andrew.smirnov@gmail.com>

Remove various bits of debug code, commented DCD commands and
separators as a small clean-up in preparation for commits that would
follow.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 .../flash-header-vf610-twr.imxcfg             | 34 -----------------
 .../flash-header-zii-vf610-dev.imxcfg         | 37 -------------------
 2 files changed, 71 deletions(-)

diff --git a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
index 8dd62be21..ae7447b4f 100644
--- a/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
+++ b/arch/arm/boards/freescale-vf610-twr/flash-header-vf610-twr.imxcfg
@@ -13,16 +13,6 @@ dcdofs 0x400
 #define DDRMC_PHY_OFF		0x00000000
 #define DDRMC_PHY_PROC_PAD_ODT	0x00010101
 
-#ifdef DEBUG
-#define CHECKPOINT(n) wm 32 0x3f040000 n
-#else
-#define CHECKPOINT(n)
-#endif
-
-CHECKPOINT(1)
-
-/* ======================= Clock initialization =======================*/
-
 /*
  * Ungate all IP block clocks
  */
@@ -60,28 +50,17 @@ wm 32 0x4006b06c 0xffffffff
  */
 wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */
 
-CHECKPOINT(2)
-
 /*
  * Wait for PLLs to lock
  */
 check 32 until_any_bit_set 0x40050030 0x80000000
 
-
-CHECKPOINT(3)
-
 /*
  * Switch DDRMC to be clocked with PLL2 PFD2 and enable PFD2 output
  */
 clear_bits 32 0x4006b008 0x00000040
 set_bits   32 0x4006b008 0x00002000
 
-
-
-/* ======================= DDR IOMUX ======================= */
-
-CHECKPOINT(4)
-
 wm 32 0x40048220 VF610_DDR_PAD_CTRL
 wm 32 0x40048224 VF610_DDR_PAD_CTRL
 wm 32 0x40048228 VF610_DDR_PAD_CTRL
@@ -131,10 +110,6 @@ wm 32 0x400482d4 VF610_DDR_PAD_CTRL
 wm 32 0x400482d8 VF610_DDR_PAD_CTRL
 wm 32 0x4004821c VF610_DDR_PAD_CTRL
 
-/* ======================= DDR Controller =======================*/
-
-CHECKPOINT(5)
-
 wm 32 0x400ae000 0x00000600
 wm 32 0x400ae008 0x00000020
 wm 32 0x400ae028 0x00013880
@@ -214,10 +189,6 @@ wm 32 0x400ae26c 0x00000012
 wm 32 0x400ae278 0x00000006
 wm 32 0x400ae284 0x00010202
 
-/* ======================= DDR PHY =======================*/
-
-CHECKPOINT(6)
-
 wm 32 0x400ae400 DDRMC_PHY_DQ_TIMING
 wm 32 0x400ae440 DDRMC_PHY_DQ_TIMING
 wm 32 0x400ae480 DDRMC_PHY_DQ_TIMING
@@ -238,12 +209,8 @@ wm 32 0x400ae4d0 DDRMC_PHY_PROC_PAD_ODT
 
 wm 32 0x400ae000 0x00000601
 
-CHECKPOINT(7)
-
 check 32 until_any_bit_set 0x400ae140 0x100
 
-CHECKPOINT(8)
-
 /*
  * Cargo cult DDR controller initialization here we come!
  *
@@ -275,4 +242,3 @@ wm 32 0x400ae000 0x00000601
 
 check 32 until_any_bit_set 0x400ae140 0x100
 
-CHECKPOINT(9)
diff --git a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
index bb858907a..a641ff82e 100644
--- a/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
+++ b/arch/arm/boards/zii-vf610-dev/flash-header-zii-vf610-dev.imxcfg
@@ -13,12 +13,6 @@ dcdofs 0x400
 #define DDRMC_PHY_OFF		0x00000000
 #define DDRMC_PHY_PROC_PAD_ODT	0x00010101
 
-#define CHECKPOINT(n) wm 32 0x3f000000 n
-
-CHECKPOINT(1)
-
-/* ======================= Clock initialization =======================*/
-
 /*
  * Ungate all IP block clocks
  */
@@ -40,25 +34,14 @@ wm 32 0x4006b06c 0xffffffff
  */
 wm 32 0x40050030 0x00002001 /* Fout = Fin * 22 */
 
-CHECKPOINT(2)
-
 /*
  * Wait for PLLs to lock
  */
 check 32 until_any_bit_set 0x40050030 0x80000000
 
-
-CHECKPOINT(3)
-
 clear_bits 32 0x4006b008 0x00000040
 set_bits   32 0x4006b008 0x00002000
 
-
-
-/* ======================= DDR IOMUX =======================*/
-
-CHECKPOINT(4)
-
 wm 32 0x40048220 0x00000180
 wm 32 0x40048224 0x00000180
 wm 32 0x40048228 0x00000180
@@ -108,9 +91,6 @@ wm 32 0x400482d4 0x00000180
 wm 32 0x400482d8 0x00000180
 wm 32 0x4004821c 0x00000180
 
-/* ======================= DDR Controller =======================*/
-
-CHECKPOINT(5)
 wm 32 0x400ae000 0x00000600
 wm 32 0x400ae008 0x00000005
 wm 32 0x400ae028 0x00013880
@@ -193,10 +173,6 @@ wm 32 0x400ae26c 0x00000012
 wm 32 0x400ae278 0x00000006
 wm 32 0x400ae284 0x00010202
 
-/* ======================= DDR PHY =======================*/
-
-CHECKPOINT(6)
-
 wm 32 0x400ae400 0x00002613
 wm 32 0x400ae440 0x00002613
 wm 32 0x400ae480 0x00002613
@@ -216,14 +192,7 @@ wm 32 0x400ae4c8 0x00001100
 wm 32 0x400ae4d0 0x00010101
 wm 32 0x400ae000 0x00000601
 
-CHECKPOINT(7)
-
 check 32 until_any_bit_set 0x400ae140 0x100
-# check 32 until_any_bit_set 0x400ae42c 0x1
-# check 32 until_any_bit_set 0x400ae46c 0x1
-# check 32 until_any_bit_set 0x400ae4ac 0x1
-
-CHECKPOINT(8)
 
 wm 32 0x80000000 0xa5a5a5a5
 check 32 until_any_bit_set 0x80000000 0xa5a5a5a5
@@ -232,12 +201,6 @@ wm 32 0x400ae000 0x00000600
 wm 32 0x400ae000 0x00000601
 
 check 32 until_any_bit_set 0x400ae140 0x100
-# check 32 until_any_bit_set 0x400ae42c 0x1
-# check 32 until_any_bit_set 0x400ae46c 0x1
-# check 32 until_any_bit_set 0x400ae4ac 0x1
 
-/* wm 32 0x3f040000 0xf0
- check 32 until_any_bit_set 0x3f040000 0x0f */
 
 
-CHECKPOINT(9)
-- 
2.17.0


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  reply	other threads:[~2018-06-12 18:48 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-12 18:47 [PATCH 00/14] VFxxx DCD fixes and improvements Andrey Smirnov
2018-06-12 18:47 ` Andrey Smirnov [this message]
2018-06-12 18:47 ` [PATCH 02/14] VFxxx: Add common header for DDR IOMUX DCD configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 03/14] VFxxx: Add common DDR PHY DCD header Andrey Smirnov
2018-06-12 18:47 ` [PATCH 04/14] VFxxx: Add common header for DDR clock setting DCD Andrey Smirnov
2018-06-12 18:47 ` [PATCH 05/14] VFxxx: Add common DCD header for common DDR configuration Andrey Smirnov
2018-06-12 18:47 ` [PATCH 06/14] VFxxx: Reconcile shared DDR DCD configuration with U-Boot Andrey Smirnov
2018-06-12 18:47 ` [PATCH 07/14] VFxxx: Reconcile shared DDR DCD with memory datasheet Andrey Smirnov
2018-06-12 18:47 ` [PATCH 08/14] VFxxx: zii-vf610-dev: Drop most custom DDRMC DCD code Andrey Smirnov
2018-06-12 18:47 ` [PATCH 09/14] VFxxx: Initialize IOMUXC_DUMMY_DDRBYTE1/2 in default DDR DCD Andrey Smirnov
2018-06-12 18:47 ` [PATCH 10/14] VFxxx: Reconcile shared DDR IOMUX DCD with schematic Andrey Smirnov
2018-06-12 18:47 ` [PATCH 11/14] VFxxx: DCD: Remove CR151 initialization Andrey Smirnov
2018-06-12 18:47 ` [PATCH 12/14] VFxxx: DCD: Drop initialization of CR139 - CR148 Andrey Smirnov
2018-06-12 18:47 ` [PATCH 13/14] VFxxx: DCD: Remove CR97, CR98 and CR99 Andrey Smirnov
2018-06-12 18:48 ` [PATCH 14/14] VFxxx: DCD: Remove read leveling and gate training delays Andrey Smirnov
2018-06-13  7:58 ` [PATCH 00/14] VFxxx DCD fixes and improvements Sascha Hauer

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