From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v2 11/12] ARM: nxp-imx8mq-evk: Add bootflow comments
Date: Thu, 19 Jul 2018 18:03:56 -0700 [thread overview]
Message-ID: <20180720010357.22822-12-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180720010357.22822-1-andrew.smirnov@gmail.com>
Add some notes on how the boot-flow goes while I still remember it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 41 +++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index db746bb94..fdc964ac9 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -66,6 +66,26 @@ static void nxp_imx8mq_evk_sram_setup(void)
BUG_ON(ret);
}
+/*
+ * Power-on execution flow of start_nxp_imx8mq_evk() might not be
+ * obvious for a very frist read, so here's, hopefully helpful,
+ * summary:
+ *
+ * 1. MaskROM uploads PBL into OCRAM and that's where this function is
+ * executed for the first time
+ *
+ * 2. DDR is initialized and full i.MX image is loaded to the
+ * beginning of RAM
+ *
+ * 3. start_nxp_imx8mq_evk, now in RAM, is executed again
+ *
+ * 4. BL31 blob is uploaded to OCRAM and the control is transfer to it
+ *
+ * 5. BL31 exits EL3 into EL2 at address MX8MQ_ATF_BL33_BASE_ADDR,
+ * executing start_nxp_imx8mq_evk() the third time
+ *
+ * 6. Standard barebox boot flow continues
+ */
ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
{
arm_cpu_lowlevel_init();
@@ -73,9 +93,23 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
if (IS_ENABLED(CONFIG_DEBUG_LL))
setup_uart();
- if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR)
+ if (get_pc() < MX8MQ_DDR_CSD1_BASE_ADDR) {
+ /*
+ * We assume that we were just loaded by MaskROM into
+ * SRAM if we are not running from DDR. We also assume
+ * that means DDR needs to be initialized for the
+ * first time.
+ */
nxp_imx8mq_evk_sram_setup();
-
+ }
+ /*
+ * Straight from the power-on we are at EL3, so the following
+ * code _will_ load and jump to ATF.
+ *
+ * However when we are re-executed upon exit from ATF's
+ * initialization routine, it is EL2 which means we'll skip
+ * loadting ATF blob again
+ */
if (current_el() == 3) {
const u8 *bl31;
size_t bl31_size;
@@ -84,6 +118,9 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
imx8mq_atf_load_bl31(bl31, bl31_size);
}
+ /*
+ * Standard entry we hit once we initialized both DDR and ATF
+ */
barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR,
SZ_2G + SZ_1G, __dtb_imx8mq_evk_start);
}
--
2.17.1
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
next prev parent reply other threads:[~2018-07-20 1:04 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 1:03 [PATCH v2 00/12] ARM: i.MX8MQ and EVK support, part II Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 01/12] ARM: nxp-imx8mq-evk: Update DDR initialization code Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 02/12] ARM: Add code to support SMCCC on AArch64 Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 03/12] ARM: i.MX8MQ: Configure cntfrq only in EL3 Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 04/12] ARM: i.MX8MQ: Add code to load BL31 ATF blob Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 05/12] ARM: i.MX: fimware: Add pre-built " Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 06/12] ARM: i.MX: Move i.MX header definitions to mach-imx Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 07/12] ARM: i.MX: xload-esdhc: Make use of <mach/imx-header.h> Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 08/12] ARM: i.MX: xload-esdhc: Allow placing image to align its etnry point Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 09/12] ARM: nxp-imx8mq-evk: Add code to load ATF BL31 blob Andrey Smirnov
2018-07-20 1:03 ` [PATCH v2 10/12] ARM: i.MX8MQ: Query and display ATF fimware hash if availible Andrey Smirnov
2018-07-20 1:03 ` Andrey Smirnov [this message]
2018-07-20 1:03 ` [PATCH v2 12/12] firmware: Fix copy-paste comment mistake Andrey Smirnov
2018-08-08 6:34 ` [PATCH v2 00/12] ARM: i.MX8MQ and EVK support, part II Sascha Hauer
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180720010357.22822-12-andrew.smirnov@gmail.com \
--to=andrew.smirnov@gmail.com \
--cc=barebox@lists.infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox