From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1fgJqP-0002p6-16 for barebox@lists.infradead.org; Fri, 20 Jul 2018 01:04:31 +0000 Received: by mail-pg1-x52a.google.com with SMTP id z8-v6so5272927pgu.8 for ; Thu, 19 Jul 2018 18:04:18 -0700 (PDT) From: Andrey Smirnov Date: Thu, 19 Jul 2018 18:03:46 -0700 Message-Id: <20180720010357.22822-2-andrew.smirnov@gmail.com> In-Reply-To: <20180720010357.22822-1-andrew.smirnov@gmail.com> References: <20180720010357.22822-1-andrew.smirnov@gmail.com> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH v2 01/12] ARM: nxp-imx8mq-evk: Update DDR initialization code To: barebox@lists.infradead.org Cc: Andrey Smirnov Previous version of DDR initialization code was generated by a beta version of MX8_DDR_tool. This updates the code to the output of MX8_DDR_tool v1.0, which seem to fix the vendor Linux kernel hang* that was happening with the previous version. * The kernel would hang as soon as it tried to utilize DDR's DVFS features and switch DDR frequency (disabling busfreq-imx8mq.c would fix the problem). Signed-off-by: Andrey Smirnov --- arch/arm/boards/nxp-imx8mq-evk/ddr_init.c | 120 +++++----- arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c | 219 +++++------------- 2 files changed, 125 insertions(+), 214 deletions(-) diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c index 81691b2fa..44103b5e2 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddr_init.c @@ -2,7 +2,8 @@ * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ - * Generated code from MX8_DDR_tool + * + * Generated code from MX8M_DDR_tool */ #include "ddr.h" @@ -21,7 +22,7 @@ void ddr_init(void) reg32_write(0x303a00f8,tmp); reg32_write(0x30391000,0x8f000000); reg32_write(0x30391004,0x8f000000); - reg32_write(0x30360068,0xbbe580); + reg32_write(0x30360068,0xece580); tmp=reg32_read(0x30360060); tmp &= ~0x80; reg32_write(0x30360060,tmp); @@ -41,18 +42,19 @@ void ddr_init(void) reg32_write(0x30391000,0x8f000006); reg32_write(0x3d400304,0x1); reg32_write(0x3d400030,0x1); - reg32_write(0x3d400000,0x83080020); + reg32_write(0x3d400000,0xa3080020); + reg32_write(0x3d400028,0x0); + reg32_write(0x3d400020,0x203); + reg32_write(0x3d400024,0x186a000); reg32_write(0x3d400064,0x6100e0); reg32_write(0x3d4000d0,0xc003061c); reg32_write(0x3d4000d4,0x9e0000); reg32_write(0x3d4000dc,0xd4002d); reg32_write(0x3d4000e0,0x310008); - reg32_write(0x3d4000e8,0x46004d); - reg32_write(0x3d4000ec,0x15004d); - reg32_write(0x3d4000f4,0x639); + reg32_write(0x3d4000e8,0x66004a); + reg32_write(0x3d4000ec,0x16004a); reg32_write(0x3d400100,0x1a201b22); reg32_write(0x3d400104,0x60633); - reg32_write(0x3d400108,0x70e1214); reg32_write(0x3d40010c,0xc0c000); reg32_write(0x3d400110,0xf04080f); reg32_write(0x3d400114,0x2040c0c); @@ -64,78 +66,77 @@ void ddr_init(void) reg32_write(0x3d400144,0xa00050); reg32_write(0x3d400180,0x3200018); reg32_write(0x3d400184,0x28061a8); + reg32_write(0x3d400188,0x0); reg32_write(0x3d400190,0x497820a); reg32_write(0x3d400194,0x80303); - reg32_write(0x3d4001b4,0x170a); - reg32_write(0x3d4001b0,0x11); reg32_write(0x3d4001a0,0xe0400018); reg32_write(0x3d4001a4,0xdf00e4); - reg32_write(0x3d4001a8,0x0); + reg32_write(0x3d4001a8,0x80000000); + reg32_write(0x3d4001b0,0x11); + reg32_write(0x3d4001b4,0x170a); reg32_write(0x3d4001c0,0x1); reg32_write(0x3d4001c4,0x1); + reg32_write(0x3d4000f4,0x639); + reg32_write(0x3d400108,0x70e1214); reg32_write(0x3d400200,0x15); reg32_write(0x3d40020c,0x0); reg32_write(0x3d400210,0x1f1f); reg32_write(0x3d400204,0x80808); reg32_write(0x3d400214,0x7070707); reg32_write(0x3d400218,0x48080707); + reg32_write(0x3d402020,0x1); + reg32_write(0x3d402024,0x518b00); + reg32_write(0x3d402050,0x20d040); + reg32_write(0x3d402064,0x14002f); + reg32_write(0x3d4020dc,0x940009); + reg32_write(0x3d4020e0,0x310000); + reg32_write(0x3d4020e8,0x66004a); + reg32_write(0x3d4020ec,0x16004a); + reg32_write(0x3d402100,0xb070508); + reg32_write(0x3d402104,0x3040b); + reg32_write(0x3d402108,0x305090c); + reg32_write(0x3d40210c,0x505000); + reg32_write(0x3d402110,0x4040204); + reg32_write(0x3d402114,0x2030303); + reg32_write(0x3d402118,0x1010004); + reg32_write(0x3d40211c,0x301); + reg32_write(0x3d402130,0x20300); + reg32_write(0x3d402134,0xa100002); + reg32_write(0x3d402138,0x31); + reg32_write(0x3d402144,0x220011); + reg32_write(0x3d402180,0xa70006); + reg32_write(0x3d402190,0x3858202); + reg32_write(0x3d402194,0x80303); + reg32_write(0x3d4021b4,0x502); reg32_write(0x3d400244,0x0); - reg32_write(0x3d400490,0x1); - reg32_write(0x3d400250,0x29001f01); + reg32_write(0x3d400250,0x29001505); reg32_write(0x3d400254,0x2c); - reg32_write(0x3d400264,0x900093e7); + reg32_write(0x3d40025c,0x5900575b); + reg32_write(0x3d400264,0x9); reg32_write(0x3d40026c,0x2005574); - reg32_write(0x3d400400,0x400); + reg32_write(0x3d400300,0x16); + reg32_write(0x3d400304,0x0); + reg32_write(0x3d40030c,0x0); + reg32_write(0x3d400320,0x1); + reg32_write(0x3d40036c,0x11); + reg32_write(0x3d400400,0x111); + reg32_write(0x3d400404,0x10f3); reg32_write(0x3d400408,0x72ff); - reg32_write(0x3d400494,0x10e00); - reg32_write(0x3d400498,0x620096); - reg32_write(0x3d40049c,0x10e00); - reg32_write(0x3d4004a0,0x12c); + reg32_write(0x3d400490,0x1); + reg32_write(0x3d400494,0x1110d00); + reg32_write(0x3d400498,0x620790); + reg32_write(0x3d40049c,0x100001); + reg32_write(0x3d4004a0,0x41f); reg32_write(0x30391000,0x8f000004); reg32_write(0x30391000,0x8f000000); - reg32_write(0x3d400304,0x0); reg32_write(0x3d400030,0xa8); + do{ + tmp=reg32_read(0x3d400004); + if(tmp&0x223) break; + }while(1); reg32_write(0x3d400320,0x0); reg32_write(0x3d000000,0x1); reg32_write(0x3d4001b0,0x10); - reg32_write(0x3d402100,0xa040305); - reg32_write(0x3d402104,0x30407); - reg32_write(0x3d402108,0x203060b); - reg32_write(0x3d40210c,0x505000); - reg32_write(0x3d402110,0x2040202); - reg32_write(0x3d402114,0x2030202); - reg32_write(0x3d402118,0x1010004); - reg32_write(0x3d40211c,0x301); - reg32_write(0x3d402138,0x1d); - reg32_write(0x3d402144,0x14000a); - reg32_write(0x3d403024,0x30d400); - reg32_write(0x3d402050,0x20d040); - reg32_write(0x3d402190,0x3818200); - reg32_write(0x3d4021b4,0x100); - reg32_write(0x3d402064,0xc001c); - reg32_write(0x3d4020dc,0x840000); - reg32_write(0x3d4020e8,0x46004d); - reg32_write(0x3d4020ec,0x15004d); - reg32_write(0x3d4020e0,0x310000); - reg32_write(0x3d403100,0x6010102); - reg32_write(0x3d403104,0x30404); - reg32_write(0x3d403108,0x203060b); - reg32_write(0x3d40310c,0x505000); - reg32_write(0x3d403110,0x2040202); - reg32_write(0x3d403114,0x2030202); - reg32_write(0x3d403118,0x1010004); - reg32_write(0x3d40311c,0x301); - reg32_write(0x3d403138,0x8); - reg32_write(0x3d403144,0x50003); - reg32_write(0x3d403024,0xc3500); - reg32_write(0x3d403050,0x20d040); - reg32_write(0x3d403190,0x3818200); - reg32_write(0x3d4031b4,0x100); - reg32_write(0x3d403064,0x30007); - reg32_write(0x3d4030dc,0x840000); - reg32_write(0x3d4030e8,0x46004d); - reg32_write(0x3d4030ec,0x15004d); - reg32_write(0x3d4030e0,0x310000); reg32_write(0x3c040280,0x0); reg32_write(0x3c040284,0x1); reg32_write(0x3c040288,0x2); @@ -218,6 +219,7 @@ void ddr_init(void) /* enable port 0 */ reg32_write(DDRC_PCTRL_0(0), 0x00000001); - tmp = reg32_read(DDRC_CRCPARSTAT(0)); - reg32_write(DDRC_RFSHCTL3(0), 0x00000000); + /* enable DDR auto-refresh mode */ + tmp = reg32_read(DDRC_RFSHCTL3(0)) & ~0x1; + reg32_write(DDRC_RFSHCTL3(0), tmp); } \ No newline at end of file diff --git a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c index 156d7cf87..1b30ff725 100644 --- a/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c +++ b/arch/arm/boards/nxp-imx8mq-evk/ddrphy_train.c @@ -2,6 +2,8 @@ * Copyright 2017 NXP * * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool */ #include "ddr.h" @@ -32,14 +34,6 @@ void ddr_cfg_phy(void) { reg32_write(0x3c44857c,0x1ff); reg32_write(0x3c44c17c,0x1ff); reg32_write(0x3c44c57c,0x1ff); - reg32_write(0x3c84017c,0x1ff); - reg32_write(0x3c84057c,0x1ff); - reg32_write(0x3c84417c,0x1ff); - reg32_write(0x3c84457c,0x1ff); - reg32_write(0x3c84817c,0x1ff); - reg32_write(0x3c84857c,0x1ff); - reg32_write(0x3c84c17c,0x1ff); - reg32_write(0x3c84c57c,0x1ff); reg32_write(0x3c000154,0x1ff); reg32_write(0x3c004154,0x1ff); reg32_write(0x3c008154,0x1ff); @@ -52,22 +46,16 @@ void ddr_cfg_phy(void) { reg32_write(0x3c024154,0x1ff); reg32_write(0x3c080314,0x19); reg32_write(0x3c480314,0x7); - reg32_write(0x3c880314,0x7); reg32_write(0x3c0800b8,0x2); - reg32_write(0x3c4800b8,0x2); - reg32_write(0x3c8800b8,0x2); + reg32_write(0x3c4800b8,0x1); reg32_write(0x3c240810,0x0); reg32_write(0x3c640810,0x0); - reg32_write(0x3ca40810,0x0); reg32_write(0x3c080090,0xab); reg32_write(0x3c0800e8,0x0); reg32_write(0x3c480090,0xab); reg32_write(0x3c0800e8,0x0); - reg32_write(0x3c880090,0xab); - reg32_write(0x3c0800e8,0x0); - reg32_write(0x3c080158,0x7); + reg32_write(0x3c080158,0x3); reg32_write(0x3c480158,0xa); - reg32_write(0x3c880158,0xa); reg32_write(0x3c040134,0xe00); reg32_write(0x3c040534,0xe00); reg32_write(0x3c044134,0xe00); @@ -84,14 +72,6 @@ void ddr_cfg_phy(void) { reg32_write(0x3c448534,0xe00); reg32_write(0x3c44c134,0xe00); reg32_write(0x3c44c534,0xe00); - reg32_write(0x3c840134,0xe00); - reg32_write(0x3c840534,0xe00); - reg32_write(0x3c844134,0xe00); - reg32_write(0x3c844534,0xe00); - reg32_write(0x3c848134,0xe00); - reg32_write(0x3c848534,0xe00); - reg32_write(0x3c84c134,0xe00); - reg32_write(0x3c84c534,0xe00); reg32_write(0x3c040124,0xfbe); reg32_write(0x3c040524,0xfbe); reg32_write(0x3c044124,0xfbe); @@ -108,14 +88,6 @@ void ddr_cfg_phy(void) { reg32_write(0x3c448524,0xfbe); reg32_write(0x3c44c124,0xfbe); reg32_write(0x3c44c524,0xfbe); - reg32_write(0x3c840124,0xfbe); - reg32_write(0x3c840524,0xfbe); - reg32_write(0x3c844124,0xfbe); - reg32_write(0x3c844524,0xfbe); - reg32_write(0x3c848124,0xfbe); - reg32_write(0x3c848524,0xfbe); - reg32_write(0x3c84c124,0xfbe); - reg32_write(0x3c84c524,0xfbe); reg32_write(0x3c00010c,0x63); reg32_write(0x3c00410c,0x63); reg32_write(0x3c00810c,0x63); @@ -130,8 +102,7 @@ void ddr_cfg_phy(void) { reg32_write(0x3c0801d4,0x4); reg32_write(0x3c080140,0x0); reg32_write(0x3c080020,0x320); - reg32_write(0x3c480020,0x64); - reg32_write(0x3c880020,0x19); + reg32_write(0x3c480020,0xa7); reg32_write(0x3c080220,0x9); reg32_write(0x3c0802c8,0xdc); reg32_write(0x3c04010c,0x5a1); @@ -151,33 +122,21 @@ void ddr_cfg_phy(void) { reg32_write(0x3c44850c,0x5a1); reg32_write(0x3c44c10c,0x5a1); reg32_write(0x3c44c50c,0x5a1); - reg32_write(0x3c8802c8,0xdc); - reg32_write(0x3c84010c,0x5a1); - reg32_write(0x3c84050c,0x5a1); - reg32_write(0x3c84410c,0x5a1); - reg32_write(0x3c84450c,0x5a1); - reg32_write(0x3c84810c,0x5a1); - reg32_write(0x3c84850c,0x5a1); - reg32_write(0x3c84c10c,0x5a1); - reg32_write(0x3c84c50c,0x5a1); reg32_write(0x3c0803e8,0x1); reg32_write(0x3c4803e8,0x1); - reg32_write(0x3c8803e8,0x1); reg32_write(0x3c080064,0x1); reg32_write(0x3c480064,0x1); - reg32_write(0x3c880064,0x1); - reg32_write(0x3c0803c0,0x660); + reg32_write(0x3c0803c0,0x0); reg32_write(0x3c0803c4,0x0); reg32_write(0x3c0803c8,0x4444); reg32_write(0x3c0803cc,0x8888); - reg32_write(0x3c0803d0,0x5665); + reg32_write(0x3c0803d0,0x5555); reg32_write(0x3c0803d4,0x0); reg32_write(0x3c0803d8,0x0); reg32_write(0x3c0803dc,0xf000); reg32_write(0x3c080094,0x0); reg32_write(0x3c0800b4,0x0); reg32_write(0x3c4800b4,0x0); - reg32_write(0x3c8800b4,0x0); reg32_write(0x3c080180,0x2); //enable APB bus to access DDRPHY RAM @@ -195,31 +154,32 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54008,0x131f); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54009,0xc8); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400b,0x2); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5400d,0x100); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x15); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x15); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1500); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1500); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); //disable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); @@ -233,96 +193,57 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); //set the PHY input clock to the desired frequency for pstate 1 - reg32_write(0x3038a008,0x7070000); - reg32_write(0x3038a004,0x5000000); - reg32_write(0x3038a088,0x7070000); - reg32_write(0x3038a084,0x2010000); - reg32_write(0x303a00ec,0xffff); - tmp=reg32_read(0x303a00f8); - tmp |= 0x20; - reg32_write(0x303a00f8,tmp); - reg32_write(0x30389804,0x1000000); - - //enable APB bus to access DDRPHY RAM - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - - reg32_write(0x3c150008,0x101); - reg32_write(0x3c15000c,0x190); - reg32_write(0x3c150020,0x121f); - reg32_write(0x3c150064,0x84); - reg32_write(0x3c150068,0x31); - reg32_write(0x3c15006c,0x4d46); - reg32_write(0x3c150070,0x4d08); - reg32_write(0x3c150074,0x0); - reg32_write(0x3c150078,0x15); - reg32_write(0x3c15007c,0x84); - reg32_write(0x3c150080,0x31); - reg32_write(0x3c150084,0x4d46); - reg32_write(0x3c150088,0x4d08); - reg32_write(0x3c15008c,0x0); - reg32_write(0x3c150090,0x15); - reg32_write(0x3c1500c8,0x8400); - reg32_write(0x3c1500cc,0x3100); - reg32_write(0x3c1500d0,0x4600); - reg32_write(0x3c1500d4,0x84d); - reg32_write(0x3c1500d8,0x4d); - reg32_write(0x3c1500dc,0x1500); - reg32_write(0x3c1500e0,0x8400); - reg32_write(0x3c1500e4,0x3100); - reg32_write(0x3c1500e8,0x4600); - reg32_write(0x3c1500ec,0x84d); - reg32_write(0x3c1500f0,0x4d); - reg32_write(0x3c1500f4,0x1500); - reg32_write(0x3c1500f8,0x0); - - //disable APB bus to access DDRPHY RAM - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); - //Reset MPU and run - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x9); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x0); - wait_ddrphy_training_complete(); - - //configure DDRPHY-FW DMEM structure @clock2... - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0099, 0x1); - - //set the PHY input clock to the desired frequency for pstate 2 - reg32_write(0x3038a008,0x7070000); - reg32_write(0x3038a004,0x2000000); reg32_write(0x3038a088,0x7070000); - reg32_write(0x3038a084,0x2010000); + reg32_write(0x3038a084,0x4030000); reg32_write(0x303a00ec,0xffff); tmp=reg32_read(0x303a00f8); tmp |= 0x20; reg32_write(0x303a00f8,tmp); - reg32_write(0x30389804,0x1000000); + reg32_write(0x30360068,0xf5a406); + tmp=reg32_read(0x30360060); + tmp &= ~0x80; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp |= 0x200; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x20; + reg32_write(0x30360060,tmp); + tmp=reg32_read(0x30360060); + tmp &= ~0x10; + reg32_write(0x30360060,tmp); + do{ + tmp=reg32_read(0x30360060); + if(tmp&0x80000000) break; + }while(1); + reg32_write(0x30389808,0x1000000); //enable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x0); - reg32_write(0x3c150008,0x102); - reg32_write(0x3c15000c,0x64); + reg32_write(0x3c150008,0x1); + reg32_write(0x3c15000c,0x29c); reg32_write(0x3c150020,0x121f); - reg32_write(0x3c150064,0x84); + reg32_write(0x3c150064,0x994); reg32_write(0x3c150068,0x31); reg32_write(0x3c15006c,0x4d46); reg32_write(0x3c150070,0x4d08); reg32_write(0x3c150074,0x0); reg32_write(0x3c150078,0x15); - reg32_write(0x3c15007c,0x84); + reg32_write(0x3c15007c,0x994); reg32_write(0x3c150080,0x31); reg32_write(0x3c150084,0x4d46); reg32_write(0x3c150088,0x4d08); reg32_write(0x3c15008c,0x0); reg32_write(0x3c150090,0x15); - reg32_write(0x3c1500c8,0x8400); - reg32_write(0x3c1500cc,0x3100); + reg32_write(0x3c1500c8,0x9400); + reg32_write(0x3c1500cc,0x3109); reg32_write(0x3c1500d0,0x4600); reg32_write(0x3c1500d4,0x84d); reg32_write(0x3c1500d8,0x4d); reg32_write(0x3c1500dc,0x1500); - reg32_write(0x3c1500e0,0x8400); - reg32_write(0x3c1500e4,0x3100); + reg32_write(0x3c1500e0,0x9400); + reg32_write(0x3c1500e4,0x3109); reg32_write(0x3c1500e8,0x4600); reg32_write(0x3c1500ec,0x84d); reg32_write(0x3c1500f0,0x4d); @@ -344,7 +265,7 @@ void ddr_cfg_phy(void) { tmp=reg32_read(0x303a00f8); tmp |= 0x20; reg32_write(0x303a00f8,tmp); - reg32_write(0x30360068,0xbbe580); + reg32_write(0x30360068,0xece580); tmp=reg32_read(0x30360060); tmp &= ~0x80; reg32_write(0x30360060,tmp); @@ -380,28 +301,28 @@ void ddr_cfg_phy(void) { reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54012,0x310); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54019,0x2dd4); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401a,0x31); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4d46); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4d08); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x15); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401b,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401c,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401e,0x16); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5401f,0x2dd4); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54020,0x31); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4d46); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4d08); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x15); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54021,0x4a66); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54022,0x4a08); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54024,0x16); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402b,0x1000); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5402c,0x3); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54032,0xd400); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54033,0x312d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x4600); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1500); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54034,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54035,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54036,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54037,0x1600); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54038,0xd400); reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x54039,0x312d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x4600); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4d); - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1500); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403a,0x6600); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403b,0x84a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403c,0x4a); + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0x5403d,0x1600); //disable APB bus to access DDRPHY RAM reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * 0xd0000, 0x1); @@ -912,10 +833,6 @@ void ddr_cfg_phy(void) { reg32_write(0x3c480030,0xc9); reg32_write(0x3c480034,0x7d1); reg32_write(0x3c480038,0x2c); - reg32_write(0x3c88002c,0x65); - reg32_write(0x3c880030,0xc9); - reg32_write(0x3c880034,0x7d1); - reg32_write(0x3c880038,0x2c); reg32_write(0x3c240030,0x0); reg32_write(0x3c240034,0x173); reg32_write(0x3c240038,0x60); @@ -928,8 +845,6 @@ void ddr_cfg_phy(void) { reg32_write(0x3c080044,0x3); reg32_write(0x3c480040,0x5a); reg32_write(0x3c480044,0x3); - reg32_write(0x3c880040,0x5a); - reg32_write(0x3c880044,0x3); reg32_write(0x3c100200,0xe0); reg32_write(0x3c100204,0x12); reg32_write(0x3c100208,0xe0); @@ -942,12 +857,6 @@ void ddr_cfg_phy(void) { reg32_write(0x3c50020c,0x12); reg32_write(0x3c500210,0xe0); reg32_write(0x3c500214,0x12); - reg32_write(0x3c900200,0xe0); - reg32_write(0x3c900204,0x12); - reg32_write(0x3c900208,0xe0); - reg32_write(0x3c90020c,0x12); - reg32_write(0x3c900210,0xe0); - reg32_write(0x3c900214,0x12); reg32_write(0x3c1003f4,0xf); reg32_write(0x3c040044,0x1); reg32_write(0x3c040048,0x1); -- 2.17.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox