* [PATCH 1/6] ARM: i.MX8M: Expose code to query cpu revision
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
@ 2018-08-10 19:04 ` Andrey Smirnov
2018-08-10 19:04 ` [PATCH 2/6] ARM: i.MX: boot: Fix accidental comma Andrey Smirnov
` (5 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-10 19:04 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
CPU revision information is needed for boot source detection, so
expose it as a small helper function and convert existing code to use
it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/imx8mq.c | 57 +++++++------------------
arch/arm/mach-imx/include/mach/imx8mq.h | 38 +++++++++++++++++
2 files changed, 53 insertions(+), 42 deletions(-)
create mode 100644 arch/arm/mach-imx/include/mach/imx8mq.h
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index 152f07bc1..bc463ee75 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -18,53 +18,13 @@
#include <asm/system.h>
#include <mach/generic.h>
#include <mach/revision.h>
-#include <mach/imx8mq-regs.h>
+#include <mach/imx8mq.h>
#include <linux/arm-smccc.h>
-#define IMX8MQ_ROM_VERSION_A0 0x800
-#define IMX8MQ_ROM_VERSION_B0 0x83C
-
-#define MX8MQ_ANATOP_DIGPROG 0x6c
-
#define FSL_SIP_BUILDINFO 0xC2000003
#define FSL_SIP_BUILDINFO_GET_COMMITHASH 0x00
-static void imx8mq_silicon_revision(void)
-{
- void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
- uint32_t reg = readl(anatop + MX8MQ_ANATOP_DIGPROG);
- uint32_t type = (reg >> 16) & 0xff;
- uint32_t rom_version;
- const char *cputypestr;
-
- reg &= 0xff;
-
- if (reg == IMX_CHIP_REV_1_0) {
- /*
- * For B0 chip, the DIGPROG is not updated, still TO1.0.
- * we have to check ROM version further
- */
- rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_A0));
- if (rom_version != IMX_CHIP_REV_1_0) {
- rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_B0));
- if (rom_version >= IMX_CHIP_REV_2_0)
- reg = IMX_CHIP_REV_2_0;
- }
- }
-
- switch (type) {
- case 0x82:
- cputypestr = "i.MX8MQ";
- break;
- default:
- cputypestr = "unknown i.MX8M";
- break;
- };
-
- imx_set_silicon_revision(cputypestr, reg);
-}
-
static int imx8mq_init_syscnt_frequency(void)
{
if (current_el() == 3) {
@@ -86,9 +46,22 @@ core_initcall(imx8mq_init_syscnt_frequency);
int imx8mq_init(void)
{
+ void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
+ uint32_t reg = readl(anatop + MX8MQ_ANATOP_DIGPROG);
+ uint32_t type = (reg >> 16) & 0xff;
struct arm_smccc_res res;
+ const char *cputypestr;
+
+ switch (type) {
+ case 0x82:
+ cputypestr = "i.MX8MQ";
+ break;
+ default:
+ cputypestr = "unknown i.MX8M";
+ break;
+ };
- imx8mq_silicon_revision();
+ imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision());
if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h
new file mode 100644
index 000000000..f51d4e664
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/imx8mq.h
@@ -0,0 +1,38 @@
+#ifndef __MACH_IMX8MQ_H
+#define __MACH_IMX8MQ_H
+
+#include <io.h>
+#include <mach/generic.h>
+#include <mach/imx8mq-regs.h>
+#include <mach/revision.h>
+
+#define IMX8MQ_ROM_VERSION_A0 0x800
+#define IMX8MQ_ROM_VERSION_B0 0x83C
+
+#define MX8MQ_ANATOP_DIGPROG 0x6c
+
+static inline int imx8mq_cpu_revision(void)
+{
+ void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
+ uint32_t revision = readl(anatop + MX8MQ_ANATOP_DIGPROG);
+
+ revision &= 0xff;
+
+ if (revision == IMX_CHIP_REV_1_0) {
+ uint32_t rom_version;
+ /*
+ * For B0 chip, the DIGPROG is not updated, still TO1.0.
+ * we have to check ROM version further
+ */
+ rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_A0));
+ if (rom_version != IMX_CHIP_REV_1_0) {
+ rom_version = readl(IOMEM(IMX8MQ_ROM_VERSION_B0));
+ if (rom_version >= IMX_CHIP_REV_2_0)
+ revision = IMX_CHIP_REV_2_0;
+ }
+ }
+
+ return revision;
+}
+
+#endif /* __MACH_IMX8_H */
\ No newline at end of file
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/6] ARM: i.MX: boot: Fix accidental comma
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
2018-08-10 19:04 ` [PATCH 1/6] ARM: i.MX8M: Expose code to query cpu revision Andrey Smirnov
@ 2018-08-10 19:04 ` Andrey Smirnov
2018-08-10 19:04 ` [PATCH 3/6] ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ Andrey Smirnov
` (4 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-10 19:04 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/boot.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index ab25f75b2..45170ab10 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -512,7 +512,7 @@ void imx7_get_boot_source(enum bootsource *src, int *instance)
*src = BOOTSOURCE_NAND;
break;
case 6:
- *src = BOOTSOURCE_SPI_NOR,
+ *src = BOOTSOURCE_SPI_NOR;
*instance = imx7_boot_instance_spi_nor(sbmr1);
break;
case 4:
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/6] ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
2018-08-10 19:04 ` [PATCH 1/6] ARM: i.MX8M: Expose code to query cpu revision Andrey Smirnov
2018-08-10 19:04 ` [PATCH 2/6] ARM: i.MX: boot: Fix accidental comma Andrey Smirnov
@ 2018-08-10 19:04 ` Andrey Smirnov
2018-08-13 7:10 ` Sascha Hauer
2018-08-10 19:04 ` [PATCH 4/6] ARM: i.MX8MQ: Replace magic numbers with named constants Andrey Smirnov
` (3 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-10 19:04 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
For both SoCs data found in SBMR registers reflects only the boot
source that was selected via pins of fuses and not the final boot
source that ended up being used by MaskROM code. Original i.MX7 boot
source detection implementation worked around that fact by having a
special code to correctly handle "Manufacturing Mode".
MaskROM in i.MX8MQ changed what SoC uses as recovery device and
switched it to be USDHC2. It also made recovery device switch always
enabled. Since correct actual boot source detection is important to
being able to properly boot i.MX8MQ (due to not using DCD to
initialize RAM), change the code to handle described exception.
Instead of trying to adapt original i.MX7 code with yet another
special case if(), change the whole thing to do what U-Boot does on
i.MX7 and i.MX8MQ and use "Boot information for software" provided by
recent (found in i.MX7 and i.MX8MQ) versions of MaskROM.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/boot.c | 97 +++++++++++++---------------------------
1 file changed, 30 insertions(+), 67 deletions(-)
diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 45170ab10..f1fc40479 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -28,6 +28,7 @@
#include <mach/imx6-regs.h>
#include <mach/imx7-regs.h>
#include <mach/vf610-regs.h>
+#include <mach/imx8mq.h>
static void
@@ -424,32 +425,12 @@ void imx6_boot_save_loc(void)
imx_boot_save_loc(imx6_get_boot_source);
}
-#define IMX7_SRC_SBMR1 0x58
-#define IMX7_SRC_SBMR2 0x70
+#define IMX7_BOOT_SW_INFO_POINTER_ADDR 0x000001E8
+#define IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 0x000009e8
+#define IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0 0x00000968
-/*
- * Re-defined to match the naming in reference manual
- */
-#define BOOT_CFG(m, l) BOOT_CFG1(m, l)
-
-#define IMX_BOOT_SW_INFO_POINTER_ADDR 0x000001E8
#define IMX_BOOT_SW_INFO_BDT_SD 0x1
-static unsigned int imx7_bootsource_internal(uint32_t r)
-{
- return FIELD_GET(BOOT_CFG(15, 12), r);
-}
-
-static int imx7_boot_instance_spi_nor(uint32_t r)
-{
- return FIELD_GET(BOOT_CFG(11, 9), r);
-}
-
-static int imx7_boot_instance_mmc(uint32_t r)
-{
- return FIELD_GET(BOOT_CFG(11, 10), r);
-}
-
struct imx_boot_sw_info {
uint8_t reserved_1;
uint8_t boot_device_instance;
@@ -460,60 +441,26 @@ struct imx_boot_sw_info {
uint32_t reserved_3[3];
} __packed;
-void imx7_get_boot_source(enum bootsource *src, int *instance)
+static void __imx7_get_boot_source(enum bootsource *src, int *instance,
+ unsigned long boot_sw_info_pointer_addr)
{
- void __iomem *src_base = IOMEM(MX7_SRC_BASE_ADDR);
- uint32_t sbmr1 = readl(src_base + IMX7_SRC_SBMR1);
- uint32_t sbmr2 = readl(src_base + IMX7_SRC_SBMR2);
+ const struct imx_boot_sw_info *info;
- if (imx6_bootsource_reserved(sbmr2))
- return;
+ info = (const void *)(unsigned long)
+ readl(boot_sw_info_pointer_addr);
- if (imx6_bootsource_serial(sbmr2)) {
- /*
- * On i.MX7 ROM code will try to bood from uSDHC1
- * before entering serial mode. It doesn't seem to be
- * reflected in the contents of SBMR1 in any way when
- * that happens, so we check "Boot_SW_Info" structure
- * (per 6.6.14 Boot information for software) to see
- * if that really happened.
- *
- * FIXME: This behaviour can be inhibited by
- * DISABLE_SDMMC_MFG, but location of that fuse
- * doesn't seem to be documented anywhere. Once that
- * is known it should be taken into account here.
- */
- const struct imx_boot_sw_info *info;
-
- info = (const void *)(unsigned long)
- readl(IMX_BOOT_SW_INFO_POINTER_ADDR);
-
- if (info->boot_device_type == IMX_BOOT_SW_INFO_BDT_SD) {
- *src = BOOTSOURCE_MMC;
- /*
- * We are expecting to only ever boot from
- * uSDHC1 here
- */
- WARN_ON(*instance = info->boot_device_instance);
- return;
- }
-
- *src = BOOTSOURCE_SERIAL;
- return;
- }
-
- switch (imx7_bootsource_internal(sbmr1)) {
+ switch (info->boot_device_type) {
case 1:
case 2:
*src = BOOTSOURCE_MMC;
- *instance = imx7_boot_instance_mmc(sbmr1);
+ *instance = info->boot_device_instance;
break;
case 3:
*src = BOOTSOURCE_NAND;
break;
case 6:
*src = BOOTSOURCE_SPI_NOR;
- *instance = imx7_boot_instance_spi_nor(sbmr1);
+ *instance = info->boot_device_instance;
break;
case 4:
*src = BOOTSOURCE_SPI; /* Really: qspi */
@@ -526,6 +473,11 @@ void imx7_get_boot_source(enum bootsource *src, int *instance)
}
}
+void imx7_get_boot_source(enum bootsource *src, int *instance)
+{
+ __imx7_get_boot_source(src, instance, IMX7_BOOT_SW_INFO_POINTER_ADDR);
+}
+
void imx7_boot_save_loc(void)
{
imx_boot_save_loc(imx7_get_boot_source);
@@ -626,6 +578,17 @@ void vf610_boot_save_loc(void)
}
void imx8_get_boot_source(enum bootsource *src, int *instance)
- __alias(imx7_get_boot_source);
+{
+ unsigned long addr;
+
+ addr = (imx8mq_cpu_revision() == IMX_CHIP_REV_1_0) ?
+ IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 :
+ IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0;
-void imx8_boot_save_loc(void) __alias(imx7_boot_save_loc);
+ __imx7_get_boot_source(src, instance, addr);
+}
+
+void imx8_boot_save_loc(void)
+{
+ imx_boot_save_loc(imx8_get_boot_source);
+}
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 3/6] ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ
2018-08-10 19:04 ` [PATCH 3/6] ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ Andrey Smirnov
@ 2018-08-13 7:10 ` Sascha Hauer
2018-08-13 14:15 ` Andrey Smirnov
0 siblings, 1 reply; 10+ messages in thread
From: Sascha Hauer @ 2018-08-13 7:10 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Fri, Aug 10, 2018 at 12:04:26PM -0700, Andrey Smirnov wrote:
> For both SoCs data found in SBMR registers reflects only the boot
> source that was selected via pins of fuses and not the final boot
> source that ended up being used by MaskROM code. Original i.MX7 boot
> source detection implementation worked around that fact by having a
> special code to correctly handle "Manufacturing Mode".
>
> MaskROM in i.MX8MQ changed what SoC uses as recovery device and
> switched it to be USDHC2. It also made recovery device switch always
> enabled. Since correct actual boot source detection is important to
> being able to properly boot i.MX8MQ (due to not using DCD to
> initialize RAM), change the code to handle described exception.
>
> Instead of trying to adapt original i.MX7 code with yet another
> special case if(), change the whole thing to do what U-Boot does on
> i.MX7 and i.MX8MQ and use "Boot information for software" provided by
> recent (found in i.MX7 and i.MX8MQ) versions of MaskROM.
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> arch/arm/mach-imx/boot.c | 97 +++++++++++++---------------------------
> 1 file changed, 30 insertions(+), 67 deletions(-)
>
> diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
> index 45170ab10..f1fc40479 100644
> --- a/arch/arm/mach-imx/boot.c
> +++ b/arch/arm/mach-imx/boot.c
> @@ -28,6 +28,7 @@
> #include <mach/imx6-regs.h>
> #include <mach/imx7-regs.h>
> #include <mach/vf610-regs.h>
> +#include <mach/imx8mq.h>
>
>
> static void
> @@ -424,32 +425,12 @@ void imx6_boot_save_loc(void)
> imx_boot_save_loc(imx6_get_boot_source);
> }
>
> -#define IMX7_SRC_SBMR1 0x58
> -#define IMX7_SRC_SBMR2 0x70
> +#define IMX7_BOOT_SW_INFO_POINTER_ADDR 0x000001E8
> +#define IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 0x000009e8
> +#define IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0 0x00000968
Uargh. Whatever they smoke @NXP, I hope it at least makes them feel
good. We are provided a "Boot information for software" pointer whose
address depends on the mask ROM version? So to use the information we
must first get the mask ROM version which itself is found at varying
offsets in the mask ROM?
Needless to say that my i.MX8MQ reference manual specifies the pointer
address to 0x1e8 which is obviously copied from the i.MX7 Manual without
adjusting.
Sascha
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^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 3/6] ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ
2018-08-13 7:10 ` Sascha Hauer
@ 2018-08-13 14:15 ` Andrey Smirnov
0 siblings, 0 replies; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-13 14:15 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Mon, Aug 13, 2018 at 12:10 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Fri, Aug 10, 2018 at 12:04:26PM -0700, Andrey Smirnov wrote:
> > For both SoCs data found in SBMR registers reflects only the boot
> > source that was selected via pins of fuses and not the final boot
> > source that ended up being used by MaskROM code. Original i.MX7 boot
> > source detection implementation worked around that fact by having a
> > special code to correctly handle "Manufacturing Mode".
> >
> > MaskROM in i.MX8MQ changed what SoC uses as recovery device and
> > switched it to be USDHC2. It also made recovery device switch always
> > enabled. Since correct actual boot source detection is important to
> > being able to properly boot i.MX8MQ (due to not using DCD to
> > initialize RAM), change the code to handle described exception.
> >
> > Instead of trying to adapt original i.MX7 code with yet another
> > special case if(), change the whole thing to do what U-Boot does on
> > i.MX7 and i.MX8MQ and use "Boot information for software" provided by
> > recent (found in i.MX7 and i.MX8MQ) versions of MaskROM.
> >
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> > arch/arm/mach-imx/boot.c | 97 +++++++++++++---------------------------
> > 1 file changed, 30 insertions(+), 67 deletions(-)
> >
> > diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
> > index 45170ab10..f1fc40479 100644
> > --- a/arch/arm/mach-imx/boot.c
> > +++ b/arch/arm/mach-imx/boot.c
> > @@ -28,6 +28,7 @@
> > #include <mach/imx6-regs.h>
> > #include <mach/imx7-regs.h>
> > #include <mach/vf610-regs.h>
> > +#include <mach/imx8mq.h>
> >
> >
> > static void
> > @@ -424,32 +425,12 @@ void imx6_boot_save_loc(void)
> > imx_boot_save_loc(imx6_get_boot_source);
> > }
> >
> > -#define IMX7_SRC_SBMR1 0x58
> > -#define IMX7_SRC_SBMR2 0x70
> > +#define IMX7_BOOT_SW_INFO_POINTER_ADDR 0x000001E8
> > +#define IMX8M_BOOT_SW_INFO_POINTER_ADDR_A0 0x000009e8
> > +#define IMX8M_BOOT_SW_INFO_POINTER_ADDR_B0 0x00000968
>
> Uargh. Whatever they smoke @NXP, I hope it at least makes them feel
> good. We are provided a "Boot information for software" pointer whose
> address depends on the mask ROM version?
AFAIK, yes. What I've been told by NXP folks is: "This could
potentially change with each ROM release update" (this meaning the
location address), so I am assuming this all depends on where linker
would place that global variable next time they recompile the MaskROM
code.
> So to use the information we must first get the mask ROM version which itself is found at varying
> offsets in the mask ROM?
True, although this seems like a genuine screw-up, whereas "NXP's
Moving Boot Info" sounds more like a "works as intended" kind of
scenario.
> Needless to say that my i.MX8MQ reference manual specifies the pointer
> address to 0x1e8 which is obviously copied from the i.MX7 Manual without
> adjusting.
Yeah, I discovered that the hard way. I brought it up to NXP folks and
there's supposed to be a ticket, to fix that discrepancy in the next
revision of the RM, somewhere within their corporate ticket tracking
system.
Thanks,
Andrey Smirnov
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 4/6] ARM: i.MX8MQ: Replace magic numbers with named constants
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
` (2 preceding siblings ...)
2018-08-10 19:04 ` [PATCH 3/6] ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ Andrey Smirnov
@ 2018-08-10 19:04 ` Andrey Smirnov
2018-08-10 19:04 ` [PATCH 5/6] ARM: i.MX8MQ: Add code to detect reset reason Andrey Smirnov
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-10 19:04 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/imx8mq.c | 6 +++---
arch/arm/mach-imx/include/mach/imx8mq.h | 11 ++++++++---
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index bc463ee75..95839f31d 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -47,13 +47,13 @@ core_initcall(imx8mq_init_syscnt_frequency);
int imx8mq_init(void)
{
void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
- uint32_t reg = readl(anatop + MX8MQ_ANATOP_DIGPROG);
- uint32_t type = (reg >> 16) & 0xff;
+ uint32_t type = FIELD_GET(DIGPROG_MAJOR,
+ readl(anatop + MX8MQ_ANATOP_DIGPROG));
struct arm_smccc_res res;
const char *cputypestr;
switch (type) {
- case 0x82:
+ case IMX8M_CPUTYPE_IMX8MQ:
cputypestr = "i.MX8MQ";
break;
default:
diff --git a/arch/arm/mach-imx/include/mach/imx8mq.h b/arch/arm/mach-imx/include/mach/imx8mq.h
index f51d4e664..f4a537d2b 100644
--- a/arch/arm/mach-imx/include/mach/imx8mq.h
+++ b/arch/arm/mach-imx/include/mach/imx8mq.h
@@ -5,18 +5,23 @@
#include <mach/generic.h>
#include <mach/imx8mq-regs.h>
#include <mach/revision.h>
+#include <linux/bitfield.h>
#define IMX8MQ_ROM_VERSION_A0 0x800
#define IMX8MQ_ROM_VERSION_B0 0x83C
#define MX8MQ_ANATOP_DIGPROG 0x6c
+#define DIGPROG_MAJOR GENMASK(23, 8)
+#define DIGPROG_MINOR GENMASK(7, 0)
+
+#define IMX8M_CPUTYPE_IMX8MQ 0x8240
+
static inline int imx8mq_cpu_revision(void)
{
void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
- uint32_t revision = readl(anatop + MX8MQ_ANATOP_DIGPROG);
-
- revision &= 0xff;
+ uint32_t revision = FIELD_GET(DIGPROG_MINOR,
+ readl(anatop + MX8MQ_ANATOP_DIGPROG));
if (revision == IMX_CHIP_REV_1_0) {
uint32_t rom_version;
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/6] ARM: i.MX8MQ: Add code to detect reset reason
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
` (3 preceding siblings ...)
2018-08-10 19:04 ` [PATCH 4/6] ARM: i.MX8MQ: Replace magic numbers with named constants Andrey Smirnov
@ 2018-08-10 19:04 ` Andrey Smirnov
2018-08-10 19:04 ` [PATCH 6/6] ARM: i.MX8MQ: Save boot location during initialization Andrey Smirnov
2018-08-13 7:12 ` [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Sascha Hauer
6 siblings, 0 replies; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-10 19:04 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Reset reason bits and their meaning seem to be identical between i.MX7
and i.MX8MQ. Share the definitions for the former and used it for the
latter.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/imx.c | 11 +++++++++++
arch/arm/mach-imx/imx7.c | 11 -----------
arch/arm/mach-imx/imx8mq.c | 6 ++++++
arch/arm/mach-imx/include/mach/reset-reason.h | 1 +
4 files changed, 18 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-imx/imx.c b/arch/arm/mach-imx/imx.c
index 6fe53f314..ad227663d 100644
--- a/arch/arm/mach-imx/imx.c
+++ b/arch/arm/mach-imx/imx.c
@@ -157,6 +157,17 @@ static int imx_init(void)
}
postcore_initcall(imx_init);
+const struct imx_reset_reason imx7_reset_reasons[] = {
+ { IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 },
+ { IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 },
+ { IMX_SRC_SRSR_JTAG_RESET, RESET_JTAG, 0 },
+ { IMX_SRC_SRSR_JTAG_SW_RESET, RESET_JTAG, 0 },
+ { IMX_SRC_SRSR_WDOG3_RESET, RESET_WDG, 1 },
+ { IMX_SRC_SRSR_WDOG4_RESET, RESET_WDG, 2 },
+ { IMX_SRC_SRSR_TEMPSENSE_RESET, RESET_THERM, 0 },
+ { /* sentinel */ }
+};
+
const struct imx_reset_reason imx_reset_reasons[] = {
{ IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 },
{ IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 },
diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c
index e49baf6f7..ca11e8345 100644
--- a/arch/arm/mach-imx/imx7.c
+++ b/arch/arm/mach-imx/imx7.c
@@ -168,17 +168,6 @@ static struct psci_ops imx7_psci_ops = {
.cpu_off = imx7_cpu_off,
};
-static const struct imx_reset_reason imx7_reset_reasons[] = {
- { IMX_SRC_SRSR_IPP_RESET, RESET_POR, 0 },
- { IMX_SRC_SRSR_WDOG1_RESET, RESET_WDG, 0 },
- { IMX_SRC_SRSR_JTAG_RESET, RESET_JTAG, 0 },
- { IMX_SRC_SRSR_JTAG_SW_RESET, RESET_JTAG, 0 },
- { IMX_SRC_SRSR_WDOG3_RESET, RESET_WDG, 1 },
- { IMX_SRC_SRSR_WDOG4_RESET, RESET_WDG, 2 },
- { IMX_SRC_SRSR_TEMPSENSE_RESET, RESET_THERM, 0 },
- { /* sentinel */ }
-};
-
int imx7_init(void)
{
const char *cputypestr;
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index 95839f31d..1d0bbcfdb 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -19,6 +19,7 @@
#include <mach/generic.h>
#include <mach/revision.h>
#include <mach/imx8mq.h>
+#include <mach/reset-reason.h>
#include <linux/arm-smccc.h>
@@ -47,6 +48,7 @@ core_initcall(imx8mq_init_syscnt_frequency);
int imx8mq_init(void)
{
void __iomem *anatop = IOMEM(MX8MQ_ANATOP_BASE_ADDR);
+ void __iomem *src = IOMEM(MX8MQ_SRC_BASE_ADDR);
uint32_t type = FIELD_GET(DIGPROG_MAJOR,
readl(anatop + MX8MQ_ANATOP_DIGPROG));
struct arm_smccc_res res;
@@ -62,6 +64,10 @@ int imx8mq_init(void)
};
imx_set_silicon_revision(cputypestr, imx8mq_cpu_revision());
+ /*
+ * Reset reasons seem to be identical to that of i.MX7
+ */
+ imx_set_reset_reason(src + IMX7_SRC_SRSR, imx7_reset_reasons);
if (IS_ENABLED(CONFIG_ARM_SMCCC) &&
IS_ENABLED(CONFIG_FIRMWARE_IMX8MQ_ATF)) {
diff --git a/arch/arm/mach-imx/include/mach/reset-reason.h b/arch/arm/mach-imx/include/mach/reset-reason.h
index 0f644a8c1..91a817189 100644
--- a/arch/arm/mach-imx/include/mach/reset-reason.h
+++ b/arch/arm/mach-imx/include/mach/reset-reason.h
@@ -33,5 +33,6 @@ struct imx_reset_reason {
void imx_set_reset_reason(void __iomem *, const struct imx_reset_reason *);
extern const struct imx_reset_reason imx_reset_reasons[];
+extern const struct imx_reset_reason imx7_reset_reasons[];
#endif /* __MACH_RESET_REASON_H__ */
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6/6] ARM: i.MX8MQ: Save boot location during initialization
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
` (4 preceding siblings ...)
2018-08-10 19:04 ` [PATCH 5/6] ARM: i.MX8MQ: Add code to detect reset reason Andrey Smirnov
@ 2018-08-10 19:04 ` Andrey Smirnov
2018-08-13 7:12 ` [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Sascha Hauer
6 siblings, 0 replies; 10+ messages in thread
From: Andrey Smirnov @ 2018-08-10 19:04 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/mach-imx/imx8mq.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/imx8mq.c b/arch/arm/mach-imx/imx8mq.c
index 1d0bbcfdb..4d00da5f0 100644
--- a/arch/arm/mach-imx/imx8mq.c
+++ b/arch/arm/mach-imx/imx8mq.c
@@ -54,6 +54,8 @@ int imx8mq_init(void)
struct arm_smccc_res res;
const char *cputypestr;
+ imx8_boot_save_loc();
+
switch (type) {
case IMX8M_CPUTYPE_IMX8MQ:
cputypestr = "i.MX8MQ";
--
2.17.1
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^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 0/6] i.MX8MQ boot source, reset reason, etc.
2018-08-10 19:04 [PATCH 0/6] i.MX8MQ boot source, reset reason, etc Andrey Smirnov
` (5 preceding siblings ...)
2018-08-10 19:04 ` [PATCH 6/6] ARM: i.MX8MQ: Save boot location during initialization Andrey Smirnov
@ 2018-08-13 7:12 ` Sascha Hauer
6 siblings, 0 replies; 10+ messages in thread
From: Sascha Hauer @ 2018-08-13 7:12 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Fri, Aug 10, 2018 at 12:04:23PM -0700, Andrey Smirnov wrote:
> Everyone:
>
> This series is a number of fixes and changes I made for boot source
> and reset reason detection on i.MX8MQ. Hopefully all of the changes
> are self-explanatory.
>
> Feedback is welcome!
>
> Thanks,
> Andrey Smirnov
Applied, thanks
Sascha
>
> Andrey Smirnov (6):
> ARM: i.MX8M: Expose code to query cpu revision
> ARM: i.MX: boot: Fix accidental comma
> ARM: i.MX: boot: Rework boot source detection for i.MX7 and i.MX8MQ
> ARM: i.MX8MQ: Replace magic numbers with named constants
> ARM: i.MX8MQ: Add code to detect reset reason
> ARM: i.MX8MQ: Save boot location during initialization
>
> arch/arm/mach-imx/boot.c | 99 ++++++-------------
> arch/arm/mach-imx/imx.c | 11 +++
> arch/arm/mach-imx/imx7.c | 11 ---
> arch/arm/mach-imx/imx8mq.c | 65 +++++-------
> arch/arm/mach-imx/include/mach/imx8mq.h | 43 ++++++++
> arch/arm/mach-imx/include/mach/reset-reason.h | 1 +
> 6 files changed, 109 insertions(+), 121 deletions(-)
> create mode 100644 arch/arm/mach-imx/include/mach/imx8mq.h
>
> --
> 2.17.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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^ permalink raw reply [flat|nested] 10+ messages in thread