* [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output @ 2018-08-21 6:28 Andrey Smirnov 2018-08-21 6:28 ` [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 Andrey Smirnov 2018-08-22 7:32 ` [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output Sascha Hauer 0 siblings, 2 replies; 7+ messages in thread From: Andrey Smirnov @ 2018-08-21 6:28 UTC (permalink / raw) To: barebox; +Cc: Andrey Smirnov Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- drivers/clk/imx/clk-sccg-pll.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index 951234367..bbfd95a11 100644 --- a/drivers/clk/imx/clk-sccg-pll.c +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -121,11 +121,9 @@ static void clk_pll1_unprepare(struct clk *clk) { struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); u32 val; -printf("%s %p\n", __func__, pll); val = readl(pll->base); val |= (1 << PLL_PD); writel(val, pll->base); -printf("fuschi\n"); } static unsigned long clk_pll2_recalc_rate(struct clk *clk, -- 2.17.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 2018-08-21 6:28 [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output Andrey Smirnov @ 2018-08-21 6:28 ` Andrey Smirnov 2018-08-22 7:31 ` Sascha Hauer 2018-08-22 7:32 ` [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output Sascha Hauer 1 sibling, 1 reply; 7+ messages in thread From: Andrey Smirnov @ 2018-08-21 6:28 UTC (permalink / raw) To: barebox; +Cc: Andrey Smirnov A number of PLL pairs (e.g. "sys1_pll1" and "sys1_pll2") share the same configuration register, so touching PD bit, as is done for SCCG_PLL2 in its prepare/unprepare methods will result in shut down of both PLLs. This is very undesireable, since attempting to re-parent a clock to "sys1_pll2" might result in complete system shutdown due to "sys1_pll1" being shut-down as a part of re-parenting process. There might be a better solution, but for now, just drop both methods for SCCG_PLL2, since this seem to work OK in practice. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> --- drivers/clk/imx/clk-sccg-pll.c | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c index bbfd95a11..cd1079b0c 100644 --- a/drivers/clk/imx/clk-sccg-pll.c +++ b/drivers/clk/imx/clk-sccg-pll.c @@ -103,29 +103,6 @@ static int clk_pll1_set_rate(struct clk *clk, unsigned long rate, return 0; } -static int clk_pll1_prepare(struct clk *clk) -{ - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); - u32 val; - - val = readl(pll->base); - val &= ~(1 << PLL_PD); - writel(val, pll->base); - - /* FIXME: PLL lock check */ - - return 0; -} - -static void clk_pll1_unprepare(struct clk *clk) -{ - struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); - u32 val; - val = readl(pll->base); - val |= (1 << PLL_PD); - writel(val, pll->base); -} - static unsigned long clk_pll2_recalc_rate(struct clk *clk, unsigned long parent_rate) { @@ -198,8 +175,6 @@ static const struct clk_ops clk_sccg_pll1_ops = { }; static const struct clk_ops clk_sccg_pll2_ops = { - .enable = clk_pll1_prepare, - .disable = clk_pll1_unprepare, .recalc_rate = clk_pll2_recalc_rate, .round_rate = clk_pll2_round_rate, .set_rate = clk_pll2_set_rate, -- 2.17.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 2018-08-21 6:28 ` [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 Andrey Smirnov @ 2018-08-22 7:31 ` Sascha Hauer 2018-08-23 1:07 ` Andrey Smirnov 0 siblings, 1 reply; 7+ messages in thread From: Sascha Hauer @ 2018-08-22 7:31 UTC (permalink / raw) To: Andrey Smirnov; +Cc: barebox On Mon, Aug 20, 2018 at 11:28:53PM -0700, Andrey Smirnov wrote: > A number of PLL pairs (e.g. "sys1_pll1" and "sys1_pll2") share the > same configuration register, so touching PD bit, as is done for > SCCG_PLL2 in its prepare/unprepare methods will result in shut down of > both PLLs. This is very undesireable, since attempting to re-parent a > clock to "sys1_pll2" might result in complete system shutdown due to > "sys1_pll1" being shut-down as a part of re-parenting process. I can imagine that there are problems with the way it is currently handled, but the scenario you describe shouldn't happen. "sys1_pll1" will never be shut down because it doesn't have a disable hook: static const struct clk_ops clk_sccg_pll1_ops = { .is_enabled = clk_pll1_is_prepared, .recalc_rate = clk_pll1_recalc_rate, .round_rate = clk_pll1_round_rate, .set_rate = clk_pll1_set_rate, }; static const struct clk_ops clk_sccg_pll2_ops = { .enable = clk_pll1_prepare, .disable = clk_pll1_unprepare, .recalc_rate = clk_pll2_recalc_rate, .round_rate = clk_pll2_round_rate, .set_rate = clk_pll2_set_rate, }; Have I missed something? Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 2018-08-22 7:31 ` Sascha Hauer @ 2018-08-23 1:07 ` Andrey Smirnov 2018-08-23 6:54 ` Sascha Hauer 0 siblings, 1 reply; 7+ messages in thread From: Andrey Smirnov @ 2018-08-23 1:07 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List On Wed, Aug 22, 2018 at 12:31 AM Sascha Hauer <s.hauer@pengutronix.de> wrote: > > On Mon, Aug 20, 2018 at 11:28:53PM -0700, Andrey Smirnov wrote: > > A number of PLL pairs (e.g. "sys1_pll1" and "sys1_pll2") share the > > same configuration register, so touching PD bit, as is done for > > SCCG_PLL2 in its prepare/unprepare methods will result in shut down of > > both PLLs. This is very undesireable, since attempting to re-parent a > > clock to "sys1_pll2" might result in complete system shutdown due to > > "sys1_pll1" being shut-down as a part of re-parenting process. > > I can imagine that there are problems with the way it is currently > handled, but the scenario you describe shouldn't happen. "sys1_pll1" > will never be shut down because it doesn't have a disable hook: > > static const struct clk_ops clk_sccg_pll1_ops = { > .is_enabled = clk_pll1_is_prepared, > .recalc_rate = clk_pll1_recalc_rate, > .round_rate = clk_pll1_round_rate, > .set_rate = clk_pll1_set_rate, > }; > > static const struct clk_ops clk_sccg_pll2_ops = { > .enable = clk_pll1_prepare, > .disable = clk_pll1_unprepare, > .recalc_rate = clk_pll2_recalc_rate, > .round_rate = clk_pll2_round_rate, > .set_rate = clk_pll2_set_rate, > }; > > Have I missed something? > Yes, but that's probably due to my explanation being too vague, so let me try again. Both clocks "sys1_pll1" and "sys1_pll2" are controlled/configured via separate bit fields in the _same_ register. That register also has a single "powerdown"/"PD" bit that is shared between both PLLs and affects them both. The way code is currently implemented calling clk_disable() on "sys1_pll2" will clear PD bit and as a result "sys1_pll1" will be shut down as well. This is not that far-fetched of a scenario because a number of derived clocks that go out to individual peripherals are specified with CLK_OPS_PARENT_ENABLE, so trivial clock re-parenting like this one: https://github.com/ndreys/barebox/commit/802d1d5be1f1f3df996ba26b115dd3a55bc10c67 will result in hung system. Hopefully this does a better job of explaining what I was trying to fix. Thanks, Andrey Smirnov _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 2018-08-23 1:07 ` Andrey Smirnov @ 2018-08-23 6:54 ` Sascha Hauer 2018-08-28 19:25 ` Andrey Smirnov 0 siblings, 1 reply; 7+ messages in thread From: Sascha Hauer @ 2018-08-23 6:54 UTC (permalink / raw) To: Andrey Smirnov; +Cc: Barebox List On Wed, Aug 22, 2018 at 06:07:01PM -0700, Andrey Smirnov wrote: > On Wed, Aug 22, 2018 at 12:31 AM Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > > On Mon, Aug 20, 2018 at 11:28:53PM -0700, Andrey Smirnov wrote: > > > A number of PLL pairs (e.g. "sys1_pll1" and "sys1_pll2") share the > > > same configuration register, so touching PD bit, as is done for > > > SCCG_PLL2 in its prepare/unprepare methods will result in shut down of > > > both PLLs. This is very undesireable, since attempting to re-parent a > > > clock to "sys1_pll2" might result in complete system shutdown due to > > > "sys1_pll1" being shut-down as a part of re-parenting process. > > > > I can imagine that there are problems with the way it is currently > > handled, but the scenario you describe shouldn't happen. "sys1_pll1" > > will never be shut down because it doesn't have a disable hook: > > > > static const struct clk_ops clk_sccg_pll1_ops = { > > .is_enabled = clk_pll1_is_prepared, > > .recalc_rate = clk_pll1_recalc_rate, > > .round_rate = clk_pll1_round_rate, > > .set_rate = clk_pll1_set_rate, > > }; > > > > static const struct clk_ops clk_sccg_pll2_ops = { > > .enable = clk_pll1_prepare, > > .disable = clk_pll1_unprepare, > > .recalc_rate = clk_pll2_recalc_rate, > > .round_rate = clk_pll2_round_rate, > > .set_rate = clk_pll2_set_rate, > > }; > > > > Have I missed something? > > > > Yes, but that's probably due to my explanation being too vague, so let > me try again. Both clocks "sys1_pll1" and "sys1_pll2" are > controlled/configured via separate bit fields in the _same_ register. > That register also has a single "powerdown"/"PD" bit that is shared > between both PLLs and affects them both. The way code is currently > implemented calling clk_disable() on "sys1_pll2" will clear PD bit and > as a result "sys1_pll1" will be shut down as well. This is not that > far-fetched of a scenario because a number of derived clocks that go > out to individual peripherals are specified with > CLK_OPS_PARENT_ENABLE, so trivial clock re-parenting like this one: > https://github.com/ndreys/barebox/commit/802d1d5be1f1f3df996ba26b115dd3a55bc10c67 > will result in hung system. > > Hopefully this does a better job of explaining what I was trying to fix. Yeah, I thought you mixed up both PLLs, but reading your initial eplanation again you were right from the start. I agree that we should just remove the enable/disable hooks and see what we have to do when somebody actually tries to do something with the clocks (other than get the rate from) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 2018-08-23 6:54 ` Sascha Hauer @ 2018-08-28 19:25 ` Andrey Smirnov 0 siblings, 0 replies; 7+ messages in thread From: Andrey Smirnov @ 2018-08-28 19:25 UTC (permalink / raw) To: Sascha Hauer; +Cc: Barebox List On Wed, Aug 22, 2018 at 11:54 PM Sascha Hauer <s.hauer@pengutronix.de> wrote: > > On Wed, Aug 22, 2018 at 06:07:01PM -0700, Andrey Smirnov wrote: > > On Wed, Aug 22, 2018 at 12:31 AM Sascha Hauer <s.hauer@pengutronix.de> wrote: > > > > > > On Mon, Aug 20, 2018 at 11:28:53PM -0700, Andrey Smirnov wrote: > > > > A number of PLL pairs (e.g. "sys1_pll1" and "sys1_pll2") share the > > > > same configuration register, so touching PD bit, as is done for > > > > SCCG_PLL2 in its prepare/unprepare methods will result in shut down of > > > > both PLLs. This is very undesireable, since attempting to re-parent a > > > > clock to "sys1_pll2" might result in complete system shutdown due to > > > > "sys1_pll1" being shut-down as a part of re-parenting process. > > > > > > I can imagine that there are problems with the way it is currently > > > handled, but the scenario you describe shouldn't happen. "sys1_pll1" > > > will never be shut down because it doesn't have a disable hook: > > > > > > static const struct clk_ops clk_sccg_pll1_ops = { > > > .is_enabled = clk_pll1_is_prepared, > > > .recalc_rate = clk_pll1_recalc_rate, > > > .round_rate = clk_pll1_round_rate, > > > .set_rate = clk_pll1_set_rate, > > > }; > > > > > > static const struct clk_ops clk_sccg_pll2_ops = { > > > .enable = clk_pll1_prepare, > > > .disable = clk_pll1_unprepare, > > > .recalc_rate = clk_pll2_recalc_rate, > > > .round_rate = clk_pll2_round_rate, > > > .set_rate = clk_pll2_set_rate, > > > }; > > > > > > Have I missed something? > > > > > > > Yes, but that's probably due to my explanation being too vague, so let > > me try again. Both clocks "sys1_pll1" and "sys1_pll2" are > > controlled/configured via separate bit fields in the _same_ register. > > That register also has a single "powerdown"/"PD" bit that is shared > > between both PLLs and affects them both. The way code is currently > > implemented calling clk_disable() on "sys1_pll2" will clear PD bit and > > as a result "sys1_pll1" will be shut down as well. This is not that > > far-fetched of a scenario because a number of derived clocks that go > > out to individual peripherals are specified with > > CLK_OPS_PARENT_ENABLE, so trivial clock re-parenting like this one: > > https://github.com/ndreys/barebox/commit/802d1d5be1f1f3df996ba26b115dd3a55bc10c67 > > will result in hung system. > > > > Hopefully this does a better job of explaining what I was trying to fix. > > Yeah, I thought you mixed up both PLLs, but reading your initial > eplanation again you were right from the start. > > I agree that we should just remove the enable/disable hooks and see what > we have to do when somebody actually tries to do something with the > clocks (other than get the rate from) > Hmm, revisiting this in light of a related kernel thread [1], I think this problem can be avoided if reference counters of critical clocks are properly initialized. Unless you already applied this patch, I think we should just wait for the kernel code to land, I'll backport it and we can work on resolving any issues if they arise then. Thanks, Andrey Smirnov [1] https://lore.kernel.org/lkml/1534945703-4730-4-git-send-email-abel.vesa@nxp.com/T/#u _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output 2018-08-21 6:28 [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output Andrey Smirnov 2018-08-21 6:28 ` [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 Andrey Smirnov @ 2018-08-22 7:32 ` Sascha Hauer 1 sibling, 0 replies; 7+ messages in thread From: Sascha Hauer @ 2018-08-22 7:32 UTC (permalink / raw) To: Andrey Smirnov; +Cc: barebox On Mon, Aug 20, 2018 at 11:28:52PM -0700, Andrey Smirnov wrote: > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> > --- > drivers/clk/imx/clk-sccg-pll.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c > index 951234367..bbfd95a11 100644 > --- a/drivers/clk/imx/clk-sccg-pll.c > +++ b/drivers/clk/imx/clk-sccg-pll.c > @@ -121,11 +121,9 @@ static void clk_pll1_unprepare(struct clk *clk) > { > struct clk_sccg_pll *pll = to_clk_sccg_pll(clk); > u32 val; > -printf("%s %p\n", __func__, pll); > val = readl(pll->base); > val |= (1 << PLL_PD); > writel(val, pll->base); > -printf("fuschi\n"); > } Applied this one, thanks I'm glad I haven't used more explicit words as debug markers ;) Sascha -- Pengutronix e.K. | | Industrial Linux Solutions | http://www.pengutronix.de/ | Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-08-28 19:25 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-08-21 6:28 [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output Andrey Smirnov 2018-08-21 6:28 ` [PATCH 2/2] clk: clk-sccg-pll: Drop prepare/unprepare for SCCG_PLL2 Andrey Smirnov 2018-08-22 7:31 ` Sascha Hauer 2018-08-23 1:07 ` Andrey Smirnov 2018-08-23 6:54 ` Sascha Hauer 2018-08-28 19:25 ` Andrey Smirnov 2018-08-22 7:32 ` [PATCH 1/2] clk: clk-sccg-pll: Remove leftover debug output Sascha Hauer
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox