[PATCH 00/18] crypto: caam: Pull CAAM support improvements from Linux

[PATCH 00/18] crypto: caam: Pull CAAM support improvements from Linux

[Marcin Niestroj]

Hi,

This is a set of patches, which improve CAAM support. They sync CAAM
support with Linux v4.19-rc1. Applying them allows to use CAAM on
ARM IMX devices. Some of these patches had to be adapted to match
Barebox.

Marcin Niestroj (18):
  crypto: caam - fix RNG init descriptor ret. code checking
  crypto: caam - fix warning in APPEND_MATH_IMM_u64
  crypto: caam - fix writing to JQCR_MS when using service interface
  crypto: caam - handle core endianness != caam endianness
  crypto: caam - add support for iMX6UL
  crypto: caam - fix sparse warnings
  crypto: caam - trivial code clean-up
  crypto: caam - remove unreachable code in report_ccb_status()
  crypto: caam - constify pointer to descriptor buffer
  crypto: caam - avoid double inclusion in desc_constr.h
  crypto: caam - clean-up in caam_init_rng()
  crypto: caam - fix incorrect define
  crypto: caam - constify key data
  crypto: caam - fix endless loop when DECO acquire fails
  crypto: caam - do not use mem and emi_slow clock for imx7x
  crypto: caam - sync desc.h with Linux
  crypto: caam - staticize caam_get_era()
  crypto: caam - allow retrieving 'era' from register

 drivers/crypto/caam/caamrng.c     |   9 +-
 drivers/crypto/caam/ctrl.c        | 240 +++++++++++++++++++-----------
 drivers/crypto/caam/ctrl.h        |   1 -
 drivers/crypto/caam/desc.h        |  35 ++---
 drivers/crypto/caam/desc_constr.h | 118 +++++++++------
 drivers/crypto/caam/error.c       |   5 +-
 drivers/crypto/caam/jr.c          |  64 +++-----
 drivers/crypto/caam/regs.h        | 123 ++++++++++++++-
 8 files changed, 374 insertions(+), 221 deletions(-)

-- 
2.18.0


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[PATCH 01/18] crypto: caam - fix RNG init descriptor ret. code checking

[Marcin Niestroj]

Pick commit 62743a4145bb9c3fe090a48e10ddc0ebae85bfbf from Linux
upstream.

    crypto: caam - fix RNG init descriptor ret. code checking

    When successful, the descriptor that performs RNG initialization
    is allowed to return a status code of 7000_0000h, since last command
    in the descriptor is a JUMP HALT.

    Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 4deed8a19..eafff8ef0 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -170,7 +170,7 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 {
 	struct caam_drv_private *ctrlpriv = ctrldev->priv;
 	struct caam_ctrl __iomem *ctrl;
-	u32 *desc, status, rdsta_val;
+	u32 *desc, status = 0, rdsta_val;
 	int ret = 0, sh_idx;
 
 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
@@ -200,7 +200,8 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * CAAM eras), then try again.
 		 */
 		rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
-		if (status || !(rdsta_val & (1 << sh_idx)))
+		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
+		    !(rdsta_val & (1 << sh_idx)))
 			ret = -EAGAIN;
 		if (ret)
 			break;
-- 
2.18.0


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[PATCH 02/18] crypto: caam - fix warning in APPEND_MATH_IMM_u64

[Marcin Niestroj]

Pick commit c1f2cd21ed5335bfcf5dd1d3a05a2a83bae14c3a from Linux
upstream.

    crypto: caam - fix warning in APPEND_MATH_IMM_u64

    An implicit truncation is done when using a variable of 64 bits
    in MATH command:

    warning: large integer implicitly truncated to unsigned type [-Woverflow]

    Silence the compiler by feeding it with an explicit truncated value.

    Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com>
    Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 9f79fd7bd..c06ee734d 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -367,7 +367,7 @@ do { \
 	if (upper) \
 		append_u64(desc, data); \
 	else \
-		append_u32(desc, data); \
+		append_u32(desc, lower_32_bits(data));	\
 } while (0)
 
 #define append_math_add_imm_u64(desc, dest, src0, src1, data) \
-- 
2.18.0


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[PATCH 03/18] crypto: caam - fix writing to JQCR_MS when using service interface

[Marcin Niestroj]

Pick commit 9f587fa29f7e8ed6b8885cff51a51ace3ad85152 from Linux
upstream.

    crypto: caam - fix writing to JQCR_MS when using service interface

    Most significant part of JQCR (Job Queue Control Register) contains
    bits that control endianness: ILE - Immediate Little Endian,
    DWS - Double Word Swap.
    The bits are automatically set by the Job Queue Controller HW.

    Unfortunately these bits are cleared in SW when submitting descriptors
    via the register-based service interface.
    >From LS1021A:
    JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
    JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)

    This would cause problems on little endian caam for descriptors
    containing immediata data or double-word pointers.
    Currently there is no problem since the only descriptors ran through
    this interface are the ones that (un)instantiate RNG.

    Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index eafff8ef0..8ce9a859e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -117,7 +117,7 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 		flags |= DECO_JQCR_FOUR;
 
 	/* Instruct the DECO to execute it */
-	writel(flags, &deco->jr_ctl_hi);
+	setbits32(&deco->jr_ctl_hi, flags);
 
 	start = get_time_ns();
 	while ((deco_dbg_reg = readl(&deco->desc_dbg)) &
-- 
2.18.0


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[PATCH 04/18] crypto: caam - handle core endianness != caam endianness

[Marcin Niestroj]

Pick commit 261ea058f016bc04fa064348ad9bf39d94379381 from Linux
upstream.

    crypto: caam - handle core endianness != caam endianness

    There are SoCs like LS1043A where CAAM endianness (BE) does not match
    the default endianness of the core (LE).
    Moreover, there are requirements for the driver to handle cases like
    CPU_BIG_ENDIAN=y on ARM-based SoCs.
    This requires for a complete rewrite of the I/O accessors.

    PPC-specific accessors - {in,out}_{le,be}XX - are replaced with
    generic ones - io{read,write}[be]XX.

    Endianness is detected dynamically (at runtime) to allow for
    multiplatform kernels, for e.g. running the same kernel image
    on LS1043A (BE CAAM) and LS2080A (LE CAAM) armv8-based SoCs.

    While here: debugfs entries need to take into consideration the
    endianness of the core when displaying data. Add the necessary
    glue code so the entries remain the same, but they are properly
    read, regardless of the core and/or SEC endianness.

    Note: pdb.h fixes only what is currently being used (IPsec).

    Reviewed-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

As part of this patch rd_reg[8,16,32,64]() and wr_reg[8,16,32,64]()
helper functions are introduced. All readl() calls are replaced by
rd_reg32() and all writel() calls are replaced by wr_reg32().

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c        |  87 +++++++++++-----------
 drivers/crypto/caam/desc.h        |   3 +-
 drivers/crypto/caam/desc_constr.h |  42 +++++++----
 drivers/crypto/caam/jr.c          |  62 +++++-----------
 drivers/crypto/caam/regs.h        | 117 +++++++++++++++++++++++++++++-
 5 files changed, 206 insertions(+), 105 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 8ce9a859e..0baddf733 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -20,6 +20,9 @@
 #include "error.h"
 #include "ctrl.h"
 
+bool caam_little_end;
+EXPORT_SYMBOL(caam_little_end);
+
 /*
  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  * load the JDKEK, TDKEK and TDSK registers
@@ -83,10 +86,10 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 	deco = ctrlpriv->deco;
 
 	if (ctrlpriv->virt_en == 1) {
-		setbits32(&ctrl->deco_rsr, DECORSR_JR0);
+		clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 
 		start = get_time_ns();
-		while (!(readl(&ctrl->deco_rsr) & DECORSR_VALID)) {
+		while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID)) {
 			if (is_timeout(start, 100 * MSECOND)) {
 				dev_err(ctrldev, "DECO timed out\n");
 				return -ETIMEDOUT;
@@ -94,19 +97,19 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 		}
 	}
 
-	setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+	clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 
 	start = get_time_ns();
-	while (!(readl(&ctrl->deco_rq) & DECORR_DEN0)) {
+	while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0)) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(ctrldev, "failed to acquire DECO 0\n");
-			clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+			clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 			return -ETIMEDOUT;
 		}
 	}
 
 	for (i = 0; i < desc_len(desc); i++)
-		writel(*(desc + i), &deco->descbuf[i]);
+		wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 
 	flags = DECO_JQCR_WHL;
 	/*
@@ -117,10 +120,10 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 		flags |= DECO_JQCR_FOUR;
 
 	/* Instruct the DECO to execute it */
-	setbits32(&deco->jr_ctl_hi, flags);
+	clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 
 	start = get_time_ns();
-	while ((deco_dbg_reg = readl(&deco->desc_dbg)) &
+	while ((deco_dbg_reg = rd_reg32(&deco->desc_dbg)) &
 		 DESC_DBG_DECO_STAT_VALID) {
 		/*
 		 * If an error occured in the descriptor, then
@@ -131,14 +134,14 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 			break;
 	}
 
-	*status = readl(&deco->op_status_hi) &
+	*status = rd_reg32(&deco->op_status_hi) &
 		  DECO_OP_STATUS_HI_ERR_MASK;
 
 	if (ctrlpriv->virt_en == 1)
-		clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
+		clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 
 	/* Mark the DECO as free */
-	clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+	clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 
 	if (is_timeout(start, 100 * MSECOND))
 		return -EAGAIN;
@@ -199,7 +202,7 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * without any error (HW optimizations for later
 		 * CAAM eras), then try again.
 		 */
-		rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 		    !(rdsta_val & (1 << sh_idx)))
 			ret = -EAGAIN;
@@ -241,7 +244,7 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	r4tst = &ctrl->r4tst[0];
 
 	/* put RNG4 into program mode */
-	setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+	clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 
 	/*
 	 * Performance-wise, it does not make sense to
@@ -251,33 +254,33 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	 * time trying to set the values controlling the sample
 	 * frequency, the function simply returns.
 	 */
-	val = (readl(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
+	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 	      >> RTSDCTL_ENT_DLY_SHIFT;
 	if (ent_delay <= val) {
 		/* put RNG4 into run mode */
-		clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+		clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
 		return;
 	}
 
-	val = readl(&r4tst->rtsdctl);
+	val = rd_reg32(&r4tst->rtsdctl);
 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
-	writel(val, &r4tst->rtsdctl);
+	wr_reg32(&r4tst->rtsdctl, val);
 	/* min. freq. count, equal to 1/4 of the entropy sample length */
-	writel(ent_delay >> 2, &r4tst->rtfrqmin);
+	wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 	/* disable maximum frequency count */
-	writel(RTFRQMAX_DISABLE, &r4tst->rtfrqmax);
+	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 	/* read the control register */
-	val = readl(&r4tst->rtmctl);
+	val = rd_reg32(&r4tst->rtmctl);
 	/*
 	 * select raw sampling in both entropy shifter
 	 * and statistical checker
 	 */
-	setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
+	clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
 	/* put RNG4 into run mode */
-	clrbits32(&val, RTMCTL_PRGM);
+	clrsetbits_32(&val, RTMCTL_PRGM, 0);
 	/* write back the control register */
-	writel(val, &r4tst->rtmctl);
+	wr_reg32(&r4tst->rtmctl, val);
 }
 
 /**
@@ -379,8 +382,12 @@ static int caam_probe(struct device_d *dev)
 		dev_err(dev, "caam: of_iomap() failed\n");
 		return -ENOMEM;
 	}
+
+	caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
+				  (CSTA_PLEND | CSTA_ALT_PLEND));
+
 	/* Finding the page size for using the CTPR_MS register */
-	comp_params = readl(&ctrl->perfmon.comp_parms_ms);
+	comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 	pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 
 	/* Allocating the BLOCK_OFFSET based on the supported page size on
@@ -403,7 +410,7 @@ static int caam_probe(struct device_d *dev)
 	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 	 * long pointers in master configuration register
 	 */
-	clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK,
+	clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK,
 			MCFGR_AWCACHE_CACH | MCFGR_ARCACHE_MASK |
 			MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
 					  MCFGR_LONG_PTR : 0));
@@ -412,7 +419,7 @@ static int caam_probe(struct device_d *dev)
 	 *  Read the Compile Time paramters and SCFGR to determine
 	 * if Virtualization is enabled for this platform
 	 */
-	scfgr = readl(&ctrl->scfgr);
+	scfgr = rd_reg32(&ctrl->scfgr);
 
 	ctrlpriv->virt_en = 0;
 	if (comp_params & CTPR_MS_VIRT_EN_INCL) {
@@ -430,9 +437,9 @@ static int caam_probe(struct device_d *dev)
 	}
 
 	if (ctrlpriv->virt_en == 1)
-		setbits32(&ctrl->jrstart, JRSTART_JR0_START |
-			  JRSTART_JR1_START | JRSTART_JR2_START |
-			  JRSTART_JR3_START);
+		clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
+			      JRSTART_JR1_START | JRSTART_JR2_START |
+			      JRSTART_JR3_START);
 
 	/*
 	 * ERRATA:  mx6 devices have an issue wherein AXI bus transactions
@@ -443,8 +450,8 @@ static int caam_probe(struct device_d *dev)
 	 * to a depth of 1 (from it's default of 4) to preclude this situation
 	 * from occurring.
 	 */
-	writel((readl(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) |
-	       ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK), &ctrl->mcr);
+	wr_reg32(&ctrl->mcr, (rd_reg32(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) |
+			((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK));
 
 	/*
 	 * Detect and enable JobRs
@@ -487,15 +494,13 @@ static int caam_probe(struct device_d *dev)
 	}
 
 	/* Check to see if QI present. If so, enable */
-	ctrlpriv->qi_present =
-			!!(readl(&ctrl->perfmon.comp_parms_ms) &
-			   CTPR_MS_QI_MASK);
+	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 	if (ctrlpriv->qi_present) {
 		ctrlpriv->qi = (struct caam_queue_if __force *)
 			       ((uint8_t *)ctrl +
 				 BLOCK_OFFSET * QI_BLOCK_NUMBER);
 		/* This is all that's required to physically enable QI */
-		writel(QICTL_DQEN, &ctrlpriv->qi->qi_control_lo);
+		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 	}
 
 	/* If no QI and no rings specified, quit and go home */
@@ -505,7 +510,7 @@ static int caam_probe(struct device_d *dev)
 		return -ENOMEM;
 	}
 
-	cha_vid_ls = readl(&ctrl->perfmon.cha_id_ls);
+	cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 
 	/*
 	 * If SEC has RNG version >= 4 and RNG state handle has not been
@@ -513,7 +518,7 @@ static int caam_probe(struct device_d *dev)
 	 */
 	if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 		ctrlpriv->rng4_sh_init =
-			readl(&ctrl->r4tst[0].rdsta);
+			rd_reg32(&ctrl->r4tst[0].rdsta);
 		/*
 		 * If the secure keys (TDKEK, JDKEK, TDSK), were already
 		 * generated, signal this to the function that is instantiating
@@ -524,7 +529,7 @@ static int caam_probe(struct device_d *dev)
 		ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 		do {
 			int inst_handles =
-				readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+				rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 			/*
 			 * If either SH were instantiated by somebody else
 			 * (e.g. u-boot) then it is assumed that the entropy
@@ -560,7 +565,7 @@ static int caam_probe(struct device_d *dev)
 		ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 
 		/* Enable RDB bit so that RNG works faster */
-		setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
+		clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 	}
 
 	if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG)) {
@@ -573,8 +578,8 @@ static int caam_probe(struct device_d *dev)
 	}
 
 	/* NOTE: RTIC detection ought to go here, around Si time */
-	caam_id = (u64)readl(&ctrl->perfmon.caam_id_ms) << 32 |
-		  (u64)readl(&ctrl->perfmon.caam_id_ls);
+	caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
+		  (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 
 	/* Report "alive" for developer to see */
 	dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index a12eb8603..e964a5a93 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -30,8 +30,7 @@ struct sec4_sg_entry {
 	u32 ptr;
 #endif
 	u32 len;
-	u16 buf_pool_id;
-	u16 offset;
+	u32 bpid_offset;
 };
 
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index c06ee734d..cf86cc83b 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -5,6 +5,7 @@
  */
 
 #include "desc.h"
+#include "regs.h"
 
 #define IMMEDIATE (1 << 23)
 #define CAAM_CMD_SZ sizeof(u32)
@@ -32,7 +33,7 @@
 
 static inline int desc_len(u32 *desc)
 {
-	return *desc & HDR_DESCLEN_MASK;
+	return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
 }
 
 static inline int desc_bytes(void *desc)
@@ -52,7 +53,7 @@ static inline void *sh_desc_pdb(u32 *desc)
 
 static inline void init_desc(u32 *desc, u32 options)
 {
-	*desc = (options | HDR_ONE) + 1;
+	*desc = cpu_to_caam32((options | HDR_ONE) + 1);
 }
 
 static inline void init_sh_desc(u32 *desc, u32 options)
@@ -78,9 +79,10 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 {
 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
-	*offset = ptr;
+	*offset = cpu_to_caam_dma(ptr);
 
-	(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
+				CAAM_PTR_SZ / CAAM_CMD_SZ);
 }
 
 static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
@@ -99,16 +101,17 @@ static inline void append_data(u32 *desc, void *data, int len)
 	if (len) /* avoid sparse warning: memcpy with byte count of 0 */
 		memcpy(offset, data, len);
 
-	(*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
+				(len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
 }
 
 static inline void append_cmd(u32 *desc, u32 command)
 {
 	u32 *cmd = desc_end(desc);
 
-	*cmd = command;
+	*cmd = cpu_to_caam32(command);
 
-	(*desc)++;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + 1);
 }
 
 #define append_u32 append_cmd
@@ -117,16 +120,22 @@ static inline void append_u64(u32 *desc, u64 data)
 {
 	u32 *offset = desc_end(desc);
 
-	*offset = upper_32_bits(data);
-	*(++offset) = lower_32_bits(data);
+	/* Only 32-bit alignment is guaranteed in descriptor buffer */
+	if (caam_little_end) {
+		*offset = cpu_to_caam32(lower_32_bits(data));
+		*(++offset) = cpu_to_caam32(upper_32_bits(data));
+	} else {
+		*offset = cpu_to_caam32(upper_32_bits(data));
+		*(++offset) = cpu_to_caam32(lower_32_bits(data));
+	}
 
-	(*desc) += 2;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + 2);
 }
 
 /* Write command without affecting header, and return pointer to next word */
 static inline u32 *write_cmd(u32 *desc, u32 command)
 {
-	*desc = command;
+	*desc = cpu_to_caam32(command);
 
 	return desc + 1;
 }
@@ -168,14 +177,17 @@ APPEND_CMD_RET(move, MOVE)
 
 static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
 {
-	*jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc));
+	*jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
+				(desc_len(desc) - (jump_cmd - desc)));
 }
 
 static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
 {
-	*move_cmd &= ~MOVE_OFFSET_MASK;
-	*move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) &
-				 MOVE_OFFSET_MASK);
+	u32 val = caam32_to_cpu(*move_cmd);
+
+	val &= ~MOVE_OFFSET_MASK;
+	val |= (desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & MOVE_OFFSET_MASK;
+	*move_cmd = cpu_to_caam32(val);
 }
 
 #define APPEND_CMD(cmd, op) \
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 8f169d406..84396e41e 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -21,43 +21,16 @@
 #include "desc.h"
 #include "intern.h"
 
-/*
- * The DMA address registers in the JR are a pair of 32-bit registers.
- * The layout is:
- *
- *    base + 0x0000 : most-significant 32 bits
- *    base + 0x0004 : least-significant 32 bits
- *
- * The 32-bit version of this core therefore has to write to base + 0x0004
- * to set the 32-bit wide DMA address. This seems to be independent of the
- * endianness of the written/read data.
- */
-
-#define REG64_MS32(reg) ((u32 __iomem *)(reg))
-#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)
-
-static inline void wr_reg64(u64 __iomem *reg, u64 data)
-{
-	writel(data >> 32, REG64_MS32(reg));
-	writel(data, REG64_LS32(reg));
-}
-
-static inline u64 rd_reg64(u64 __iomem *reg)
-{
-	return ((u64)readl(REG64_MS32(reg)) << 32 |
-		(u64)readl(REG64_LS32(reg)));
-}
-
 static int caam_reset_hw_jr(struct device_d *dev)
 {
 	struct caam_drv_private_jr *jrp = dev->priv;
 	uint64_t start;
 
 	/* initiate flush (required prior to reset) */
-	writel(JRCR_RESET, &jrp->rregs->jrcommand);
+	wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
 
 	start = get_time_ns();
-	while ((readl(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
+	while ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
 	        JRINT_ERR_HALT_INPROGRESS) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(dev, "job ring %d timed out on flush\n",
@@ -67,10 +40,10 @@ static int caam_reset_hw_jr(struct device_d *dev)
 	}
 
 	/* initiate reset */
-	writel(JRCR_RESET, &jrp->rregs->jrcommand);
+	wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
 
 	start = get_time_ns();
-	while (readl(&jrp->rregs->jrcommand) & JRCR_RESET) {
+	while (rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(dev, "job ring %d timed out on reset\n",
 				jrp->ridx);
@@ -90,7 +63,7 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
 	void *userarg;
 	int found;
 
-	while (readl(&jrp->rregs->outring_used)) {
+	while (rd_reg32(&jrp->rregs->outring_used)) {
 		head = jrp->head;
 
 		sw_idx = tail = jrp->tail;
@@ -102,7 +75,7 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
 			sw_idx = (tail + i) & (JOBR_DEPTH - 1);
 
 			if (jrp->outring[hw_idx].desc ==
-			    jrp->entinfo[sw_idx].desc_addr_dma) {
+			    caam_dma_to_cpu(jrp->entinfo[sw_idx].desc_addr_dma)) {
 				found = 1;
 				break; /* found */
 			}
@@ -120,12 +93,12 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
 		usercall = jrp->entinfo[sw_idx].callbk;
 		userarg = jrp->entinfo[sw_idx].cbkarg;
 		userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
-		userstatus = jrp->outring[hw_idx].jrstatus;
+		userstatus = caam32_to_cpu(jrp->outring[hw_idx].jrstatus);
 
 		barrier();
 
 		/* set done */
-		writel(1, &jrp->rregs->outring_rmvd);
+		wr_reg32(&jrp->rregs->outring_rmvd, 1);
 
 		jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) &
 					   (JOBR_DEPTH - 1);
@@ -158,7 +131,7 @@ static int caam_jr_interrupt(struct caam_drv_private_jr *jrp)
 	u32 irqstate;
 
 	start = get_time_ns();
-	while (!(irqstate = readl(&jrp->rregs->jrintstatus))) {
+	while (!(irqstate = rd_reg32(&jrp->rregs->jrintstatus))) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(jrp->dev, "timeout waiting for interrupt\n");
 			return -ETIMEDOUT;
@@ -176,7 +149,7 @@ static int caam_jr_interrupt(struct caam_drv_private_jr *jrp)
 	}
 
 	/* Have valid interrupt at this point, just ACK and trigger */
-	writel(irqstate, &jrp->rregs->jrintstatus);
+	wr_reg32(&jrp->rregs->jrintstatus, irqstate);
 
 	return caam_jr_dequeue(jrp);
 }
@@ -218,7 +191,7 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 	struct caam_jrentry_info *head_entry;
 	int head, tail, desc_size;
 
-	desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32);
+	desc_size = (caam32_to_cpu(*desc) & HDR_JD_LENGTH_MASK) * sizeof(u32);
 
 	if (!dev->priv)
 		return -ENODEV;
@@ -227,7 +200,7 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 
 	head = jrp->head;
 	tail = jrp->tail;
-	if (!readl(&jrp->rregs->inpring_avail) ||
+	if (!rd_reg32(&jrp->rregs->inpring_avail) ||
 	    CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) {
 		return -EBUSY;
 	}
@@ -242,7 +215,8 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 	if (!jrp->inpring)
 		return -EIO;
 
-	jrp->inpring[jrp->inp_ring_write_index] = (dma_addr_t)desc;
+	jrp->inpring[jrp->inp_ring_write_index] =
+		cpu_to_caam_dma((dma_addr_t)desc);
 
 	barrier();
 
@@ -251,9 +225,9 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 	jrp->head = (head + 1) & (JOBR_DEPTH - 1);
 
 	barrier();
-	writel(1, &jrp->rregs->inpring_jobadd);
+	wr_reg32(&jrp->rregs->inpring_jobadd, 1);
 
-	clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
+	clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
 
 	return caam_jr_interrupt(jrp);
 }
@@ -301,8 +275,8 @@ static int caam_jr_init(struct device_d *dev)
 
 	wr_reg64(&jrp->rregs->inpring_base, dma_inpring);
 	wr_reg64(&jrp->rregs->outring_base, dma_outring);
-	writel(JOBR_DEPTH, &jrp->rregs->inpring_size);
-	writel(JOBR_DEPTH, &jrp->rregs->outring_size);
+	wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);
+	wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);
 
 	jrp->ringsize = JOBR_DEPTH;
 
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index b8ca5e396..d50e9ad69 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -10,9 +10,118 @@
 #include <linux/types.h>
 #include <io.h>
 
-/* These are common macros for Power, put here for ARMs */
-#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
-#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
+extern bool caam_little_end;
+
+#define caam_to_cpu(len)				\
+static inline u##len caam##len ## _to_cpu(u##len val)	\
+{							\
+	if (caam_little_end)				\
+		return le##len ## _to_cpu(val);		\
+	else						\
+		return be##len ## _to_cpu(val);		\
+}
+
+#define cpu_to_caam(len)				\
+static inline u##len cpu_to_caam##len(u##len val)	\
+{							\
+	if (caam_little_end)				\
+		return cpu_to_le##len(val);		\
+	else						\
+		return cpu_to_be##len(val);		\
+}
+
+caam_to_cpu(16)
+caam_to_cpu(32)
+caam_to_cpu(64)
+cpu_to_caam(16)
+cpu_to_caam(32)
+cpu_to_caam(64)
+
+static inline void wr_reg32(void __iomem *reg, u32 data)
+{
+	if (caam_little_end)
+		iowrite32(data, reg);
+	else
+		iowrite32be(data, reg);
+}
+
+static inline u32 rd_reg32(void __iomem *reg)
+{
+	if (caam_little_end)
+		return ioread32(reg);
+
+	return ioread32be(reg);
+}
+
+static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
+{
+	if (caam_little_end)
+		iowrite32((ioread32(reg) & ~clear) | set, reg);
+	else
+		iowrite32be((ioread32be(reg) & ~clear) | set, reg);
+}
+
+/*
+ * The DMA address registers in the JR are a pair of 32-bit registers.
+ * The layout is:
+ *
+ *    base + 0x0000 : most-significant 32 bits
+ *    base + 0x0004 : least-significant 32 bits
+ *
+ * The 32-bit version of this core therefore has to write to base + 0x0004
+ * to set the 32-bit wide DMA address. This seems to be independent of the
+ * endianness of the written/read data.
+ */
+
+#ifdef CONFIG_64BIT
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+	if (caam_little_end)
+		iowrite64(data, reg);
+	else
+		iowrite64be(data, reg);
+}
+
+static inline void rd_reg64(void __iomem *reg)
+{
+	if (caam_little_end)
+		ioread64(reg);
+	else
+		ioread64be(reg);
+}
+#else /* CONFIG_64BIT */
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+	wr_reg32((u32 __iomem *)(reg), data >> 32);
+	wr_reg32((u32 __iomem *)(reg) + 1, data);
+}
+
+static inline u64 rd_reg64(void __iomem *reg)
+{
+	return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
+		(u64)rd_reg32((u32 __iomem *)(reg) + 1));
+}
+#endif /* CONFIG_64BIT */
+
+static inline u64 cpu_to_caam_dma64(dma_addr_t value)
+{
+	return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
+		 (u64)cpu_to_caam32(upper_32_bits(value)));
+}
+
+static inline u64 caam_dma64_to_cpu(u64 value)
+{
+	return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
+		 (u64)caam32_to_cpu(upper_32_bits(value)));
+}
+
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
+#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
+#else
+#define cpu_to_caam_dma(value) cpu_to_caam32(value)
+#define caam_dma_to_cpu(value) caam32_to_cpu(value)
+#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
 
 /*
  * jr_outentry
@@ -190,6 +299,8 @@ struct caam_perfmon {
 	u32 faultliodn;	/* FALR - Fault Address LIODN	*/
 	u32 faultdetail;	/* FADR - Fault Addr Detail	*/
 	u32 rsvd3;
+#define CSTA_PLEND		BIT(10)
+#define CSTA_ALT_PLEND		BIT(18)
 	u32 status;		/* CSTA - CAAM Status */
 	u32 smpart;		/* Secure Memory Partition Parameters */
 	u32 smvid;		/* Secure Memory Version ID */
-- 
2.18.0


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[PATCH 05/18] crypto: caam - add support for iMX6UL

[Marcin Niestroj]

Pick commit 4e518816a938187b3bfe1b62fa291d4e38dca06e from Linux
upstream.

    crypto: caam - add support for iMX6UL

    i.MX6UL does only require three clocks to enable CAAM module.

    Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
    Acked-by: Rob Herring <robh@kernel.org>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 0baddf733..55193f6ef 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -224,7 +224,8 @@ static void caam_remove(struct device_d *dev)
 	clk_disable(ctrlpriv->caam_ipg);
 	clk_disable(ctrlpriv->caam_mem);
 	clk_disable(ctrlpriv->caam_aclk);
-	clk_disable(ctrlpriv->caam_emi_slow);
+	if (ctrlpriv->caam_emi_slow)
+		clk_disable(ctrlpriv->caam_emi_slow);
 }
 
 /*
@@ -341,12 +342,14 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
-	if (IS_ERR(ctrlpriv->caam_emi_slow)) {
-		ret = PTR_ERR(ctrlpriv->caam_emi_slow);
-		dev_err(dev,
-			"can't identify CAAM emi slow clk: %d\n", ret);
-		return -ENODEV;
+	if (!of_machine_is_compatible("fsl,imx6ul")) {
+		ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
+		if (IS_ERR(ctrlpriv->caam_emi_slow)) {
+			ret = PTR_ERR(ctrlpriv->caam_emi_slow);
+			dev_err(dev,
+				"can't identify CAAM emi slow clk: %d\n", ret);
+			return -ENODEV;
+		}
 	}
 
 	ret = clk_enable(ctrlpriv->caam_ipg);
@@ -368,11 +371,13 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ret = clk_enable(ctrlpriv->caam_emi_slow);
-	if (ret < 0) {
-		dev_err(dev, "can't enable CAAM emi slow clock: %d\n",
-			ret);
-		return -ENODEV;
+	if (ctrlpriv->caam_emi_slow) {
+		ret = clk_enable(ctrlpriv->caam_emi_slow);
+		if (ret < 0) {
+			dev_err(dev, "can't enable CAAM emi slow clock: %d\n",
+				ret);
+			return -ENODEV;
+		}
 	}
 
 	/* Get configuration properties from device tree */
-- 
2.18.0


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[PATCH 06/18] crypto: caam - fix sparse warnings

[Marcin Niestroj]

Pick commit 8439e94fceb3812989bae41922567123cffd1cf7 from Linux
upstream.

    crypto: caam - fix sparse warnings

    Fix the following sparse warning (note that endianness issues
    are not not addressed in current patch):

    drivers/crypto/caam/ctrl.c:388:24: warning: incorrect type in argument 1 (different address spaces)
    drivers/crypto/caam/ctrl.c:388:24:    expected void [noderef] <asn:2>*reg
    drivers/crypto/caam/ctrl.c:388:24:    got unsigned int *<noident>
    drivers/crypto/caam/ctrl.c:390:24: warning: incorrect type in argument 1 (different address spaces)
    drivers/crypto/caam/ctrl.c:390:24:    expected void [noderef] <asn:2>*reg
    drivers/crypto/caam/ctrl.c:390:24:    got unsigned int *<noident>
    drivers/crypto/caam/ctrl.c:548:24: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:548:24:    expected struct caam_ctrl [noderef] <asn:2>*ctrl
    drivers/crypto/caam/ctrl.c:548:24:    got struct caam_ctrl *<noident>
    drivers/crypto/caam/ctrl.c:550:30: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:549:26: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:549:26:    expected struct caam_assurance [noderef] <asn:2>*assure
    drivers/crypto/caam/ctrl.c:549:26:    got struct caam_assurance *<noident>
    drivers/crypto/caam/ctrl.c:554:28: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:553:24: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:553:24:    expected struct caam_deco [noderef] <asn:2>*deco
    drivers/crypto/caam/ctrl.c:553:24:    got struct caam_deco *<noident>
    drivers/crypto/caam/ctrl.c:634:48: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:633:44: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:633:44:    expected struct caam_job_ring [noderef] <asn:2>*<noident>
    drivers/crypto/caam/ctrl.c:633:44:    got struct caam_job_ring *<noident>
    drivers/crypto/caam/ctrl.c:648:34: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:647:30: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:647:30:    expected struct caam_queue_if [noderef] <asn:2>*qi
    drivers/crypto/caam/ctrl.c:647:30:    got struct caam_queue_if *<noident>
    drivers/crypto/caam/ctrl.c:806:37: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:806:37:    expected void *data
    drivers/crypto/caam/ctrl.c:806:37:    got unsigned int [noderef] <asn:2>*
    drivers/crypto/caam/ctrl.c:814:38: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:814:38:    expected void *data
    drivers/crypto/caam/ctrl.c:814:38:    got unsigned int [noderef] <asn:2>*
    drivers/crypto/caam/ctrl.c:822:38: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:822:38:    expected void *data
    drivers/crypto/caam/ctrl.c:822:38:    got unsigned int [noderef] <asn:2>*
    drivers/crypto/caam/jr.c:492:23: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/jr.c:492:23:    expected struct caam_job_ring [noderef] <asn:2>*rregs
    drivers/crypto/caam/jr.c:492:23:    got struct caam_job_ring *<noident>
    drivers/crypto/caam/caampkc.c:398:35: warning: Using plain integer as NULL pointer
    drivers/crypto/caam/caampkc.c:444:35: warning: Using plain integer as NULL pointer

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 34 ++++++++++++++--------------------
 drivers/crypto/caam/jr.c   |  2 +-
 2 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 55193f6ef..0f9ad328e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -257,11 +257,8 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	 */
 	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 	      >> RTSDCTL_ENT_DLY_SHIFT;
-	if (ent_delay <= val) {
-		/* put RNG4 into run mode */
-		clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
-		return;
-	}
+	if (ent_delay <= val)
+		goto start_rng;
 
 	val = rd_reg32(&r4tst->rtsdctl);
 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
@@ -273,15 +270,12 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 	/* read the control register */
 	val = rd_reg32(&r4tst->rtmctl);
+start_rng:
 	/*
 	 * select raw sampling in both entropy shifter
-	 * and statistical checker
+	 * and statistical checker; ; put RNG4 into run mode
 	 */
-	clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
-	/* put RNG4 into run mode */
-	clrsetbits_32(&val, RTMCTL_PRGM, 0);
-	/* write back the control register */
-	wr_reg32(&r4tst->rtmctl, val);
+	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 }
 
 /**
@@ -403,12 +397,12 @@ static int caam_probe(struct device_d *dev)
 	else
 		BLOCK_OFFSET = PG_SIZE_64K;
 
-	ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
-	ctrlpriv->assure = (struct caam_assurance __force *)
-			   ((uint8_t *)ctrl +
+	ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
+	ctrlpriv->assure = (struct caam_assurance __iomem __force *)
+			   ((__force uint8_t *)ctrl +
 			    BLOCK_OFFSET * ASSURE_BLOCK_NUMBER);
-	ctrlpriv->deco = (struct caam_deco __force *)
-			 ((uint8_t *)ctrl +
+	ctrlpriv->deco = (struct caam_deco __iomem __force *)
+			 ((__force uint8_t *)ctrl +
 			  BLOCK_OFFSET * DECO_BLOCK_NUMBER);
 
 	/*
@@ -489,8 +483,8 @@ static int caam_probe(struct device_d *dev)
 			}
 
 			ctrlpriv->jrpdev[ring] = jrdev;
-			ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
-					     ((uint8_t *)ctrl +
+			ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
+					     ((__force uint8_t *)ctrl +
 					     (ring + JR_BLOCK_NUMBER) *
 					      BLOCK_OFFSET);
 			ctrlpriv->total_jobrs++;
@@ -501,8 +495,8 @@ static int caam_probe(struct device_d *dev)
 	/* Check to see if QI present. If so, enable */
 	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 	if (ctrlpriv->qi_present) {
-		ctrlpriv->qi = (struct caam_queue_if __force *)
-			       ((uint8_t *)ctrl +
+		ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
+			       ((__force uint8_t *)ctrl +
 				 BLOCK_OFFSET * QI_BLOCK_NUMBER);
 		/* This is all that's required to physically enable QI */
 		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 84396e41e..b602a7b0e 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -309,7 +309,7 @@ int caam_jr_probe(struct device_d *dev)
 	if (IS_ERR(ctrl))
 		return PTR_ERR(ctrl);
 
-	jrpriv->rregs = (struct caam_job_ring __force *)ctrl;
+	jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
 
 	/* Now do the platform independent part */
 	error = caam_jr_init(dev); /* now turn on hardware */
-- 
2.18.0


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[PATCH 07/18] crypto: caam - trivial code clean-up

[Marcin Niestroj]

Pick commit 4ca7c7d8fea1ffdc36df33578c1e68d0d6367b0c from Linux
upstream.

    crypto: caam - trivial code clean-up

    -replace offsetof with container_of
    -remove unused "assoc_nents", "iv_dma" from aead_edesc
    and fix comments
    -remove unused CAAM_MAX_IV_LENGTH #define

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/caamrng.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 51c267e3d..b62e3eb77 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -81,8 +81,7 @@ static void rng_done(struct device_d *jrdev, u32 *desc, u32 err, void *context)
 {
 	struct buf_data *bd;
 
-	bd = (struct buf_data *)((char *)desc -
-	      offsetof(struct buf_data, hw_desc));
+	bd = container_of(desc, struct buf_data, hw_desc[0]);
 
 	if (err)
 		caam_jr_strstatus(jrdev, err);
-- 
2.18.0


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[PATCH 08/18] crypto: caam - remove unreachable code in report_ccb_status()

[Marcin Niestroj]

Pick commit 9305dff7ab8b5e1aef2c4c5c733ce7e1dc345433 from Linux
upstream.

    crypto: caam - remove unreachable code in report_ccb_status()

    ERRID is a 4-bit field.
    Since err_id values are in [0..15] and err_id_list array size is 16,
    the condition "err_id < ARRAY_SIZE(err_id_list)" is always true.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/error.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index 9c875375d..766875b58 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -150,10 +150,9 @@ static void report_ccb_status(struct device_d *jrdev, const u32 status,
 	    strlen(rng_err_id_list[err_id])) {
 		/* RNG-only error */
 		err_str = rng_err_id_list[err_id];
-	} else if (err_id < ARRAY_SIZE(err_id_list))
+	} else {
 		err_str = err_id_list[err_id];
-	else
-		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+	}
 
 	/*
 	 * CCB ICV check failures are part of normal operation life;
-- 
2.18.0


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[PATCH 09/18] crypto: caam - constify pointer to descriptor buffer

[Marcin Niestroj]

Pick commit 24a4f14f0a93f6fff7e6ade5d99b402c831bbd96 from Linux
upstream.

    crypto: caam - constify pointer to descriptor buffer

    The pointer to the descriptor buffer is not touched,
    it always points to start of the descriptor buffer.
    Thus, make it const.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 69 ++++++++++++++++---------------
 1 file changed, 36 insertions(+), 33 deletions(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index cf86cc83b..305069e74 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -31,38 +31,39 @@
 			       LDST_SRCDST_WORD_DECOCTRL | \
 			       (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
 
-static inline int desc_len(u32 *desc)
+static inline int desc_len(u32 * const desc)
 {
 	return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
 }
 
-static inline int desc_bytes(void *desc)
+static inline int desc_bytes(void * const desc)
 {
 	return desc_len(desc) * CAAM_CMD_SZ;
 }
 
-static inline u32 *desc_end(u32 *desc)
+static inline u32 *desc_end(u32 * const desc)
 {
 	return desc + desc_len(desc);
 }
 
-static inline void *sh_desc_pdb(u32 *desc)
+static inline void *sh_desc_pdb(u32 * const desc)
 {
 	return desc + 1;
 }
 
-static inline void init_desc(u32 *desc, u32 options)
+static inline void init_desc(u32 * const desc, u32 options)
 {
 	*desc = cpu_to_caam32((options | HDR_ONE) + 1);
 }
 
-static inline void init_sh_desc(u32 *desc, u32 options)
+static inline void init_sh_desc(u32 * const desc, u32 options)
 {
 	PRINT_POS;
 	init_desc(desc, CMD_SHARED_DESC_HDR | options);
 }
 
-static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+static inline void init_sh_desc_pdb(u32 * const desc, u32 options,
+				size_t pdb_bytes)
 {
 	u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
 
@@ -70,12 +71,12 @@ static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
 		     options);
 }
 
-static inline void init_job_desc(u32 *desc, u32 options)
+static inline void init_job_desc(u32 * const desc, u32 options)
 {
 	init_desc(desc, CMD_DESC_HDR | options);
 }
 
-static inline void append_ptr(u32 *desc, dma_addr_t ptr)
+static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
 {
 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
@@ -85,8 +86,8 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 				CAAM_PTR_SZ / CAAM_CMD_SZ);
 }
 
-static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
-					u32 options)
+static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
+					int len, u32 options)
 {
 	PRINT_POS;
 	init_job_desc(desc, HDR_SHARED | options |
@@ -94,7 +95,7 @@ static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
 	append_ptr(desc, ptr);
 }
 
-static inline void append_data(u32 *desc, void *data, int len)
+static inline void append_data(u32 * const desc, void *data, int len)
 {
 	u32 *offset = desc_end(desc);
 
@@ -105,7 +106,7 @@ static inline void append_data(u32 *desc, void *data, int len)
 				(len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
 }
 
-static inline void append_cmd(u32 *desc, u32 command)
+static inline void append_cmd(u32 * const desc, u32 command)
 {
 	u32 *cmd = desc_end(desc);
 
@@ -116,7 +117,7 @@ static inline void append_cmd(u32 *desc, u32 command)
 
 #define append_u32 append_cmd
 
-static inline void append_u64(u32 *desc, u64 data)
+static inline void append_u64(u32 * const desc, u64 data)
 {
 	u32 *offset = desc_end(desc);
 
@@ -133,14 +134,14 @@ static inline void append_u64(u32 *desc, u64 data)
 }
 
 /* Write command without affecting header, and return pointer to next word */
-static inline u32 *write_cmd(u32 *desc, u32 command)
+static inline u32 *write_cmd(u32 * const desc, u32 command)
 {
 	*desc = cpu_to_caam32(command);
 
 	return desc + 1;
 }
 
-static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
+static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
 				  u32 command)
 {
 	append_cmd(desc, command | len);
@@ -148,7 +149,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
 }
 
 /* Write length after pointer, rather than inside command */
-static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
+static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
 					 unsigned int len, u32 command)
 {
 	append_cmd(desc, command);
@@ -157,7 +158,7 @@ static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
 	append_cmd(desc, len);
 }
 
-static inline void append_cmd_data(u32 *desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, void *data, int len,
 				   u32 command)
 {
 	append_cmd(desc, command | IMMEDIATE | len);
@@ -165,7 +166,7 @@ static inline void append_cmd_data(u32 *desc, void *data, int len,
 }
 
 #define APPEND_CMD_RET(cmd, op) \
-static inline u32 *append_##cmd(u32 *desc, u32 options) \
+static inline u32 *append_##cmd(u32 * const desc, u32 options) \
 { \
 	u32 *cmd = desc_end(desc); \
 	PRINT_POS; \
@@ -175,13 +176,13 @@ static inline u32 *append_##cmd(u32 *desc, u32 options) \
 APPEND_CMD_RET(jump, JUMP)
 APPEND_CMD_RET(move, MOVE)
 
-static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
+static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd)
 {
 	*jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
 				(desc_len(desc) - (jump_cmd - desc)));
 }
 
-static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
+static inline void set_move_tgt_here(u32 * const desc, u32 *move_cmd)
 {
 	u32 val = caam32_to_cpu(*move_cmd);
 
@@ -191,7 +192,7 @@ static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
 }
 
 #define APPEND_CMD(cmd, op) \
-static inline void append_##cmd(u32 *desc, u32 options) \
+static inline void append_##cmd(u32 * const desc, u32 options) \
 { \
 	PRINT_POS; \
 	append_cmd(desc, CMD_##op | options); \
@@ -199,7 +200,8 @@ static inline void append_##cmd(u32 *desc, u32 options) \
 APPEND_CMD(operation, OPERATION)
 
 #define APPEND_CMD_LEN(cmd, op) \
-static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
+static inline void append_##cmd(u32 * const desc, unsigned int len, \
+				u32 options) \
 { \
 	PRINT_POS; \
 	append_cmd(desc, CMD_##op | len | options); \
@@ -211,8 +213,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
 APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
 
 #define APPEND_CMD_PTR(cmd, op) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
-				u32 options) \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
+				unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
 	append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
@@ -222,8 +224,8 @@ APPEND_CMD_PTR(load, LOAD)
 APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
 APPEND_CMD_PTR(fifo_store, FIFO_STORE)
 
-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
-				u32 options)
+static inline void append_store(u32 * const desc, dma_addr_t ptr,
+				unsigned int len, u32 options)
 {
 	u32 cmd_src;
 
@@ -240,7 +242,8 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
 }
 
 #define APPEND_SEQ_PTR_INTLEN(cmd, op) \
-static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_seq_##cmd##_ptr_intlen(u32 * const desc, \
+						 dma_addr_t ptr, \
 						 unsigned int len, \
 						 u32 options) \
 { \
@@ -254,7 +257,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
 APPEND_SEQ_PTR_INTLEN(out, OUT)
 
 #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -264,7 +267,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
 APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
 
 #define APPEND_CMD_PTR_EXTLEN(cmd, op) \
-static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd##_extlen(u32 * const desc, dma_addr_t ptr, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -278,7 +281,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
  * the size of its type
  */
 #define APPEND_CMD_PTR_LEN(cmd, op, type) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
 				type len, u32 options) \
 { \
 	PRINT_POS; \
@@ -295,7 +298,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
  * from length of immediate data provided, e.g., split keys
  */
 #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
 					 unsigned int data_len, \
 					 unsigned int len, u32 options) \
 { \
@@ -306,7 +309,7 @@ static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
 APPEND_CMD_PTR_TO_IMM2(key, KEY);
 
 #define APPEND_CMD_RAW_IMM(cmd, op, type) \
-static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
+static inline void append_##cmd##_imm_##type(u32 * const desc, type immediate, \
 					     u32 options) \
 { \
 	PRINT_POS; \
-- 
2.18.0


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[PATCH 10/18] crypto: caam - avoid double inclusion in desc_constr.h

[Marcin Niestroj]

Pick commit cd373691d262afea523f4ae6ebf3dee3a204c8a7 from Linux
upstream.

    crypto: caam - avoid double inclusion in desc_constr.h

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 305069e74..3e2ee785b 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -4,6 +4,9 @@
  * Copyright 2008-2012 Freescale Semiconductor, Inc.
  */
 
+#ifndef DESC_CONSTR_H
+#define DESC_CONSTR_H
+
 #include "desc.h"
 #include "regs.h"
 
@@ -403,3 +406,5 @@ do { \
 	APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data)
 #define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \
 	APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data)
+
+#endif /* DESC_CONSTR_H */
-- 
2.18.0


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[PATCH 11/18] crypto: caam - clean-up in caam_init_rng()

[Marcin Niestroj]

Pick commit f366af462aef1dcaeab0f68b031e5c4c4eb860e1 from Linux
upstream.

    crypto: caam - clean-up in caam_init_rng()

    Clean up the code, as indicated by Coccinelle.

    Cc: Julia Lawall <julia.lawall@lip6.fr>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/caamrng.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index b62e3eb77..39a90568d 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -242,11 +242,7 @@ static int caam_init_rng(struct caam_rng_ctx *ctx, struct device_d *jrdev)
 	if (err)
 		return err;
 
-	err = caam_init_buf(ctx, 1);
-	if (err)
-		return err;
-
-	return 0;
+	return caam_init_buf(ctx, 1);
 }
 
 int caam_rng_probe(struct device_d *dev, struct device_d *jrdev)
-- 
2.18.0


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[PATCH 12/18] crypto: caam - fix incorrect define

[Marcin Niestroj]

Pick commit cc2f8ab5334a736fa0e775cfccf06c1e268667f0 from Linux
upstream.

    crypto: caam - fix incorrect define

    Fixes: 3ebfa92f49a6 ("crypto: caam - Add new macros for building extended SEC descriptors (> 64 words)")
    Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index e964a5a93..2b5f49967 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -1468,7 +1468,7 @@ struct sec4_sg_entry {
 #define MATH_SRC1_REG2		(0x02 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_REG3		(0x03 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_IMM		(0x04 << MATH_SRC1_SHIFT)
-#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC0_SHIFT)
+#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_INFIFO	(0x0a << MATH_SRC1_SHIFT)
 #define MATH_SRC1_OUTFIFO	(0x0b << MATH_SRC1_SHIFT)
 #define MATH_SRC1_ONE		(0x0c << MATH_SRC1_SHIFT)
-- 
2.18.0


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[PATCH 13/18] crypto: caam - constify key data

[Marcin Niestroj]

Pick commit 6674a4fdc6c2e690b28b7f590cd20871aeee55ad from Linux
upstream.

    crypto: caam - constify key data

    Key data is not modified, it is copied in the shared descriptor.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 3e2ee785b..0d5778ba0 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -98,7 +98,7 @@ static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
 	append_ptr(desc, ptr);
 }
 
-static inline void append_data(u32 * const desc, void *data, int len)
+static inline void append_data(u32 * const desc, const void *data, int len)
 {
 	u32 *offset = desc_end(desc);
 
@@ -161,7 +161,7 @@ static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
 	append_cmd(desc, len);
 }
 
-static inline void append_cmd_data(u32 * const desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, const void *data, int len,
 				   u32 command)
 {
 	append_cmd(desc, command | IMMEDIATE | len);
@@ -260,7 +260,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
 APPEND_SEQ_PTR_INTLEN(out, OUT)
 
 #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -301,7 +301,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
  * from length of immediate data provided, e.g., split keys
  */
 #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
 					 unsigned int data_len, \
 					 unsigned int len, u32 options) \
 { \
-- 
2.18.0


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[PATCH 14/18] crypto: caam - fix endless loop when DECO acquire fails

[Marcin Niestroj]

Pick commit 225ece3e7dad4cfc44cca38ce7a3a80f255ea8f1 from Linux
upstream.

    crypto: caam - fix endless loop when DECO acquire fails

    In case DECO0 cannot be acquired - i.e. run_descriptor_deco0() fails
    with -ENODEV, caam_probe() enters an endless loop:

    run_descriptor_deco0
            ret -ENODEV
            -> instantiate_rng
                    -ENODEV, overwritten by -EAGAIN
                    ret -EAGAIN
                    -> caam_probe
                            -EAGAIN results in endless loop

    It turns out the error path in instantiate_rng() is incorrect,
    the checks are done in the wrong order.

    Cc: <stable@vger.kernel.org> # 3.13+
    Fixes: 1005bccd7a4a6 ("crypto: caam - enable instantiation of all RNG4 state handles")
    Reported-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
    Suggested-by: Auer Lukas <lukas.auer@aisec.fraunhofer.de>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 0f9ad328e..681200594 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -202,12 +202,15 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * without any error (HW optimizations for later
 		 * CAAM eras), then try again.
 		 */
+		if (ret)
+			break;
+
 		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
-		    !(rdsta_val & (1 << sh_idx)))
+		    !(rdsta_val & (1 << sh_idx))) {
 			ret = -EAGAIN;
-		if (ret)
 			break;
+		}
 		dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 		/* Clear the contents before recreating the descriptor */
 		memset(desc, 0x00, CAAM_CMD_SZ * 7);
-- 
2.18.0


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[PATCH 15/18] crypto: caam - do not use mem and emi_slow clock for imx7x

[Marcin Niestroj]

Pick commit 699e491bac84a2069c7abeacf2f4367ecb19fa9c from Linux
upstream.

    crypto: caam - do not use mem and emi_slow clock for imx7x

    I.MX7x only use two clocks for the CAAM module, so make sure we do not try to
    use the mem and the emi_slow clock when running in that imx7d and imx7s machine
    type.

    Cc: "Horia Geantă" <horia.geanta@nxp.com>
    Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Peng Fan <peng.fan@nxp.com>
    Cc: "David S. Miller" <davem@davemloft.net>
    Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
    Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 681200594..24c98df5a 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -225,7 +225,8 @@ static void caam_remove(struct device_d *dev)
 
 	/* shut clocks off before finalizing shutdown */
 	clk_disable(ctrlpriv->caam_ipg);
-	clk_disable(ctrlpriv->caam_mem);
+	if (ctrlpriv->caam_mem)
+		clk_disable(ctrlpriv->caam_mem);
 	clk_disable(ctrlpriv->caam_aclk);
 	if (ctrlpriv->caam_emi_slow)
 		clk_disable(ctrlpriv->caam_emi_slow);
@@ -324,11 +325,15 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ctrlpriv->caam_mem = clk_get(dev, "mem");
-	if (IS_ERR(ctrlpriv->caam_mem)) {
-		ret = PTR_ERR(ctrlpriv->caam_mem);
-		dev_err(dev, "can't identify CAAM secure mem clk: %d\n", ret);
-		return -ENODEV;
+	if (!of_machine_is_compatible("fsl,imx7d") &&
+	    !of_machine_is_compatible("fsl,imx7s")) {
+		ctrlpriv->caam_mem = clk_get(dev, "mem");
+		if (IS_ERR(ctrlpriv->caam_mem)) {
+			ret = PTR_ERR(ctrlpriv->caam_mem);
+			dev_err(dev,
+				"can't identify CAAM mem clk: %d\n", ret);
+			return -ENODEV;
+		}
 	}
 
 	ctrlpriv->caam_aclk = clk_get(dev, "aclk");
@@ -339,7 +344,9 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	if (!of_machine_is_compatible("fsl,imx6ul")) {
+	if (!of_machine_is_compatible("fsl,imx6ul") &&
+	    !of_machine_is_compatible("fsl,imx7d") &&
+	    !of_machine_is_compatible("fsl,imx7s")) {
 		ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
 		if (IS_ERR(ctrlpriv->caam_emi_slow)) {
 			ret = PTR_ERR(ctrlpriv->caam_emi_slow);
@@ -355,11 +362,13 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ret = clk_enable(ctrlpriv->caam_mem);
-	if (ret < 0) {
-		dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
-			ret);
-		return -ENODEV;
+	if (ctrlpriv->caam_mem) {
+		ret = clk_enable(ctrlpriv->caam_mem);
+		if (ret < 0) {
+			dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
+				ret);
+			return -ENODEV;
+		}
 	}
 
 	ret = clk_enable(ctrlpriv->caam_aclk);
-- 
2.18.0


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[PATCH 16/18] crypto: caam - sync desc.h with Linux

[Marcin Niestroj]

Get rid of all differences between our and Linux content of desc.h, so
we prevent running into issues when porting new features in future.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc.h | 32 +++++++++-----------------------
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index 2b5f49967..ee873c07f 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -20,18 +20,7 @@
 #define SEC4_SG_BPID_MASK	0x000000ff
 #define SEC4_SG_BPID_SHIFT	16
 #define SEC4_SG_LEN_MASK	0x3fffffff	/* Excludes EXT and FINAL */
-#define SEC4_SG_OFFS_MASK	0x00001fff
-
-struct sec4_sg_entry {
-#ifdef CONFIG_64BIT
-	u64 ptr;
-#else
-	u32 reserved;
-	u32 ptr;
-#endif
-	u32 len;
-	u32 bpid_offset;
-};
+#define SEC4_SG_OFFSET_MASK	0x00001fff
 
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
 #define MAX_CAAM_DESCSIZE	64
@@ -95,8 +84,8 @@ struct sec4_sg_entry {
 #define HDR_ZRO			0x00008000
 
 /* Start Index or SharedDesc Length */
-#define HDR_START_IDX_MASK	0x3f
 #define HDR_START_IDX_SHIFT	16
+#define HDR_START_IDX_MASK	(0x3f << HDR_START_IDX_SHIFT)
 
 /* If shared descriptor header, 6-bit length */
 #define HDR_DESCLEN_SHR_MASK	0x3f
@@ -126,10 +115,10 @@ struct sec4_sg_entry {
 #define HDR_PROP_DNR		0x00000800
 
 /* JobDesc/SharedDesc share property */
-#define HDR_SD_SHARE_MASK	0x03
 #define HDR_SD_SHARE_SHIFT	8
-#define HDR_JD_SHARE_MASK	0x07
+#define HDR_SD_SHARE_MASK	(0x03 << HDR_SD_SHARE_SHIFT)
 #define HDR_JD_SHARE_SHIFT	8
+#define HDR_JD_SHARE_MASK	(0x07 << HDR_JD_SHARE_SHIFT)
 
 #define HDR_SHARE_NEVER		(0x00 << HDR_SD_SHARE_SHIFT)
 #define HDR_SHARE_WAIT		(0x01 << HDR_SD_SHARE_SHIFT)
@@ -240,7 +229,7 @@ struct sec4_sg_entry {
 #define LDST_SRCDST_WORD_DECO_MATH2	(0x0a << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_DECO_AAD_SZ	(0x0b << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_DECO_MATH3	(0x0b << LDST_SRCDST_SHIFT)
-#define LDST_SRCDST_WORD_CLASS1_ICV_SZ	(0x0c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS1_IV_SZ	(0x0c << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_ALTDS_CLASS1	(0x0f << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_PKHA_A_SZ	(0x10 << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_PKHA_B_SZ	(0x11 << LDST_SRCDST_SHIFT)
@@ -405,10 +394,7 @@ struct sec4_sg_entry {
 #define FIFOST_TYPE_PKHA_N	 (0x08 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_A	 (0x0c << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_B	 (0x0d << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_JKEK	(0x10 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_TKEK	(0x11 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_JKEK	(0x14 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_TKEK	(0x15 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_E_JKEK	 (0x22 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_E_TKEK	 (0x23 << FIFOST_TYPE_SHIFT)
@@ -1130,8 +1116,8 @@ struct sec4_sg_entry {
 /* For non-protocol/alg-only op commands */
 #define OP_ALG_TYPE_SHIFT	24
 #define OP_ALG_TYPE_MASK	(0x7 << OP_ALG_TYPE_SHIFT)
-#define OP_ALG_TYPE_CLASS1	2
-#define OP_ALG_TYPE_CLASS2	4
+#define OP_ALG_TYPE_CLASS1	(2 << OP_ALG_TYPE_SHIFT)
+#define OP_ALG_TYPE_CLASS2	(4 << OP_ALG_TYPE_SHIFT)
 
 #define OP_ALG_ALGSEL_SHIFT	16
 #define OP_ALG_ALGSEL_MASK	(0xff << OP_ALG_ALGSEL_SHIFT)
@@ -1272,7 +1258,7 @@ struct sec4_sg_entry {
 #define OP_ALG_PKMODE_MOD_PRIMALITY	0x00f
 
 /* PKHA mode copy-memory functions */
-#define OP_ALG_PKMODE_SRC_REG_SHIFT	13
+#define OP_ALG_PKMODE_SRC_REG_SHIFT	17
 #define OP_ALG_PKMODE_SRC_REG_MASK	(7 << OP_ALG_PKMODE_SRC_REG_SHIFT)
 #define OP_ALG_PKMODE_DST_REG_SHIFT	10
 #define OP_ALG_PKMODE_DST_REG_MASK	(7 << OP_ALG_PKMODE_DST_REG_SHIFT)
-- 
2.18.0


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[PATCH 17/18] crypto: caam - staticize caam_get_era()

[Marcin Niestroj]

Pick commit b0039c00fbbbc3cb9c4b25852d81a2b4c193371d from Linux
upstream.

    crypto: caam - staticize caam_get_era()

    caam_get_era() is only used locally, so do not export this function
    and make it static instead.

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 3 +--
 drivers/crypto/caam/ctrl.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 24c98df5a..3b24c5ea2 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -286,7 +286,7 @@ start_rng:
  * caam_get_era() - Return the ERA of the SEC on SoC, based
  * on "sec-era" propery in the DTS. This property is updated by u-boot.
  **/
-int caam_get_era(void)
+static int caam_get_era(void)
 {
 	struct device_node *caam_node;
 	int ret;
@@ -297,7 +297,6 @@ int caam_get_era(void)
 
 	return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
 }
-EXPORT_SYMBOL(caam_get_era);
 
 /* Probe routine for CAAM top (controller) level */
 static int caam_probe(struct device_d *dev)
diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h
index cac5402a4..22b6ad5a7 100644
--- a/drivers/crypto/caam/ctrl.h
+++ b/drivers/crypto/caam/ctrl.h
@@ -8,6 +8,5 @@
 #define CTRL_H
 
 /* Prototypes for backend-level services exposed to APIs */
-int caam_get_era(void);
 
 #endif /* CTRL_H */
-- 
2.18.0


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[PATCH 18/18] crypto: caam - allow retrieving 'era' from register

[Marcin Niestroj]

Pick commit 654f2b937b389295581bcb4aa26011a63db7bc8f from Linux
upstream.

    crypto: caam - allow retrieving 'era' from register

    The 'era' information can be retrieved from CAAM registers, so
    introduce a caam_get_era_from_hw() function that gets it via register
    reads in case the 'fsl,sec-era' property is not passed in the device
    tree.

    This function is based on the U-Boot implementation from
    drivers/crypto/fsl/sec.c

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Tested-by: Breno Lima <breno.lima@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 56 +++++++++++++++++++++++++++++++++++---
 drivers/crypto/caam/regs.h |  6 ++++
 2 files changed, 58 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 3b24c5ea2..9e62bd6fd 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -282,11 +282,56 @@ start_rng:
 	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 }
 
+static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
+{
+	static const struct {
+		u16 ip_id;
+		u8 maj_rev;
+		u8 era;
+	} id[] = {
+		{0x0A10, 1, 1},
+		{0x0A10, 2, 2},
+		{0x0A12, 1, 3},
+		{0x0A14, 1, 3},
+		{0x0A14, 2, 4},
+		{0x0A16, 1, 4},
+		{0x0A10, 3, 4},
+		{0x0A11, 1, 4},
+		{0x0A18, 1, 4},
+		{0x0A11, 2, 5},
+		{0x0A12, 2, 5},
+		{0x0A13, 1, 5},
+		{0x0A1C, 1, 5}
+	};
+	u32 ccbvid, id_ms;
+	u8 maj_rev, era;
+	u16 ip_id;
+	int i;
+
+	ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
+	era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
+	if (era)	/* This is '0' prior to CAAM ERA-6 */
+		return era;
+
+	id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
+	ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
+	maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
+
+	for (i = 0; i < ARRAY_SIZE(id); i++)
+		if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
+			return id[i].era;
+
+	return -ENOTSUPP;
+}
+
 /**
  * caam_get_era() - Return the ERA of the SEC on SoC, based
- * on "sec-era" propery in the DTS. This property is updated by u-boot.
+ * on "sec-era" optional property in the DTS. This property is updated
+ * by u-boot.
+ * In case this property is not passed an attempt to retrieve the CAAM
+ * era via register reads will be made.
  **/
-static int caam_get_era(void)
+static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 {
 	struct device_node *caam_node;
 	int ret;
@@ -295,7 +340,10 @@ static int caam_get_era(void)
 	caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 	ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 
-	return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
+	if (!ret)
+		return prop;
+	else
+		return caam_get_era_from_hw(ctrl);
 }
 
 /* Probe routine for CAAM top (controller) level */
@@ -593,7 +641,7 @@ static int caam_probe(struct device_d *dev)
 
 	/* Report "alive" for developer to see */
 	dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
-		 caam_get_era());
+		 caam_get_era(ctrl));
 	dev_dbg(dev, "job rings = %d, qi = %d\n",
 		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index d50e9ad69..6c9d6d75a 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -307,11 +307,17 @@ struct caam_perfmon {
 
 	/* Component Instantiation Parameters			fe0-fff */
 	u32 rtic_id;		/* RVID - RTIC Version ID	*/
+#define CCBVID_ERA_MASK		0xff000000
+#define CCBVID_ERA_SHIFT	24
 	u32 ccb_id;		/* CCBVID - CCB Version ID	*/
 	u32 cha_id_ms;		/* CHAVID - CHA Version ID Most Significant*/
 	u32 cha_id_ls;		/* CHAVID - CHA Version ID Least Significant*/
 	u32 cha_num_ms;		/* CHANUM - CHA Number Most Significant	*/
 	u32 cha_num_ls;		/* CHANUM - CHA Number Least Significant*/
+#define SECVID_MS_IPID_MASK	0xffff0000
+#define SECVID_MS_IPID_SHIFT	16
+#define SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SECVID_MS_MAJ_REV_SHIFT	8
 	u32 caam_id_ms;		/* CAAMVID - CAAM Version ID MS	*/
 	u32 caam_id_ls;		/* CAAMVID - CAAM Version ID LS	*/
 };
-- 
2.18.0


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[PATCH 10/18] crypto: caam - avoid double inclusion in desc_constr.h

[Marcin Niestroj]

Pick commit cd373691d262afea523f4ae6ebf3dee3a204c8a7 from Linux
upstream.

    crypto: caam - avoid double inclusion in desc_constr.h

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 305069e74..3e2ee785b 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -4,6 +4,9 @@
  * Copyright 2008-2012 Freescale Semiconductor, Inc.
  */
 
+#ifndef DESC_CONSTR_H
+#define DESC_CONSTR_H
+
 #include "desc.h"
 #include "regs.h"
 
@@ -403,3 +406,5 @@ do { \
 	APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data)
 #define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \
 	APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data)
+
+#endif /* DESC_CONSTR_H */
-- 
2.18.0


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[PATCH 11/18] crypto: caam - clean-up in caam_init_rng()

[Marcin Niestroj]

Pick commit f366af462aef1dcaeab0f68b031e5c4c4eb860e1 from Linux
upstream.

    crypto: caam - clean-up in caam_init_rng()

    Clean up the code, as indicated by Coccinelle.

    Cc: Julia Lawall <julia.lawall@lip6.fr>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/caamrng.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index b62e3eb77..39a90568d 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -242,11 +242,7 @@ static int caam_init_rng(struct caam_rng_ctx *ctx, struct device_d *jrdev)
 	if (err)
 		return err;
 
-	err = caam_init_buf(ctx, 1);
-	if (err)
-		return err;
-
-	return 0;
+	return caam_init_buf(ctx, 1);
 }
 
 int caam_rng_probe(struct device_d *dev, struct device_d *jrdev)
-- 
2.18.0


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[PATCH 12/18] crypto: caam - fix incorrect define

[Marcin Niestroj]

Pick commit cc2f8ab5334a736fa0e775cfccf06c1e268667f0 from Linux
upstream.

    crypto: caam - fix incorrect define

    Fixes: 3ebfa92f49a6 ("crypto: caam - Add new macros for building extended SEC descriptors (> 64 words)")
    Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index e964a5a93..2b5f49967 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -1468,7 +1468,7 @@ struct sec4_sg_entry {
 #define MATH_SRC1_REG2		(0x02 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_REG3		(0x03 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_IMM		(0x04 << MATH_SRC1_SHIFT)
-#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC0_SHIFT)
+#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_INFIFO	(0x0a << MATH_SRC1_SHIFT)
 #define MATH_SRC1_OUTFIFO	(0x0b << MATH_SRC1_SHIFT)
 #define MATH_SRC1_ONE		(0x0c << MATH_SRC1_SHIFT)
-- 
2.18.0


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[PATCH 13/18] crypto: caam - constify key data

[Marcin Niestroj]

Pick commit 6674a4fdc6c2e690b28b7f590cd20871aeee55ad from Linux
upstream.

    crypto: caam - constify key data

    Key data is not modified, it is copied in the shared descriptor.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 3e2ee785b..0d5778ba0 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -98,7 +98,7 @@ static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
 	append_ptr(desc, ptr);
 }
 
-static inline void append_data(u32 * const desc, void *data, int len)
+static inline void append_data(u32 * const desc, const void *data, int len)
 {
 	u32 *offset = desc_end(desc);
 
@@ -161,7 +161,7 @@ static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
 	append_cmd(desc, len);
 }
 
-static inline void append_cmd_data(u32 * const desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, const void *data, int len,
 				   u32 command)
 {
 	append_cmd(desc, command | IMMEDIATE | len);
@@ -260,7 +260,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
 APPEND_SEQ_PTR_INTLEN(out, OUT)
 
 #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -301,7 +301,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
  * from length of immediate data provided, e.g., split keys
  */
 #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
 					 unsigned int data_len, \
 					 unsigned int len, u32 options) \
 { \
-- 
2.18.0


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[PATCH 14/18] crypto: caam - fix endless loop when DECO acquire fails

[Marcin Niestroj]

Pick commit 225ece3e7dad4cfc44cca38ce7a3a80f255ea8f1 from Linux
upstream.

    crypto: caam - fix endless loop when DECO acquire fails

    In case DECO0 cannot be acquired - i.e. run_descriptor_deco0() fails
    with -ENODEV, caam_probe() enters an endless loop:

    run_descriptor_deco0
            ret -ENODEV
            -> instantiate_rng
                    -ENODEV, overwritten by -EAGAIN
                    ret -EAGAIN
                    -> caam_probe
                            -EAGAIN results in endless loop

    It turns out the error path in instantiate_rng() is incorrect,
    the checks are done in the wrong order.

    Cc: <stable@vger.kernel.org> # 3.13+
    Fixes: 1005bccd7a4a6 ("crypto: caam - enable instantiation of all RNG4 state handles")
    Reported-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
    Suggested-by: Auer Lukas <lukas.auer@aisec.fraunhofer.de>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 0f9ad328e..681200594 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -202,12 +202,15 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * without any error (HW optimizations for later
 		 * CAAM eras), then try again.
 		 */
+		if (ret)
+			break;
+
 		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
-		    !(rdsta_val & (1 << sh_idx)))
+		    !(rdsta_val & (1 << sh_idx))) {
 			ret = -EAGAIN;
-		if (ret)
 			break;
+		}
 		dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 		/* Clear the contents before recreating the descriptor */
 		memset(desc, 0x00, CAAM_CMD_SZ * 7);
-- 
2.18.0


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[PATCH 15/18] crypto: caam - do not use mem and emi_slow clock for imx7x

[Marcin Niestroj]

Pick commit 699e491bac84a2069c7abeacf2f4367ecb19fa9c from Linux
upstream.

    crypto: caam - do not use mem and emi_slow clock for imx7x

    I.MX7x only use two clocks for the CAAM module, so make sure we do not try to
    use the mem and the emi_slow clock when running in that imx7d and imx7s machine
    type.

    Cc: "Horia Geantă" <horia.geanta@nxp.com>
    Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Peng Fan <peng.fan@nxp.com>
    Cc: "David S. Miller" <davem@davemloft.net>
    Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
    Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 681200594..24c98df5a 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -225,7 +225,8 @@ static void caam_remove(struct device_d *dev)
 
 	/* shut clocks off before finalizing shutdown */
 	clk_disable(ctrlpriv->caam_ipg);
-	clk_disable(ctrlpriv->caam_mem);
+	if (ctrlpriv->caam_mem)
+		clk_disable(ctrlpriv->caam_mem);
 	clk_disable(ctrlpriv->caam_aclk);
 	if (ctrlpriv->caam_emi_slow)
 		clk_disable(ctrlpriv->caam_emi_slow);
@@ -324,11 +325,15 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ctrlpriv->caam_mem = clk_get(dev, "mem");
-	if (IS_ERR(ctrlpriv->caam_mem)) {
-		ret = PTR_ERR(ctrlpriv->caam_mem);
-		dev_err(dev, "can't identify CAAM secure mem clk: %d\n", ret);
-		return -ENODEV;
+	if (!of_machine_is_compatible("fsl,imx7d") &&
+	    !of_machine_is_compatible("fsl,imx7s")) {
+		ctrlpriv->caam_mem = clk_get(dev, "mem");
+		if (IS_ERR(ctrlpriv->caam_mem)) {
+			ret = PTR_ERR(ctrlpriv->caam_mem);
+			dev_err(dev,
+				"can't identify CAAM mem clk: %d\n", ret);
+			return -ENODEV;
+		}
 	}
 
 	ctrlpriv->caam_aclk = clk_get(dev, "aclk");
@@ -339,7 +344,9 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	if (!of_machine_is_compatible("fsl,imx6ul")) {
+	if (!of_machine_is_compatible("fsl,imx6ul") &&
+	    !of_machine_is_compatible("fsl,imx7d") &&
+	    !of_machine_is_compatible("fsl,imx7s")) {
 		ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
 		if (IS_ERR(ctrlpriv->caam_emi_slow)) {
 			ret = PTR_ERR(ctrlpriv->caam_emi_slow);
@@ -355,11 +362,13 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ret = clk_enable(ctrlpriv->caam_mem);
-	if (ret < 0) {
-		dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
-			ret);
-		return -ENODEV;
+	if (ctrlpriv->caam_mem) {
+		ret = clk_enable(ctrlpriv->caam_mem);
+		if (ret < 0) {
+			dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
+				ret);
+			return -ENODEV;
+		}
 	}
 
 	ret = clk_enable(ctrlpriv->caam_aclk);
-- 
2.18.0


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[PATCH 16/18] crypto: caam - sync desc.h with Linux

[Marcin Niestroj]

Get rid of all differences between our and Linux content of desc.h, so
we prevent running into issues when porting new features in future.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc.h | 32 +++++++++-----------------------
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index 2b5f49967..ee873c07f 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -20,18 +20,7 @@
 #define SEC4_SG_BPID_MASK	0x000000ff
 #define SEC4_SG_BPID_SHIFT	16
 #define SEC4_SG_LEN_MASK	0x3fffffff	/* Excludes EXT and FINAL */
-#define SEC4_SG_OFFS_MASK	0x00001fff
-
-struct sec4_sg_entry {
-#ifdef CONFIG_64BIT
-	u64 ptr;
-#else
-	u32 reserved;
-	u32 ptr;
-#endif
-	u32 len;
-	u32 bpid_offset;
-};
+#define SEC4_SG_OFFSET_MASK	0x00001fff
 
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
 #define MAX_CAAM_DESCSIZE	64
@@ -95,8 +84,8 @@ struct sec4_sg_entry {
 #define HDR_ZRO			0x00008000
 
 /* Start Index or SharedDesc Length */
-#define HDR_START_IDX_MASK	0x3f
 #define HDR_START_IDX_SHIFT	16
+#define HDR_START_IDX_MASK	(0x3f << HDR_START_IDX_SHIFT)
 
 /* If shared descriptor header, 6-bit length */
 #define HDR_DESCLEN_SHR_MASK	0x3f
@@ -126,10 +115,10 @@ struct sec4_sg_entry {
 #define HDR_PROP_DNR		0x00000800
 
 /* JobDesc/SharedDesc share property */
-#define HDR_SD_SHARE_MASK	0x03
 #define HDR_SD_SHARE_SHIFT	8
-#define HDR_JD_SHARE_MASK	0x07
+#define HDR_SD_SHARE_MASK	(0x03 << HDR_SD_SHARE_SHIFT)
 #define HDR_JD_SHARE_SHIFT	8
+#define HDR_JD_SHARE_MASK	(0x07 << HDR_JD_SHARE_SHIFT)
 
 #define HDR_SHARE_NEVER		(0x00 << HDR_SD_SHARE_SHIFT)
 #define HDR_SHARE_WAIT		(0x01 << HDR_SD_SHARE_SHIFT)
@@ -240,7 +229,7 @@ struct sec4_sg_entry {
 #define LDST_SRCDST_WORD_DECO_MATH2	(0x0a << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_DECO_AAD_SZ	(0x0b << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_DECO_MATH3	(0x0b << LDST_SRCDST_SHIFT)
-#define LDST_SRCDST_WORD_CLASS1_ICV_SZ	(0x0c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS1_IV_SZ	(0x0c << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_ALTDS_CLASS1	(0x0f << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_PKHA_A_SZ	(0x10 << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_PKHA_B_SZ	(0x11 << LDST_SRCDST_SHIFT)
@@ -405,10 +394,7 @@ struct sec4_sg_entry {
 #define FIFOST_TYPE_PKHA_N	 (0x08 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_A	 (0x0c << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_B	 (0x0d << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_JKEK	(0x10 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_TKEK	(0x11 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_JKEK	(0x14 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_TKEK	(0x15 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_E_JKEK	 (0x22 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_E_TKEK	 (0x23 << FIFOST_TYPE_SHIFT)
@@ -1130,8 +1116,8 @@ struct sec4_sg_entry {
 /* For non-protocol/alg-only op commands */
 #define OP_ALG_TYPE_SHIFT	24
 #define OP_ALG_TYPE_MASK	(0x7 << OP_ALG_TYPE_SHIFT)
-#define OP_ALG_TYPE_CLASS1	2
-#define OP_ALG_TYPE_CLASS2	4
+#define OP_ALG_TYPE_CLASS1	(2 << OP_ALG_TYPE_SHIFT)
+#define OP_ALG_TYPE_CLASS2	(4 << OP_ALG_TYPE_SHIFT)
 
 #define OP_ALG_ALGSEL_SHIFT	16
 #define OP_ALG_ALGSEL_MASK	(0xff << OP_ALG_ALGSEL_SHIFT)
@@ -1272,7 +1258,7 @@ struct sec4_sg_entry {
 #define OP_ALG_PKMODE_MOD_PRIMALITY	0x00f
 
 /* PKHA mode copy-memory functions */
-#define OP_ALG_PKMODE_SRC_REG_SHIFT	13
+#define OP_ALG_PKMODE_SRC_REG_SHIFT	17
 #define OP_ALG_PKMODE_SRC_REG_MASK	(7 << OP_ALG_PKMODE_SRC_REG_SHIFT)
 #define OP_ALG_PKMODE_DST_REG_SHIFT	10
 #define OP_ALG_PKMODE_DST_REG_MASK	(7 << OP_ALG_PKMODE_DST_REG_SHIFT)
-- 
2.18.0


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[PATCH 17/18] crypto: caam - staticize caam_get_era()

[Marcin Niestroj]

Pick commit b0039c00fbbbc3cb9c4b25852d81a2b4c193371d from Linux
upstream.

    crypto: caam - staticize caam_get_era()

    caam_get_era() is only used locally, so do not export this function
    and make it static instead.

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 3 +--
 drivers/crypto/caam/ctrl.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 24c98df5a..3b24c5ea2 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -286,7 +286,7 @@ start_rng:
  * caam_get_era() - Return the ERA of the SEC on SoC, based
  * on "sec-era" propery in the DTS. This property is updated by u-boot.
  **/
-int caam_get_era(void)
+static int caam_get_era(void)
 {
 	struct device_node *caam_node;
 	int ret;
@@ -297,7 +297,6 @@ int caam_get_era(void)
 
 	return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
 }
-EXPORT_SYMBOL(caam_get_era);
 
 /* Probe routine for CAAM top (controller) level */
 static int caam_probe(struct device_d *dev)
diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h
index cac5402a4..22b6ad5a7 100644
--- a/drivers/crypto/caam/ctrl.h
+++ b/drivers/crypto/caam/ctrl.h
@@ -8,6 +8,5 @@
 #define CTRL_H
 
 /* Prototypes for backend-level services exposed to APIs */
-int caam_get_era(void);
 
 #endif /* CTRL_H */
-- 
2.18.0


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[PATCH 18/18] crypto: caam - allow retrieving 'era' from register

[Marcin Niestroj]

Pick commit 654f2b937b389295581bcb4aa26011a63db7bc8f from Linux
upstream.

    crypto: caam - allow retrieving 'era' from register

    The 'era' information can be retrieved from CAAM registers, so
    introduce a caam_get_era_from_hw() function that gets it via register
    reads in case the 'fsl,sec-era' property is not passed in the device
    tree.

    This function is based on the U-Boot implementation from
    drivers/crypto/fsl/sec.c

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Tested-by: Breno Lima <breno.lima@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 56 +++++++++++++++++++++++++++++++++++---
 drivers/crypto/caam/regs.h |  6 ++++
 2 files changed, 58 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 3b24c5ea2..9e62bd6fd 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -282,11 +282,56 @@ start_rng:
 	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 }
 
+static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
+{
+	static const struct {
+		u16 ip_id;
+		u8 maj_rev;
+		u8 era;
+	} id[] = {
+		{0x0A10, 1, 1},
+		{0x0A10, 2, 2},
+		{0x0A12, 1, 3},
+		{0x0A14, 1, 3},
+		{0x0A14, 2, 4},
+		{0x0A16, 1, 4},
+		{0x0A10, 3, 4},
+		{0x0A11, 1, 4},
+		{0x0A18, 1, 4},
+		{0x0A11, 2, 5},
+		{0x0A12, 2, 5},
+		{0x0A13, 1, 5},
+		{0x0A1C, 1, 5}
+	};
+	u32 ccbvid, id_ms;
+	u8 maj_rev, era;
+	u16 ip_id;
+	int i;
+
+	ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
+	era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
+	if (era)	/* This is '0' prior to CAAM ERA-6 */
+		return era;
+
+	id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
+	ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
+	maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
+
+	for (i = 0; i < ARRAY_SIZE(id); i++)
+		if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
+			return id[i].era;
+
+	return -ENOTSUPP;
+}
+
 /**
  * caam_get_era() - Return the ERA of the SEC on SoC, based
- * on "sec-era" propery in the DTS. This property is updated by u-boot.
+ * on "sec-era" optional property in the DTS. This property is updated
+ * by u-boot.
+ * In case this property is not passed an attempt to retrieve the CAAM
+ * era via register reads will be made.
  **/
-static int caam_get_era(void)
+static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 {
 	struct device_node *caam_node;
 	int ret;
@@ -295,7 +340,10 @@ static int caam_get_era(void)
 	caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 	ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 
-	return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
+	if (!ret)
+		return prop;
+	else
+		return caam_get_era_from_hw(ctrl);
 }
 
 /* Probe routine for CAAM top (controller) level */
@@ -593,7 +641,7 @@ static int caam_probe(struct device_d *dev)
 
 	/* Report "alive" for developer to see */
 	dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
-		 caam_get_era());
+		 caam_get_era(ctrl));
 	dev_dbg(dev, "job rings = %d, qi = %d\n",
 		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index d50e9ad69..6c9d6d75a 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -307,11 +307,17 @@ struct caam_perfmon {
 
 	/* Component Instantiation Parameters			fe0-fff */
 	u32 rtic_id;		/* RVID - RTIC Version ID	*/
+#define CCBVID_ERA_MASK		0xff000000
+#define CCBVID_ERA_SHIFT	24
 	u32 ccb_id;		/* CCBVID - CCB Version ID	*/
 	u32 cha_id_ms;		/* CHAVID - CHA Version ID Most Significant*/
 	u32 cha_id_ls;		/* CHAVID - CHA Version ID Least Significant*/
 	u32 cha_num_ms;		/* CHANUM - CHA Number Most Significant	*/
 	u32 cha_num_ls;		/* CHANUM - CHA Number Least Significant*/
+#define SECVID_MS_IPID_MASK	0xffff0000
+#define SECVID_MS_IPID_SHIFT	16
+#define SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SECVID_MS_MAJ_REV_SHIFT	8
 	u32 caam_id_ms;		/* CAAMVID - CAAM Version ID MS	*/
 	u32 caam_id_ls;		/* CAAMVID - CAAM Version ID LS	*/
 };
-- 
2.18.0


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[PATCH 00/18] crypto: caam: Pull CAAM support improvements from Linux

[Marcin Niestroj]

Hi,

This is a set of patches, which improve CAAM support. They sync CAAM
support with Linux v4.19-rc1. Applying them allows to use CAAM on
ARM IMX devices. Some of these patches had to be adapted to match
Barebox.

Marcin Niestroj (18):
  crypto: caam - fix RNG init descriptor ret. code checking
  crypto: caam - fix warning in APPEND_MATH_IMM_u64
  crypto: caam - fix writing to JQCR_MS when using service interface
  crypto: caam - handle core endianness != caam endianness
  crypto: caam - add support for iMX6UL
  crypto: caam - fix sparse warnings
  crypto: caam - trivial code clean-up
  crypto: caam - remove unreachable code in report_ccb_status()
  crypto: caam - constify pointer to descriptor buffer
  crypto: caam - avoid double inclusion in desc_constr.h
  crypto: caam - clean-up in caam_init_rng()
  crypto: caam - fix incorrect define
  crypto: caam - constify key data
  crypto: caam - fix endless loop when DECO acquire fails
  crypto: caam - do not use mem and emi_slow clock for imx7x
  crypto: caam - sync desc.h with Linux
  crypto: caam - staticize caam_get_era()
  crypto: caam - allow retrieving 'era' from register

 drivers/crypto/caam/caamrng.c     |   9 +-
 drivers/crypto/caam/ctrl.c        | 240 +++++++++++++++++++-----------
 drivers/crypto/caam/ctrl.h        |   1 -
 drivers/crypto/caam/desc.h        |  35 ++---
 drivers/crypto/caam/desc_constr.h | 118 +++++++++------
 drivers/crypto/caam/error.c       |   5 +-
 drivers/crypto/caam/jr.c          |  64 +++-----
 drivers/crypto/caam/regs.h        | 123 ++++++++++++++-
 8 files changed, 374 insertions(+), 221 deletions(-)

-- 
2.18.0


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[PATCH 01/18] crypto: caam - fix RNG init descriptor ret. code checking

[Marcin Niestroj]

Pick commit 62743a4145bb9c3fe090a48e10ddc0ebae85bfbf from Linux
upstream.

    crypto: caam - fix RNG init descriptor ret. code checking

    When successful, the descriptor that performs RNG initialization
    is allowed to return a status code of 7000_0000h, since last command
    in the descriptor is a JUMP HALT.

    Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 4deed8a19..eafff8ef0 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -170,7 +170,7 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 {
 	struct caam_drv_private *ctrlpriv = ctrldev->priv;
 	struct caam_ctrl __iomem *ctrl;
-	u32 *desc, status, rdsta_val;
+	u32 *desc, status = 0, rdsta_val;
 	int ret = 0, sh_idx;
 
 	ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
@@ -200,7 +200,8 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * CAAM eras), then try again.
 		 */
 		rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
-		if (status || !(rdsta_val & (1 << sh_idx)))
+		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
+		    !(rdsta_val & (1 << sh_idx)))
 			ret = -EAGAIN;
 		if (ret)
 			break;
-- 
2.18.0


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[PATCH 02/18] crypto: caam - fix warning in APPEND_MATH_IMM_u64

[Marcin Niestroj]

Pick commit c1f2cd21ed5335bfcf5dd1d3a05a2a83bae14c3a from Linux
upstream.

    crypto: caam - fix warning in APPEND_MATH_IMM_u64

    An implicit truncation is done when using a variable of 64 bits
    in MATH command:

    warning: large integer implicitly truncated to unsigned type [-Woverflow]

    Silence the compiler by feeding it with an explicit truncated value.

    Signed-off-by: Tudor Ambarus <tudor.ambarus@freescale.com>
    Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 9f79fd7bd..c06ee734d 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -367,7 +367,7 @@ do { \
 	if (upper) \
 		append_u64(desc, data); \
 	else \
-		append_u32(desc, data); \
+		append_u32(desc, lower_32_bits(data));	\
 } while (0)
 
 #define append_math_add_imm_u64(desc, dest, src0, src1, data) \
-- 
2.18.0


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[PATCH 03/18] crypto: caam - fix writing to JQCR_MS when using service interface

[Marcin Niestroj]

Pick commit 9f587fa29f7e8ed6b8885cff51a51ace3ad85152 from Linux
upstream.

    crypto: caam - fix writing to JQCR_MS when using service interface

    Most significant part of JQCR (Job Queue Control Register) contains
    bits that control endianness: ILE - Immediate Little Endian,
    DWS - Double Word Swap.
    The bits are automatically set by the Job Queue Controller HW.

    Unfortunately these bits are cleared in SW when submitting descriptors
    via the register-based service interface.
    >From LS1021A:
    JQCR_MS = 08080100 - before writing: ILE | DWS | SRC (JR0)
    JQCR_MS = 30000100 - after writing: WHL | FOUR | SRC (JR0)

    This would cause problems on little endian caam for descriptors
    containing immediata data or double-word pointers.
    Currently there is no problem since the only descriptors ran through
    this interface are the ones that (un)instantiate RNG.

    Signed-off-by: Horia Geant? <horia.geanta@freescale.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index eafff8ef0..8ce9a859e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -117,7 +117,7 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 		flags |= DECO_JQCR_FOUR;
 
 	/* Instruct the DECO to execute it */
-	writel(flags, &deco->jr_ctl_hi);
+	setbits32(&deco->jr_ctl_hi, flags);
 
 	start = get_time_ns();
 	while ((deco_dbg_reg = readl(&deco->desc_dbg)) &
-- 
2.18.0


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[PATCH 04/18] crypto: caam - handle core endianness != caam endianness

[Marcin Niestroj]

Pick commit 261ea058f016bc04fa064348ad9bf39d94379381 from Linux
upstream.

    crypto: caam - handle core endianness != caam endianness

    There are SoCs like LS1043A where CAAM endianness (BE) does not match
    the default endianness of the core (LE).
    Moreover, there are requirements for the driver to handle cases like
    CPU_BIG_ENDIAN=y on ARM-based SoCs.
    This requires for a complete rewrite of the I/O accessors.

    PPC-specific accessors - {in,out}_{le,be}XX - are replaced with
    generic ones - io{read,write}[be]XX.

    Endianness is detected dynamically (at runtime) to allow for
    multiplatform kernels, for e.g. running the same kernel image
    on LS1043A (BE CAAM) and LS2080A (LE CAAM) armv8-based SoCs.

    While here: debugfs entries need to take into consideration the
    endianness of the core when displaying data. Add the necessary
    glue code so the entries remain the same, but they are properly
    read, regardless of the core and/or SEC endianness.

    Note: pdb.h fixes only what is currently being used (IPsec).

    Reviewed-by: Tudor Ambarus <tudor-dan.ambarus@nxp.com>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

As part of this patch rd_reg[8,16,32,64]() and wr_reg[8,16,32,64]()
helper functions are introduced. All readl() calls are replaced by
rd_reg32() and all writel() calls are replaced by wr_reg32().

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c        |  87 +++++++++++-----------
 drivers/crypto/caam/desc.h        |   3 +-
 drivers/crypto/caam/desc_constr.h |  42 +++++++----
 drivers/crypto/caam/jr.c          |  62 +++++-----------
 drivers/crypto/caam/regs.h        | 117 +++++++++++++++++++++++++++++-
 5 files changed, 206 insertions(+), 105 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 8ce9a859e..0baddf733 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -20,6 +20,9 @@
 #include "error.h"
 #include "ctrl.h"
 
+bool caam_little_end;
+EXPORT_SYMBOL(caam_little_end);
+
 /*
  * Descriptor to instantiate RNG State Handle 0 in normal mode and
  * load the JDKEK, TDKEK and TDSK registers
@@ -83,10 +86,10 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 	deco = ctrlpriv->deco;
 
 	if (ctrlpriv->virt_en == 1) {
-		setbits32(&ctrl->deco_rsr, DECORSR_JR0);
+		clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
 
 		start = get_time_ns();
-		while (!(readl(&ctrl->deco_rsr) & DECORSR_VALID)) {
+		while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID)) {
 			if (is_timeout(start, 100 * MSECOND)) {
 				dev_err(ctrldev, "DECO timed out\n");
 				return -ETIMEDOUT;
@@ -94,19 +97,19 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 		}
 	}
 
-	setbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+	clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
 
 	start = get_time_ns();
-	while (!(readl(&ctrl->deco_rq) & DECORR_DEN0)) {
+	while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0)) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(ctrldev, "failed to acquire DECO 0\n");
-			clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+			clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 			return -ETIMEDOUT;
 		}
 	}
 
 	for (i = 0; i < desc_len(desc); i++)
-		writel(*(desc + i), &deco->descbuf[i]);
+		wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
 
 	flags = DECO_JQCR_WHL;
 	/*
@@ -117,10 +120,10 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 		flags |= DECO_JQCR_FOUR;
 
 	/* Instruct the DECO to execute it */
-	setbits32(&deco->jr_ctl_hi, flags);
+	clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
 
 	start = get_time_ns();
-	while ((deco_dbg_reg = readl(&deco->desc_dbg)) &
+	while ((deco_dbg_reg = rd_reg32(&deco->desc_dbg)) &
 		 DESC_DBG_DECO_STAT_VALID) {
 		/*
 		 * If an error occured in the descriptor, then
@@ -131,14 +134,14 @@ static inline int run_descriptor_deco0(struct device_d *ctrldev, u32 *desc,
 			break;
 	}
 
-	*status = readl(&deco->op_status_hi) &
+	*status = rd_reg32(&deco->op_status_hi) &
 		  DECO_OP_STATUS_HI_ERR_MASK;
 
 	if (ctrlpriv->virt_en == 1)
-		clrbits32(&ctrl->deco_rsr, DECORSR_JR0);
+		clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
 
 	/* Mark the DECO as free */
-	clrbits32(&ctrl->deco_rq, DECORR_RQD0ENABLE);
+	clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
 
 	if (is_timeout(start, 100 * MSECOND))
 		return -EAGAIN;
@@ -199,7 +202,7 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * without any error (HW optimizations for later
 		 * CAAM eras), then try again.
 		 */
-		rdsta_val = readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
 		    !(rdsta_val & (1 << sh_idx)))
 			ret = -EAGAIN;
@@ -241,7 +244,7 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	r4tst = &ctrl->r4tst[0];
 
 	/* put RNG4 into program mode */
-	setbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+	clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM);
 
 	/*
 	 * Performance-wise, it does not make sense to
@@ -251,33 +254,33 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	 * time trying to set the values controlling the sample
 	 * frequency, the function simply returns.
 	 */
-	val = (readl(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
+	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 	      >> RTSDCTL_ENT_DLY_SHIFT;
 	if (ent_delay <= val) {
 		/* put RNG4 into run mode */
-		clrbits32(&r4tst->rtmctl, RTMCTL_PRGM);
+		clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
 		return;
 	}
 
-	val = readl(&r4tst->rtsdctl);
+	val = rd_reg32(&r4tst->rtsdctl);
 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
 	      (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
-	writel(val, &r4tst->rtsdctl);
+	wr_reg32(&r4tst->rtsdctl, val);
 	/* min. freq. count, equal to 1/4 of the entropy sample length */
-	writel(ent_delay >> 2, &r4tst->rtfrqmin);
+	wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
 	/* disable maximum frequency count */
-	writel(RTFRQMAX_DISABLE, &r4tst->rtfrqmax);
+	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 	/* read the control register */
-	val = readl(&r4tst->rtmctl);
+	val = rd_reg32(&r4tst->rtmctl);
 	/*
 	 * select raw sampling in both entropy shifter
 	 * and statistical checker
 	 */
-	setbits32(&val, RTMCTL_SAMP_MODE_RAW_ES_SC);
+	clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
 	/* put RNG4 into run mode */
-	clrbits32(&val, RTMCTL_PRGM);
+	clrsetbits_32(&val, RTMCTL_PRGM, 0);
 	/* write back the control register */
-	writel(val, &r4tst->rtmctl);
+	wr_reg32(&r4tst->rtmctl, val);
 }
 
 /**
@@ -379,8 +382,12 @@ static int caam_probe(struct device_d *dev)
 		dev_err(dev, "caam: of_iomap() failed\n");
 		return -ENOMEM;
 	}
+
+	caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
+				  (CSTA_PLEND | CSTA_ALT_PLEND));
+
 	/* Finding the page size for using the CTPR_MS register */
-	comp_params = readl(&ctrl->perfmon.comp_parms_ms);
+	comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
 	pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
 
 	/* Allocating the BLOCK_OFFSET based on the supported page size on
@@ -403,7 +410,7 @@ static int caam_probe(struct device_d *dev)
 	 * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
 	 * long pointers in master configuration register
 	 */
-	clrsetbits_be32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK,
+	clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK | MCFGR_ARCACHE_MASK,
 			MCFGR_AWCACHE_CACH | MCFGR_ARCACHE_MASK |
 			MCFGR_WDENABLE | (sizeof(dma_addr_t) == sizeof(u64) ?
 					  MCFGR_LONG_PTR : 0));
@@ -412,7 +419,7 @@ static int caam_probe(struct device_d *dev)
 	 *  Read the Compile Time paramters and SCFGR to determine
 	 * if Virtualization is enabled for this platform
 	 */
-	scfgr = readl(&ctrl->scfgr);
+	scfgr = rd_reg32(&ctrl->scfgr);
 
 	ctrlpriv->virt_en = 0;
 	if (comp_params & CTPR_MS_VIRT_EN_INCL) {
@@ -430,9 +437,9 @@ static int caam_probe(struct device_d *dev)
 	}
 
 	if (ctrlpriv->virt_en == 1)
-		setbits32(&ctrl->jrstart, JRSTART_JR0_START |
-			  JRSTART_JR1_START | JRSTART_JR2_START |
-			  JRSTART_JR3_START);
+		clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
+			      JRSTART_JR1_START | JRSTART_JR2_START |
+			      JRSTART_JR3_START);
 
 	/*
 	 * ERRATA:  mx6 devices have an issue wherein AXI bus transactions
@@ -443,8 +450,8 @@ static int caam_probe(struct device_d *dev)
 	 * to a depth of 1 (from it's default of 4) to preclude this situation
 	 * from occurring.
 	 */
-	writel((readl(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) |
-	       ((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK), &ctrl->mcr);
+	wr_reg32(&ctrl->mcr, (rd_reg32(&ctrl->mcr) & ~(MCFGR_AXIPIPE_MASK)) |
+			((1 << MCFGR_AXIPIPE_SHIFT) & MCFGR_AXIPIPE_MASK));
 
 	/*
 	 * Detect and enable JobRs
@@ -487,15 +494,13 @@ static int caam_probe(struct device_d *dev)
 	}
 
 	/* Check to see if QI present. If so, enable */
-	ctrlpriv->qi_present =
-			!!(readl(&ctrl->perfmon.comp_parms_ms) &
-			   CTPR_MS_QI_MASK);
+	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 	if (ctrlpriv->qi_present) {
 		ctrlpriv->qi = (struct caam_queue_if __force *)
 			       ((uint8_t *)ctrl +
 				 BLOCK_OFFSET * QI_BLOCK_NUMBER);
 		/* This is all that's required to physically enable QI */
-		writel(QICTL_DQEN, &ctrlpriv->qi->qi_control_lo);
+		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
 	}
 
 	/* If no QI and no rings specified, quit and go home */
@@ -505,7 +510,7 @@ static int caam_probe(struct device_d *dev)
 		return -ENOMEM;
 	}
 
-	cha_vid_ls = readl(&ctrl->perfmon.cha_id_ls);
+	cha_vid_ls = rd_reg32(&ctrl->perfmon.cha_id_ls);
 
 	/*
 	 * If SEC has RNG version >= 4 and RNG state handle has not been
@@ -513,7 +518,7 @@ static int caam_probe(struct device_d *dev)
 	 */
 	if ((cha_vid_ls & CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT >= 4) {
 		ctrlpriv->rng4_sh_init =
-			readl(&ctrl->r4tst[0].rdsta);
+			rd_reg32(&ctrl->r4tst[0].rdsta);
 		/*
 		 * If the secure keys (TDKEK, JDKEK, TDSK), were already
 		 * generated, signal this to the function that is instantiating
@@ -524,7 +529,7 @@ static int caam_probe(struct device_d *dev)
 		ctrlpriv->rng4_sh_init &= RDSTA_IFMASK;
 		do {
 			int inst_handles =
-				readl(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
+				rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 			/*
 			 * If either SH were instantiated by somebody else
 			 * (e.g. u-boot) then it is assumed that the entropy
@@ -560,7 +565,7 @@ static int caam_probe(struct device_d *dev)
 		ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_IFMASK;
 
 		/* Enable RDB bit so that RNG works faster */
-		setbits32(&ctrl->scfgr, SCFGR_RDBENABLE);
+		clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
 	}
 
 	if (IS_ENABLED(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG)) {
@@ -573,8 +578,8 @@ static int caam_probe(struct device_d *dev)
 	}
 
 	/* NOTE: RTIC detection ought to go here, around Si time */
-	caam_id = (u64)readl(&ctrl->perfmon.caam_id_ms) << 32 |
-		  (u64)readl(&ctrl->perfmon.caam_id_ls);
+	caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
+		  (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
 
 	/* Report "alive" for developer to see */
 	dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index a12eb8603..e964a5a93 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -30,8 +30,7 @@ struct sec4_sg_entry {
 	u32 ptr;
 #endif
 	u32 len;
-	u16 buf_pool_id;
-	u16 offset;
+	u32 bpid_offset;
 };
 
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index c06ee734d..cf86cc83b 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -5,6 +5,7 @@
  */
 
 #include "desc.h"
+#include "regs.h"
 
 #define IMMEDIATE (1 << 23)
 #define CAAM_CMD_SZ sizeof(u32)
@@ -32,7 +33,7 @@
 
 static inline int desc_len(u32 *desc)
 {
-	return *desc & HDR_DESCLEN_MASK;
+	return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
 }
 
 static inline int desc_bytes(void *desc)
@@ -52,7 +53,7 @@ static inline void *sh_desc_pdb(u32 *desc)
 
 static inline void init_desc(u32 *desc, u32 options)
 {
-	*desc = (options | HDR_ONE) + 1;
+	*desc = cpu_to_caam32((options | HDR_ONE) + 1);
 }
 
 static inline void init_sh_desc(u32 *desc, u32 options)
@@ -78,9 +79,10 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 {
 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
-	*offset = ptr;
+	*offset = cpu_to_caam_dma(ptr);
 
-	(*desc) += CAAM_PTR_SZ / CAAM_CMD_SZ;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
+				CAAM_PTR_SZ / CAAM_CMD_SZ);
 }
 
 static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
@@ -99,16 +101,17 @@ static inline void append_data(u32 *desc, void *data, int len)
 	if (len) /* avoid sparse warning: memcpy with byte count of 0 */
 		memcpy(offset, data, len);
 
-	(*desc) += (len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) +
+				(len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
 }
 
 static inline void append_cmd(u32 *desc, u32 command)
 {
 	u32 *cmd = desc_end(desc);
 
-	*cmd = command;
+	*cmd = cpu_to_caam32(command);
 
-	(*desc)++;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + 1);
 }
 
 #define append_u32 append_cmd
@@ -117,16 +120,22 @@ static inline void append_u64(u32 *desc, u64 data)
 {
 	u32 *offset = desc_end(desc);
 
-	*offset = upper_32_bits(data);
-	*(++offset) = lower_32_bits(data);
+	/* Only 32-bit alignment is guaranteed in descriptor buffer */
+	if (caam_little_end) {
+		*offset = cpu_to_caam32(lower_32_bits(data));
+		*(++offset) = cpu_to_caam32(upper_32_bits(data));
+	} else {
+		*offset = cpu_to_caam32(upper_32_bits(data));
+		*(++offset) = cpu_to_caam32(lower_32_bits(data));
+	}
 
-	(*desc) += 2;
+	(*desc) = cpu_to_caam32(caam32_to_cpu(*desc) + 2);
 }
 
 /* Write command without affecting header, and return pointer to next word */
 static inline u32 *write_cmd(u32 *desc, u32 command)
 {
-	*desc = command;
+	*desc = cpu_to_caam32(command);
 
 	return desc + 1;
 }
@@ -168,14 +177,17 @@ APPEND_CMD_RET(move, MOVE)
 
 static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
 {
-	*jump_cmd = *jump_cmd | (desc_len(desc) - (jump_cmd - desc));
+	*jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
+				(desc_len(desc) - (jump_cmd - desc)));
 }
 
 static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
 {
-	*move_cmd &= ~MOVE_OFFSET_MASK;
-	*move_cmd = *move_cmd | ((desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) &
-				 MOVE_OFFSET_MASK);
+	u32 val = caam32_to_cpu(*move_cmd);
+
+	val &= ~MOVE_OFFSET_MASK;
+	val |= (desc_len(desc) << (MOVE_OFFSET_SHIFT + 2)) & MOVE_OFFSET_MASK;
+	*move_cmd = cpu_to_caam32(val);
 }
 
 #define APPEND_CMD(cmd, op) \
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 8f169d406..84396e41e 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -21,43 +21,16 @@
 #include "desc.h"
 #include "intern.h"
 
-/*
- * The DMA address registers in the JR are a pair of 32-bit registers.
- * The layout is:
- *
- *    base + 0x0000 : most-significant 32 bits
- *    base + 0x0004 : least-significant 32 bits
- *
- * The 32-bit version of this core therefore has to write to base + 0x0004
- * to set the 32-bit wide DMA address. This seems to be independent of the
- * endianness of the written/read data.
- */
-
-#define REG64_MS32(reg) ((u32 __iomem *)(reg))
-#define REG64_LS32(reg) ((u32 __iomem *)(reg) + 1)
-
-static inline void wr_reg64(u64 __iomem *reg, u64 data)
-{
-	writel(data >> 32, REG64_MS32(reg));
-	writel(data, REG64_LS32(reg));
-}
-
-static inline u64 rd_reg64(u64 __iomem *reg)
-{
-	return ((u64)readl(REG64_MS32(reg)) << 32 |
-		(u64)readl(REG64_LS32(reg)));
-}
-
 static int caam_reset_hw_jr(struct device_d *dev)
 {
 	struct caam_drv_private_jr *jrp = dev->priv;
 	uint64_t start;
 
 	/* initiate flush (required prior to reset) */
-	writel(JRCR_RESET, &jrp->rregs->jrcommand);
+	wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
 
 	start = get_time_ns();
-	while ((readl(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
+	while ((rd_reg32(&jrp->rregs->jrintstatus) & JRINT_ERR_HALT_MASK) ==
 	        JRINT_ERR_HALT_INPROGRESS) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(dev, "job ring %d timed out on flush\n",
@@ -67,10 +40,10 @@ static int caam_reset_hw_jr(struct device_d *dev)
 	}
 
 	/* initiate reset */
-	writel(JRCR_RESET, &jrp->rregs->jrcommand);
+	wr_reg32(&jrp->rregs->jrcommand, JRCR_RESET);
 
 	start = get_time_ns();
-	while (readl(&jrp->rregs->jrcommand) & JRCR_RESET) {
+	while (rd_reg32(&jrp->rregs->jrcommand) & JRCR_RESET) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(dev, "job ring %d timed out on reset\n",
 				jrp->ridx);
@@ -90,7 +63,7 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
 	void *userarg;
 	int found;
 
-	while (readl(&jrp->rregs->outring_used)) {
+	while (rd_reg32(&jrp->rregs->outring_used)) {
 		head = jrp->head;
 
 		sw_idx = tail = jrp->tail;
@@ -102,7 +75,7 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
 			sw_idx = (tail + i) & (JOBR_DEPTH - 1);
 
 			if (jrp->outring[hw_idx].desc ==
-			    jrp->entinfo[sw_idx].desc_addr_dma) {
+			    caam_dma_to_cpu(jrp->entinfo[sw_idx].desc_addr_dma)) {
 				found = 1;
 				break; /* found */
 			}
@@ -120,12 +93,12 @@ static int caam_jr_dequeue(struct caam_drv_private_jr *jrp)
 		usercall = jrp->entinfo[sw_idx].callbk;
 		userarg = jrp->entinfo[sw_idx].cbkarg;
 		userdesc = jrp->entinfo[sw_idx].desc_addr_virt;
-		userstatus = jrp->outring[hw_idx].jrstatus;
+		userstatus = caam32_to_cpu(jrp->outring[hw_idx].jrstatus);
 
 		barrier();
 
 		/* set done */
-		writel(1, &jrp->rregs->outring_rmvd);
+		wr_reg32(&jrp->rregs->outring_rmvd, 1);
 
 		jrp->out_ring_read_index = (jrp->out_ring_read_index + 1) &
 					   (JOBR_DEPTH - 1);
@@ -158,7 +131,7 @@ static int caam_jr_interrupt(struct caam_drv_private_jr *jrp)
 	u32 irqstate;
 
 	start = get_time_ns();
-	while (!(irqstate = readl(&jrp->rregs->jrintstatus))) {
+	while (!(irqstate = rd_reg32(&jrp->rregs->jrintstatus))) {
 		if (is_timeout(start, 100 * MSECOND)) {
 			dev_err(jrp->dev, "timeout waiting for interrupt\n");
 			return -ETIMEDOUT;
@@ -176,7 +149,7 @@ static int caam_jr_interrupt(struct caam_drv_private_jr *jrp)
 	}
 
 	/* Have valid interrupt at this point, just ACK and trigger */
-	writel(irqstate, &jrp->rregs->jrintstatus);
+	wr_reg32(&jrp->rregs->jrintstatus, irqstate);
 
 	return caam_jr_dequeue(jrp);
 }
@@ -218,7 +191,7 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 	struct caam_jrentry_info *head_entry;
 	int head, tail, desc_size;
 
-	desc_size = (*desc & HDR_JD_LENGTH_MASK) * sizeof(u32);
+	desc_size = (caam32_to_cpu(*desc) & HDR_JD_LENGTH_MASK) * sizeof(u32);
 
 	if (!dev->priv)
 		return -ENODEV;
@@ -227,7 +200,7 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 
 	head = jrp->head;
 	tail = jrp->tail;
-	if (!readl(&jrp->rregs->inpring_avail) ||
+	if (!rd_reg32(&jrp->rregs->inpring_avail) ||
 	    CIRC_SPACE(head, tail, JOBR_DEPTH) <= 0) {
 		return -EBUSY;
 	}
@@ -242,7 +215,8 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 	if (!jrp->inpring)
 		return -EIO;
 
-	jrp->inpring[jrp->inp_ring_write_index] = (dma_addr_t)desc;
+	jrp->inpring[jrp->inp_ring_write_index] =
+		cpu_to_caam_dma((dma_addr_t)desc);
 
 	barrier();
 
@@ -251,9 +225,9 @@ int caam_jr_enqueue(struct device_d *dev, u32 *desc,
 	jrp->head = (head + 1) & (JOBR_DEPTH - 1);
 
 	barrier();
-	writel(1, &jrp->rregs->inpring_jobadd);
+	wr_reg32(&jrp->rregs->inpring_jobadd, 1);
 
-	clrbits32(&jrp->rregs->rconfig_lo, JRCFG_IMSK);
+	clrsetbits_32(&jrp->rregs->rconfig_lo, JRCFG_IMSK, 0);
 
 	return caam_jr_interrupt(jrp);
 }
@@ -301,8 +275,8 @@ static int caam_jr_init(struct device_d *dev)
 
 	wr_reg64(&jrp->rregs->inpring_base, dma_inpring);
 	wr_reg64(&jrp->rregs->outring_base, dma_outring);
-	writel(JOBR_DEPTH, &jrp->rregs->inpring_size);
-	writel(JOBR_DEPTH, &jrp->rregs->outring_size);
+	wr_reg32(&jrp->rregs->inpring_size, JOBR_DEPTH);
+	wr_reg32(&jrp->rregs->outring_size, JOBR_DEPTH);
 
 	jrp->ringsize = JOBR_DEPTH;
 
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index b8ca5e396..d50e9ad69 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -10,9 +10,118 @@
 #include <linux/types.h>
 #include <io.h>
 
-/* These are common macros for Power, put here for ARMs */
-#define setbits32(_addr, _v) writel((readl(_addr) | (_v)), (_addr))
-#define clrbits32(_addr, _v) writel((readl(_addr) & ~(_v)), (_addr))
+extern bool caam_little_end;
+
+#define caam_to_cpu(len)				\
+static inline u##len caam##len ## _to_cpu(u##len val)	\
+{							\
+	if (caam_little_end)				\
+		return le##len ## _to_cpu(val);		\
+	else						\
+		return be##len ## _to_cpu(val);		\
+}
+
+#define cpu_to_caam(len)				\
+static inline u##len cpu_to_caam##len(u##len val)	\
+{							\
+	if (caam_little_end)				\
+		return cpu_to_le##len(val);		\
+	else						\
+		return cpu_to_be##len(val);		\
+}
+
+caam_to_cpu(16)
+caam_to_cpu(32)
+caam_to_cpu(64)
+cpu_to_caam(16)
+cpu_to_caam(32)
+cpu_to_caam(64)
+
+static inline void wr_reg32(void __iomem *reg, u32 data)
+{
+	if (caam_little_end)
+		iowrite32(data, reg);
+	else
+		iowrite32be(data, reg);
+}
+
+static inline u32 rd_reg32(void __iomem *reg)
+{
+	if (caam_little_end)
+		return ioread32(reg);
+
+	return ioread32be(reg);
+}
+
+static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
+{
+	if (caam_little_end)
+		iowrite32((ioread32(reg) & ~clear) | set, reg);
+	else
+		iowrite32be((ioread32be(reg) & ~clear) | set, reg);
+}
+
+/*
+ * The DMA address registers in the JR are a pair of 32-bit registers.
+ * The layout is:
+ *
+ *    base + 0x0000 : most-significant 32 bits
+ *    base + 0x0004 : least-significant 32 bits
+ *
+ * The 32-bit version of this core therefore has to write to base + 0x0004
+ * to set the 32-bit wide DMA address. This seems to be independent of the
+ * endianness of the written/read data.
+ */
+
+#ifdef CONFIG_64BIT
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+	if (caam_little_end)
+		iowrite64(data, reg);
+	else
+		iowrite64be(data, reg);
+}
+
+static inline void rd_reg64(void __iomem *reg)
+{
+	if (caam_little_end)
+		ioread64(reg);
+	else
+		ioread64be(reg);
+}
+#else /* CONFIG_64BIT */
+static inline void wr_reg64(void __iomem *reg, u64 data)
+{
+	wr_reg32((u32 __iomem *)(reg), data >> 32);
+	wr_reg32((u32 __iomem *)(reg) + 1, data);
+}
+
+static inline u64 rd_reg64(void __iomem *reg)
+{
+	return ((u64)rd_reg32((u32 __iomem *)(reg)) << 32 |
+		(u64)rd_reg32((u32 __iomem *)(reg) + 1));
+}
+#endif /* CONFIG_64BIT */
+
+static inline u64 cpu_to_caam_dma64(dma_addr_t value)
+{
+	return (((u64)cpu_to_caam32(lower_32_bits(value)) << 32) |
+		 (u64)cpu_to_caam32(upper_32_bits(value)));
+}
+
+static inline u64 caam_dma64_to_cpu(u64 value)
+{
+	return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
+		 (u64)caam32_to_cpu(upper_32_bits(value)));
+}
+
+#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
+#define cpu_to_caam_dma(value) cpu_to_caam_dma64(value)
+#define caam_dma_to_cpu(value) caam_dma64_to_cpu(value)
+#else
+#define cpu_to_caam_dma(value) cpu_to_caam32(value)
+#define caam_dma_to_cpu(value) caam32_to_cpu(value)
+#endif /* CONFIG_ARCH_DMA_ADDR_T_64BIT */
 
 /*
  * jr_outentry
@@ -190,6 +299,8 @@ struct caam_perfmon {
 	u32 faultliodn;	/* FALR - Fault Address LIODN	*/
 	u32 faultdetail;	/* FADR - Fault Addr Detail	*/
 	u32 rsvd3;
+#define CSTA_PLEND		BIT(10)
+#define CSTA_ALT_PLEND		BIT(18)
 	u32 status;		/* CSTA - CAAM Status */
 	u32 smpart;		/* Secure Memory Partition Parameters */
 	u32 smvid;		/* Secure Memory Version ID */
-- 
2.18.0


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[PATCH 05/18] crypto: caam - add support for iMX6UL

[Marcin Niestroj]

Pick commit 4e518816a938187b3bfe1b62fa291d4e38dca06e from Linux
upstream.

    crypto: caam - add support for iMX6UL

    i.MX6UL does only require three clocks to enable CAAM module.

    Signed-off-by: Marcus Folkesson <marcus.folkesson@gmail.com>
    Acked-by: Rob Herring <robh@kernel.org>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 29 +++++++++++++++++------------
 1 file changed, 17 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 0baddf733..55193f6ef 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -224,7 +224,8 @@ static void caam_remove(struct device_d *dev)
 	clk_disable(ctrlpriv->caam_ipg);
 	clk_disable(ctrlpriv->caam_mem);
 	clk_disable(ctrlpriv->caam_aclk);
-	clk_disable(ctrlpriv->caam_emi_slow);
+	if (ctrlpriv->caam_emi_slow)
+		clk_disable(ctrlpriv->caam_emi_slow);
 }
 
 /*
@@ -341,12 +342,14 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
-	if (IS_ERR(ctrlpriv->caam_emi_slow)) {
-		ret = PTR_ERR(ctrlpriv->caam_emi_slow);
-		dev_err(dev,
-			"can't identify CAAM emi slow clk: %d\n", ret);
-		return -ENODEV;
+	if (!of_machine_is_compatible("fsl,imx6ul")) {
+		ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
+		if (IS_ERR(ctrlpriv->caam_emi_slow)) {
+			ret = PTR_ERR(ctrlpriv->caam_emi_slow);
+			dev_err(dev,
+				"can't identify CAAM emi slow clk: %d\n", ret);
+			return -ENODEV;
+		}
 	}
 
 	ret = clk_enable(ctrlpriv->caam_ipg);
@@ -368,11 +371,13 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ret = clk_enable(ctrlpriv->caam_emi_slow);
-	if (ret < 0) {
-		dev_err(dev, "can't enable CAAM emi slow clock: %d\n",
-			ret);
-		return -ENODEV;
+	if (ctrlpriv->caam_emi_slow) {
+		ret = clk_enable(ctrlpriv->caam_emi_slow);
+		if (ret < 0) {
+			dev_err(dev, "can't enable CAAM emi slow clock: %d\n",
+				ret);
+			return -ENODEV;
+		}
 	}
 
 	/* Get configuration properties from device tree */
-- 
2.18.0


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[PATCH 06/18] crypto: caam - fix sparse warnings

[Marcin Niestroj]

Pick commit 8439e94fceb3812989bae41922567123cffd1cf7 from Linux
upstream.

    crypto: caam - fix sparse warnings

    Fix the following sparse warning (note that endianness issues
    are not not addressed in current patch):

    drivers/crypto/caam/ctrl.c:388:24: warning: incorrect type in argument 1 (different address spaces)
    drivers/crypto/caam/ctrl.c:388:24:    expected void [noderef] <asn:2>*reg
    drivers/crypto/caam/ctrl.c:388:24:    got unsigned int *<noident>
    drivers/crypto/caam/ctrl.c:390:24: warning: incorrect type in argument 1 (different address spaces)
    drivers/crypto/caam/ctrl.c:390:24:    expected void [noderef] <asn:2>*reg
    drivers/crypto/caam/ctrl.c:390:24:    got unsigned int *<noident>
    drivers/crypto/caam/ctrl.c:548:24: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:548:24:    expected struct caam_ctrl [noderef] <asn:2>*ctrl
    drivers/crypto/caam/ctrl.c:548:24:    got struct caam_ctrl *<noident>
    drivers/crypto/caam/ctrl.c:550:30: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:549:26: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:549:26:    expected struct caam_assurance [noderef] <asn:2>*assure
    drivers/crypto/caam/ctrl.c:549:26:    got struct caam_assurance *<noident>
    drivers/crypto/caam/ctrl.c:554:28: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:553:24: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:553:24:    expected struct caam_deco [noderef] <asn:2>*deco
    drivers/crypto/caam/ctrl.c:553:24:    got struct caam_deco *<noident>
    drivers/crypto/caam/ctrl.c:634:48: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:633:44: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:633:44:    expected struct caam_job_ring [noderef] <asn:2>*<noident>
    drivers/crypto/caam/ctrl.c:633:44:    got struct caam_job_ring *<noident>
    drivers/crypto/caam/ctrl.c:648:34: warning: cast removes address space of expression
    drivers/crypto/caam/ctrl.c:647:30: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:647:30:    expected struct caam_queue_if [noderef] <asn:2>*qi
    drivers/crypto/caam/ctrl.c:647:30:    got struct caam_queue_if *<noident>
    drivers/crypto/caam/ctrl.c:806:37: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:806:37:    expected void *data
    drivers/crypto/caam/ctrl.c:806:37:    got unsigned int [noderef] <asn:2>*
    drivers/crypto/caam/ctrl.c:814:38: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:814:38:    expected void *data
    drivers/crypto/caam/ctrl.c:814:38:    got unsigned int [noderef] <asn:2>*
    drivers/crypto/caam/ctrl.c:822:38: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/ctrl.c:822:38:    expected void *data
    drivers/crypto/caam/ctrl.c:822:38:    got unsigned int [noderef] <asn:2>*
    drivers/crypto/caam/jr.c:492:23: warning: incorrect type in assignment (different address spaces)
    drivers/crypto/caam/jr.c:492:23:    expected struct caam_job_ring [noderef] <asn:2>*rregs
    drivers/crypto/caam/jr.c:492:23:    got struct caam_job_ring *<noident>
    drivers/crypto/caam/caampkc.c:398:35: warning: Using plain integer as NULL pointer
    drivers/crypto/caam/caampkc.c:444:35: warning: Using plain integer as NULL pointer

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 34 ++++++++++++++--------------------
 drivers/crypto/caam/jr.c   |  2 +-
 2 files changed, 15 insertions(+), 21 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 55193f6ef..0f9ad328e 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -257,11 +257,8 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	 */
 	val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
 	      >> RTSDCTL_ENT_DLY_SHIFT;
-	if (ent_delay <= val) {
-		/* put RNG4 into run mode */
-		clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, 0);
-		return;
-	}
+	if (ent_delay <= val)
+		goto start_rng;
 
 	val = rd_reg32(&r4tst->rtsdctl);
 	val = (val & ~RTSDCTL_ENT_DLY_MASK) |
@@ -273,15 +270,12 @@ static void kick_trng(struct device_d *ctrldev, int ent_delay)
 	wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
 	/* read the control register */
 	val = rd_reg32(&r4tst->rtmctl);
+start_rng:
 	/*
 	 * select raw sampling in both entropy shifter
-	 * and statistical checker
+	 * and statistical checker; ; put RNG4 into run mode
 	 */
-	clrsetbits_32(&val, 0, RTMCTL_SAMP_MODE_RAW_ES_SC);
-	/* put RNG4 into run mode */
-	clrsetbits_32(&val, RTMCTL_PRGM, 0);
-	/* write back the control register */
-	wr_reg32(&r4tst->rtmctl, val);
+	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 }
 
 /**
@@ -403,12 +397,12 @@ static int caam_probe(struct device_d *dev)
 	else
 		BLOCK_OFFSET = PG_SIZE_64K;
 
-	ctrlpriv->ctrl = (struct caam_ctrl __force *)ctrl;
-	ctrlpriv->assure = (struct caam_assurance __force *)
-			   ((uint8_t *)ctrl +
+	ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
+	ctrlpriv->assure = (struct caam_assurance __iomem __force *)
+			   ((__force uint8_t *)ctrl +
 			    BLOCK_OFFSET * ASSURE_BLOCK_NUMBER);
-	ctrlpriv->deco = (struct caam_deco __force *)
-			 ((uint8_t *)ctrl +
+	ctrlpriv->deco = (struct caam_deco __iomem __force *)
+			 ((__force uint8_t *)ctrl +
 			  BLOCK_OFFSET * DECO_BLOCK_NUMBER);
 
 	/*
@@ -489,8 +483,8 @@ static int caam_probe(struct device_d *dev)
 			}
 
 			ctrlpriv->jrpdev[ring] = jrdev;
-			ctrlpriv->jr[ring] = (struct caam_job_ring __force *)
-					     ((uint8_t *)ctrl +
+			ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
+					     ((__force uint8_t *)ctrl +
 					     (ring + JR_BLOCK_NUMBER) *
 					      BLOCK_OFFSET);
 			ctrlpriv->total_jobrs++;
@@ -501,8 +495,8 @@ static int caam_probe(struct device_d *dev)
 	/* Check to see if QI present. If so, enable */
 	ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
 	if (ctrlpriv->qi_present) {
-		ctrlpriv->qi = (struct caam_queue_if __force *)
-			       ((uint8_t *)ctrl +
+		ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
+			       ((__force uint8_t *)ctrl +
 				 BLOCK_OFFSET * QI_BLOCK_NUMBER);
 		/* This is all that's required to physically enable QI */
 		wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
diff --git a/drivers/crypto/caam/jr.c b/drivers/crypto/caam/jr.c
index 84396e41e..b602a7b0e 100644
--- a/drivers/crypto/caam/jr.c
+++ b/drivers/crypto/caam/jr.c
@@ -309,7 +309,7 @@ int caam_jr_probe(struct device_d *dev)
 	if (IS_ERR(ctrl))
 		return PTR_ERR(ctrl);
 
-	jrpriv->rregs = (struct caam_job_ring __force *)ctrl;
+	jrpriv->rregs = (struct caam_job_ring __iomem __force *)ctrl;
 
 	/* Now do the platform independent part */
 	error = caam_jr_init(dev); /* now turn on hardware */
-- 
2.18.0


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[PATCH 07/18] crypto: caam - trivial code clean-up

[Marcin Niestroj]

Pick commit 4ca7c7d8fea1ffdc36df33578c1e68d0d6367b0c from Linux
upstream.

    crypto: caam - trivial code clean-up

    -replace offsetof with container_of
    -remove unused "assoc_nents", "iv_dma" from aead_edesc
    and fix comments
    -remove unused CAAM_MAX_IV_LENGTH #define

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/caamrng.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index 51c267e3d..b62e3eb77 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -81,8 +81,7 @@ static void rng_done(struct device_d *jrdev, u32 *desc, u32 err, void *context)
 {
 	struct buf_data *bd;
 
-	bd = (struct buf_data *)((char *)desc -
-	      offsetof(struct buf_data, hw_desc));
+	bd = container_of(desc, struct buf_data, hw_desc[0]);
 
 	if (err)
 		caam_jr_strstatus(jrdev, err);
-- 
2.18.0


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[PATCH 08/18] crypto: caam - remove unreachable code in report_ccb_status()

[Marcin Niestroj]

Pick commit 9305dff7ab8b5e1aef2c4c5c733ce7e1dc345433 from Linux
upstream.

    crypto: caam - remove unreachable code in report_ccb_status()

    ERRID is a 4-bit field.
    Since err_id values are in [0..15] and err_id_list array size is 16,
    the condition "err_id < ARRAY_SIZE(err_id_list)" is always true.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/error.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/crypto/caam/error.c b/drivers/crypto/caam/error.c
index 9c875375d..766875b58 100644
--- a/drivers/crypto/caam/error.c
+++ b/drivers/crypto/caam/error.c
@@ -150,10 +150,9 @@ static void report_ccb_status(struct device_d *jrdev, const u32 status,
 	    strlen(rng_err_id_list[err_id])) {
 		/* RNG-only error */
 		err_str = rng_err_id_list[err_id];
-	} else if (err_id < ARRAY_SIZE(err_id_list))
+	} else {
 		err_str = err_id_list[err_id];
-	else
-		snprintf(err_err_code, sizeof(err_err_code), "%02x", err_id);
+	}
 
 	/*
 	 * CCB ICV check failures are part of normal operation life;
-- 
2.18.0


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[PATCH 09/18] crypto: caam - constify pointer to descriptor buffer

[Marcin Niestroj]

Pick commit 24a4f14f0a93f6fff7e6ade5d99b402c831bbd96 from Linux
upstream.

    crypto: caam - constify pointer to descriptor buffer

    The pointer to the descriptor buffer is not touched,
    it always points to start of the descriptor buffer.
    Thus, make it const.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 69 ++++++++++++++++---------------
 1 file changed, 36 insertions(+), 33 deletions(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index cf86cc83b..305069e74 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -31,38 +31,39 @@
 			       LDST_SRCDST_WORD_DECOCTRL | \
 			       (LDOFF_ENABLE_AUTO_NFIFO << LDST_OFFSET_SHIFT))
 
-static inline int desc_len(u32 *desc)
+static inline int desc_len(u32 * const desc)
 {
 	return caam32_to_cpu(*desc) & HDR_DESCLEN_MASK;
 }
 
-static inline int desc_bytes(void *desc)
+static inline int desc_bytes(void * const desc)
 {
 	return desc_len(desc) * CAAM_CMD_SZ;
 }
 
-static inline u32 *desc_end(u32 *desc)
+static inline u32 *desc_end(u32 * const desc)
 {
 	return desc + desc_len(desc);
 }
 
-static inline void *sh_desc_pdb(u32 *desc)
+static inline void *sh_desc_pdb(u32 * const desc)
 {
 	return desc + 1;
 }
 
-static inline void init_desc(u32 *desc, u32 options)
+static inline void init_desc(u32 * const desc, u32 options)
 {
 	*desc = cpu_to_caam32((options | HDR_ONE) + 1);
 }
 
-static inline void init_sh_desc(u32 *desc, u32 options)
+static inline void init_sh_desc(u32 * const desc, u32 options)
 {
 	PRINT_POS;
 	init_desc(desc, CMD_SHARED_DESC_HDR | options);
 }
 
-static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
+static inline void init_sh_desc_pdb(u32 * const desc, u32 options,
+				size_t pdb_bytes)
 {
 	u32 pdb_len = (pdb_bytes + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ;
 
@@ -70,12 +71,12 @@ static inline void init_sh_desc_pdb(u32 *desc, u32 options, size_t pdb_bytes)
 		     options);
 }
 
-static inline void init_job_desc(u32 *desc, u32 options)
+static inline void init_job_desc(u32 * const desc, u32 options)
 {
 	init_desc(desc, CMD_DESC_HDR | options);
 }
 
-static inline void append_ptr(u32 *desc, dma_addr_t ptr)
+static inline void append_ptr(u32 * const desc, dma_addr_t ptr)
 {
 	dma_addr_t *offset = (dma_addr_t *)desc_end(desc);
 
@@ -85,8 +86,8 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
 				CAAM_PTR_SZ / CAAM_CMD_SZ);
 }
 
-static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
-					u32 options)
+static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
+					int len, u32 options)
 {
 	PRINT_POS;
 	init_job_desc(desc, HDR_SHARED | options |
@@ -94,7 +95,7 @@ static inline void init_job_desc_shared(u32 *desc, dma_addr_t ptr, int len,
 	append_ptr(desc, ptr);
 }
 
-static inline void append_data(u32 *desc, void *data, int len)
+static inline void append_data(u32 * const desc, void *data, int len)
 {
 	u32 *offset = desc_end(desc);
 
@@ -105,7 +106,7 @@ static inline void append_data(u32 *desc, void *data, int len)
 				(len + CAAM_CMD_SZ - 1) / CAAM_CMD_SZ);
 }
 
-static inline void append_cmd(u32 *desc, u32 command)
+static inline void append_cmd(u32 * const desc, u32 command)
 {
 	u32 *cmd = desc_end(desc);
 
@@ -116,7 +117,7 @@ static inline void append_cmd(u32 *desc, u32 command)
 
 #define append_u32 append_cmd
 
-static inline void append_u64(u32 *desc, u64 data)
+static inline void append_u64(u32 * const desc, u64 data)
 {
 	u32 *offset = desc_end(desc);
 
@@ -133,14 +134,14 @@ static inline void append_u64(u32 *desc, u64 data)
 }
 
 /* Write command without affecting header, and return pointer to next word */
-static inline u32 *write_cmd(u32 *desc, u32 command)
+static inline u32 *write_cmd(u32 * const desc, u32 command)
 {
 	*desc = cpu_to_caam32(command);
 
 	return desc + 1;
 }
 
-static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
+static inline void append_cmd_ptr(u32 * const desc, dma_addr_t ptr, int len,
 				  u32 command)
 {
 	append_cmd(desc, command | len);
@@ -148,7 +149,7 @@ static inline void append_cmd_ptr(u32 *desc, dma_addr_t ptr, int len,
 }
 
 /* Write length after pointer, rather than inside command */
-static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
+static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
 					 unsigned int len, u32 command)
 {
 	append_cmd(desc, command);
@@ -157,7 +158,7 @@ static inline void append_cmd_ptr_extlen(u32 *desc, dma_addr_t ptr,
 	append_cmd(desc, len);
 }
 
-static inline void append_cmd_data(u32 *desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, void *data, int len,
 				   u32 command)
 {
 	append_cmd(desc, command | IMMEDIATE | len);
@@ -165,7 +166,7 @@ static inline void append_cmd_data(u32 *desc, void *data, int len,
 }
 
 #define APPEND_CMD_RET(cmd, op) \
-static inline u32 *append_##cmd(u32 *desc, u32 options) \
+static inline u32 *append_##cmd(u32 * const desc, u32 options) \
 { \
 	u32 *cmd = desc_end(desc); \
 	PRINT_POS; \
@@ -175,13 +176,13 @@ static inline u32 *append_##cmd(u32 *desc, u32 options) \
 APPEND_CMD_RET(jump, JUMP)
 APPEND_CMD_RET(move, MOVE)
 
-static inline void set_jump_tgt_here(u32 *desc, u32 *jump_cmd)
+static inline void set_jump_tgt_here(u32 * const desc, u32 *jump_cmd)
 {
 	*jump_cmd = cpu_to_caam32(caam32_to_cpu(*jump_cmd) |
 				(desc_len(desc) - (jump_cmd - desc)));
 }
 
-static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
+static inline void set_move_tgt_here(u32 * const desc, u32 *move_cmd)
 {
 	u32 val = caam32_to_cpu(*move_cmd);
 
@@ -191,7 +192,7 @@ static inline void set_move_tgt_here(u32 *desc, u32 *move_cmd)
 }
 
 #define APPEND_CMD(cmd, op) \
-static inline void append_##cmd(u32 *desc, u32 options) \
+static inline void append_##cmd(u32 * const desc, u32 options) \
 { \
 	PRINT_POS; \
 	append_cmd(desc, CMD_##op | options); \
@@ -199,7 +200,8 @@ static inline void append_##cmd(u32 *desc, u32 options) \
 APPEND_CMD(operation, OPERATION)
 
 #define APPEND_CMD_LEN(cmd, op) \
-static inline void append_##cmd(u32 *desc, unsigned int len, u32 options) \
+static inline void append_##cmd(u32 * const desc, unsigned int len, \
+				u32 options) \
 { \
 	PRINT_POS; \
 	append_cmd(desc, CMD_##op | len | options); \
@@ -211,8 +213,8 @@ APPEND_CMD_LEN(seq_fifo_load, SEQ_FIFO_LOAD)
 APPEND_CMD_LEN(seq_fifo_store, SEQ_FIFO_STORE)
 
 #define APPEND_CMD_PTR(cmd, op) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, unsigned int len, \
-				u32 options) \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
+				unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
 	append_cmd_ptr(desc, ptr, len, CMD_##op | options); \
@@ -222,8 +224,8 @@ APPEND_CMD_PTR(load, LOAD)
 APPEND_CMD_PTR(fifo_load, FIFO_LOAD)
 APPEND_CMD_PTR(fifo_store, FIFO_STORE)
 
-static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
-				u32 options)
+static inline void append_store(u32 * const desc, dma_addr_t ptr,
+				unsigned int len, u32 options)
 {
 	u32 cmd_src;
 
@@ -240,7 +242,8 @@ static inline void append_store(u32 *desc, dma_addr_t ptr, unsigned int len,
 }
 
 #define APPEND_SEQ_PTR_INTLEN(cmd, op) \
-static inline void append_seq_##cmd##_ptr_intlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_seq_##cmd##_ptr_intlen(u32 * const desc, \
+						 dma_addr_t ptr, \
 						 unsigned int len, \
 						 u32 options) \
 { \
@@ -254,7 +257,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
 APPEND_SEQ_PTR_INTLEN(out, OUT)
 
 #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -264,7 +267,7 @@ APPEND_CMD_PTR_TO_IMM(load, LOAD);
 APPEND_CMD_PTR_TO_IMM(fifo_load, FIFO_LOAD);
 
 #define APPEND_CMD_PTR_EXTLEN(cmd, op) \
-static inline void append_##cmd##_extlen(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd##_extlen(u32 * const desc, dma_addr_t ptr, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -278,7 +281,7 @@ APPEND_CMD_PTR_EXTLEN(seq_out_ptr, SEQ_OUT_PTR)
  * the size of its type
  */
 #define APPEND_CMD_PTR_LEN(cmd, op, type) \
-static inline void append_##cmd(u32 *desc, dma_addr_t ptr, \
+static inline void append_##cmd(u32 * const desc, dma_addr_t ptr, \
 				type len, u32 options) \
 { \
 	PRINT_POS; \
@@ -295,7 +298,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
  * from length of immediate data provided, e.g., split keys
  */
 #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
 					 unsigned int data_len, \
 					 unsigned int len, u32 options) \
 { \
@@ -306,7 +309,7 @@ static inline void append_##cmd##_as_imm(u32 *desc, void *data, \
 APPEND_CMD_PTR_TO_IMM2(key, KEY);
 
 #define APPEND_CMD_RAW_IMM(cmd, op, type) \
-static inline void append_##cmd##_imm_##type(u32 *desc, type immediate, \
+static inline void append_##cmd##_imm_##type(u32 * const desc, type immediate, \
 					     u32 options) \
 { \
 	PRINT_POS; \
-- 
2.18.0


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[PATCH 10/18] crypto: caam - avoid double inclusion in desc_constr.h

[Marcin Niestroj]

Pick commit cd373691d262afea523f4ae6ebf3dee3a204c8a7 from Linux
upstream.

    crypto: caam - avoid double inclusion in desc_constr.h

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 305069e74..3e2ee785b 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -4,6 +4,9 @@
  * Copyright 2008-2012 Freescale Semiconductor, Inc.
  */
 
+#ifndef DESC_CONSTR_H
+#define DESC_CONSTR_H
+
 #include "desc.h"
 #include "regs.h"
 
@@ -403,3 +406,5 @@ do { \
 	APPEND_MATH_IMM_u64(LSHIFT, desc, dest, src0, src1, data)
 #define append_math_rshift_imm_u64(desc, dest, src0, src1, data) \
 	APPEND_MATH_IMM_u64(RSHIFT, desc, dest, src0, src1, data)
+
+#endif /* DESC_CONSTR_H */
-- 
2.18.0


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[PATCH 11/18] crypto: caam - clean-up in caam_init_rng()

[Marcin Niestroj]

Pick commit f366af462aef1dcaeab0f68b031e5c4c4eb860e1 from Linux
upstream.

    crypto: caam - clean-up in caam_init_rng()

    Clean up the code, as indicated by Coccinelle.

    Cc: Julia Lawall <julia.lawall@lip6.fr>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/caamrng.c | 6 +-----
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/drivers/crypto/caam/caamrng.c b/drivers/crypto/caam/caamrng.c
index b62e3eb77..39a90568d 100644
--- a/drivers/crypto/caam/caamrng.c
+++ b/drivers/crypto/caam/caamrng.c
@@ -242,11 +242,7 @@ static int caam_init_rng(struct caam_rng_ctx *ctx, struct device_d *jrdev)
 	if (err)
 		return err;
 
-	err = caam_init_buf(ctx, 1);
-	if (err)
-		return err;
-
-	return 0;
+	return caam_init_buf(ctx, 1);
 }
 
 int caam_rng_probe(struct device_d *dev, struct device_d *jrdev)
-- 
2.18.0


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[PATCH 12/18] crypto: caam - fix incorrect define

[Marcin Niestroj]

Pick commit cc2f8ab5334a736fa0e775cfccf06c1e268667f0 from Linux
upstream.

    crypto: caam - fix incorrect define

    Fixes: 3ebfa92f49a6 ("crypto: caam - Add new macros for building extended SEC descriptors (> 64 words)")
    Signed-off-by: Radu Alexe <radu.alexe@nxp.com>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index e964a5a93..2b5f49967 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -1468,7 +1468,7 @@ struct sec4_sg_entry {
 #define MATH_SRC1_REG2		(0x02 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_REG3		(0x03 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_IMM		(0x04 << MATH_SRC1_SHIFT)
-#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC0_SHIFT)
+#define MATH_SRC1_DPOVRD	(0x07 << MATH_SRC1_SHIFT)
 #define MATH_SRC1_INFIFO	(0x0a << MATH_SRC1_SHIFT)
 #define MATH_SRC1_OUTFIFO	(0x0b << MATH_SRC1_SHIFT)
 #define MATH_SRC1_ONE		(0x0c << MATH_SRC1_SHIFT)
-- 
2.18.0


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[PATCH 13/18] crypto: caam - constify key data

[Marcin Niestroj]

Pick commit 6674a4fdc6c2e690b28b7f590cd20871aeee55ad from Linux
upstream.

    crypto: caam - constify key data

    Key data is not modified, it is copied in the shared descriptor.

    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc_constr.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/caam/desc_constr.h b/drivers/crypto/caam/desc_constr.h
index 3e2ee785b..0d5778ba0 100644
--- a/drivers/crypto/caam/desc_constr.h
+++ b/drivers/crypto/caam/desc_constr.h
@@ -98,7 +98,7 @@ static inline void init_job_desc_shared(u32 * const desc, dma_addr_t ptr,
 	append_ptr(desc, ptr);
 }
 
-static inline void append_data(u32 * const desc, void *data, int len)
+static inline void append_data(u32 * const desc, const void *data, int len)
 {
 	u32 *offset = desc_end(desc);
 
@@ -161,7 +161,7 @@ static inline void append_cmd_ptr_extlen(u32 * const desc, dma_addr_t ptr,
 	append_cmd(desc, len);
 }
 
-static inline void append_cmd_data(u32 * const desc, void *data, int len,
+static inline void append_cmd_data(u32 * const desc, const void *data, int len,
 				   u32 command)
 {
 	append_cmd(desc, command | IMMEDIATE | len);
@@ -260,7 +260,7 @@ APPEND_SEQ_PTR_INTLEN(in, IN)
 APPEND_SEQ_PTR_INTLEN(out, OUT)
 
 #define APPEND_CMD_PTR_TO_IMM(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
 					 unsigned int len, u32 options) \
 { \
 	PRINT_POS; \
@@ -301,7 +301,7 @@ APPEND_CMD_PTR_LEN(seq_out_ptr, SEQ_OUT_PTR, u32)
  * from length of immediate data provided, e.g., split keys
  */
 #define APPEND_CMD_PTR_TO_IMM2(cmd, op) \
-static inline void append_##cmd##_as_imm(u32 * const desc, void *data, \
+static inline void append_##cmd##_as_imm(u32 * const desc, const void *data, \
 					 unsigned int data_len, \
 					 unsigned int len, u32 options) \
 { \
-- 
2.18.0


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[PATCH 14/18] crypto: caam - fix endless loop when DECO acquire fails

[Marcin Niestroj]

Pick commit 225ece3e7dad4cfc44cca38ce7a3a80f255ea8f1 from Linux
upstream.

    crypto: caam - fix endless loop when DECO acquire fails

    In case DECO0 cannot be acquired - i.e. run_descriptor_deco0() fails
    with -ENODEV, caam_probe() enters an endless loop:

    run_descriptor_deco0
            ret -ENODEV
            -> instantiate_rng
                    -ENODEV, overwritten by -EAGAIN
                    ret -EAGAIN
                    -> caam_probe
                            -EAGAIN results in endless loop

    It turns out the error path in instantiate_rng() is incorrect,
    the checks are done in the wrong order.

    Cc: <stable@vger.kernel.org> # 3.13+
    Fixes: 1005bccd7a4a6 ("crypto: caam - enable instantiation of all RNG4 state handles")
    Reported-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
    Suggested-by: Auer Lukas <lukas.auer@aisec.fraunhofer.de>
    Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 0f9ad328e..681200594 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -202,12 +202,15 @@ static int instantiate_rng(struct device_d *ctrldev, int state_handle_mask,
 		 * without any error (HW optimizations for later
 		 * CAAM eras), then try again.
 		 */
+		if (ret)
+			break;
+
 		rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK;
 		if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
-		    !(rdsta_val & (1 << sh_idx)))
+		    !(rdsta_val & (1 << sh_idx))) {
 			ret = -EAGAIN;
-		if (ret)
 			break;
+		}
 		dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
 		/* Clear the contents before recreating the descriptor */
 		memset(desc, 0x00, CAAM_CMD_SZ * 7);
-- 
2.18.0


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[PATCH 15/18] crypto: caam - do not use mem and emi_slow clock for imx7x

[Marcin Niestroj]

Pick commit 699e491bac84a2069c7abeacf2f4367ecb19fa9c from Linux
upstream.

    crypto: caam - do not use mem and emi_slow clock for imx7x

    I.MX7x only use two clocks for the CAAM module, so make sure we do not try to
    use the mem and the emi_slow clock when running in that imx7d and imx7s machine
    type.

    Cc: "Horia Geantă" <horia.geanta@nxp.com>
    Cc: Aymen Sghaier <aymen.sghaier@nxp.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Peng Fan <peng.fan@nxp.com>
    Cc: "David S. Miller" <davem@davemloft.net>
    Cc: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
    Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 33 +++++++++++++++++++++------------
 1 file changed, 21 insertions(+), 12 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 681200594..24c98df5a 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -225,7 +225,8 @@ static void caam_remove(struct device_d *dev)
 
 	/* shut clocks off before finalizing shutdown */
 	clk_disable(ctrlpriv->caam_ipg);
-	clk_disable(ctrlpriv->caam_mem);
+	if (ctrlpriv->caam_mem)
+		clk_disable(ctrlpriv->caam_mem);
 	clk_disable(ctrlpriv->caam_aclk);
 	if (ctrlpriv->caam_emi_slow)
 		clk_disable(ctrlpriv->caam_emi_slow);
@@ -324,11 +325,15 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ctrlpriv->caam_mem = clk_get(dev, "mem");
-	if (IS_ERR(ctrlpriv->caam_mem)) {
-		ret = PTR_ERR(ctrlpriv->caam_mem);
-		dev_err(dev, "can't identify CAAM secure mem clk: %d\n", ret);
-		return -ENODEV;
+	if (!of_machine_is_compatible("fsl,imx7d") &&
+	    !of_machine_is_compatible("fsl,imx7s")) {
+		ctrlpriv->caam_mem = clk_get(dev, "mem");
+		if (IS_ERR(ctrlpriv->caam_mem)) {
+			ret = PTR_ERR(ctrlpriv->caam_mem);
+			dev_err(dev,
+				"can't identify CAAM mem clk: %d\n", ret);
+			return -ENODEV;
+		}
 	}
 
 	ctrlpriv->caam_aclk = clk_get(dev, "aclk");
@@ -339,7 +344,9 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	if (!of_machine_is_compatible("fsl,imx6ul")) {
+	if (!of_machine_is_compatible("fsl,imx6ul") &&
+	    !of_machine_is_compatible("fsl,imx7d") &&
+	    !of_machine_is_compatible("fsl,imx7s")) {
 		ctrlpriv->caam_emi_slow = clk_get(dev, "emi_slow");
 		if (IS_ERR(ctrlpriv->caam_emi_slow)) {
 			ret = PTR_ERR(ctrlpriv->caam_emi_slow);
@@ -355,11 +362,13 @@ static int caam_probe(struct device_d *dev)
 		return -ENODEV;
 	}
 
-	ret = clk_enable(ctrlpriv->caam_mem);
-	if (ret < 0) {
-		dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
-			ret);
-		return -ENODEV;
+	if (ctrlpriv->caam_mem) {
+		ret = clk_enable(ctrlpriv->caam_mem);
+		if (ret < 0) {
+			dev_err(dev, "can't enable CAAM secure mem clock: %d\n",
+				ret);
+			return -ENODEV;
+		}
 	}
 
 	ret = clk_enable(ctrlpriv->caam_aclk);
-- 
2.18.0


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[PATCH 16/18] crypto: caam - sync desc.h with Linux

[Marcin Niestroj]

Get rid of all differences between our and Linux content of desc.h, so
we prevent running into issues when porting new features in future.

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/desc.h | 32 +++++++++-----------------------
 1 file changed, 9 insertions(+), 23 deletions(-)

diff --git a/drivers/crypto/caam/desc.h b/drivers/crypto/caam/desc.h
index 2b5f49967..ee873c07f 100644
--- a/drivers/crypto/caam/desc.h
+++ b/drivers/crypto/caam/desc.h
@@ -20,18 +20,7 @@
 #define SEC4_SG_BPID_MASK	0x000000ff
 #define SEC4_SG_BPID_SHIFT	16
 #define SEC4_SG_LEN_MASK	0x3fffffff	/* Excludes EXT and FINAL */
-#define SEC4_SG_OFFS_MASK	0x00001fff
-
-struct sec4_sg_entry {
-#ifdef CONFIG_64BIT
-	u64 ptr;
-#else
-	u32 reserved;
-	u32 ptr;
-#endif
-	u32 len;
-	u32 bpid_offset;
-};
+#define SEC4_SG_OFFSET_MASK	0x00001fff
 
 /* Max size of any CAAM descriptor in 32-bit words, inclusive of header */
 #define MAX_CAAM_DESCSIZE	64
@@ -95,8 +84,8 @@ struct sec4_sg_entry {
 #define HDR_ZRO			0x00008000
 
 /* Start Index or SharedDesc Length */
-#define HDR_START_IDX_MASK	0x3f
 #define HDR_START_IDX_SHIFT	16
+#define HDR_START_IDX_MASK	(0x3f << HDR_START_IDX_SHIFT)
 
 /* If shared descriptor header, 6-bit length */
 #define HDR_DESCLEN_SHR_MASK	0x3f
@@ -126,10 +115,10 @@ struct sec4_sg_entry {
 #define HDR_PROP_DNR		0x00000800
 
 /* JobDesc/SharedDesc share property */
-#define HDR_SD_SHARE_MASK	0x03
 #define HDR_SD_SHARE_SHIFT	8
-#define HDR_JD_SHARE_MASK	0x07
+#define HDR_SD_SHARE_MASK	(0x03 << HDR_SD_SHARE_SHIFT)
 #define HDR_JD_SHARE_SHIFT	8
+#define HDR_JD_SHARE_MASK	(0x07 << HDR_JD_SHARE_SHIFT)
 
 #define HDR_SHARE_NEVER		(0x00 << HDR_SD_SHARE_SHIFT)
 #define HDR_SHARE_WAIT		(0x01 << HDR_SD_SHARE_SHIFT)
@@ -240,7 +229,7 @@ struct sec4_sg_entry {
 #define LDST_SRCDST_WORD_DECO_MATH2	(0x0a << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_DECO_AAD_SZ	(0x0b << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_DECO_MATH3	(0x0b << LDST_SRCDST_SHIFT)
-#define LDST_SRCDST_WORD_CLASS1_ICV_SZ	(0x0c << LDST_SRCDST_SHIFT)
+#define LDST_SRCDST_WORD_CLASS1_IV_SZ	(0x0c << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_ALTDS_CLASS1	(0x0f << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_PKHA_A_SZ	(0x10 << LDST_SRCDST_SHIFT)
 #define LDST_SRCDST_WORD_PKHA_B_SZ	(0x11 << LDST_SRCDST_SHIFT)
@@ -405,10 +394,7 @@ struct sec4_sg_entry {
 #define FIFOST_TYPE_PKHA_N	 (0x08 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_A	 (0x0c << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_B	 (0x0d << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_JKEK	(0x10 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_AF_SBOX_CCM_TKEK	(0x11 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_JKEK	(0x14 << FIFOST_TYPE_SHIFT)
-#define FIFOST_TYPE_KEY_CCM_TKEK	(0x15 << FIFOST_TYPE_SHIFT)
+#define FIFOST_TYPE_AF_SBOX_JKEK (0x20 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_AF_SBOX_TKEK (0x21 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_E_JKEK	 (0x22 << FIFOST_TYPE_SHIFT)
 #define FIFOST_TYPE_PKHA_E_TKEK	 (0x23 << FIFOST_TYPE_SHIFT)
@@ -1130,8 +1116,8 @@ struct sec4_sg_entry {
 /* For non-protocol/alg-only op commands */
 #define OP_ALG_TYPE_SHIFT	24
 #define OP_ALG_TYPE_MASK	(0x7 << OP_ALG_TYPE_SHIFT)
-#define OP_ALG_TYPE_CLASS1	2
-#define OP_ALG_TYPE_CLASS2	4
+#define OP_ALG_TYPE_CLASS1	(2 << OP_ALG_TYPE_SHIFT)
+#define OP_ALG_TYPE_CLASS2	(4 << OP_ALG_TYPE_SHIFT)
 
 #define OP_ALG_ALGSEL_SHIFT	16
 #define OP_ALG_ALGSEL_MASK	(0xff << OP_ALG_ALGSEL_SHIFT)
@@ -1272,7 +1258,7 @@ struct sec4_sg_entry {
 #define OP_ALG_PKMODE_MOD_PRIMALITY	0x00f
 
 /* PKHA mode copy-memory functions */
-#define OP_ALG_PKMODE_SRC_REG_SHIFT	13
+#define OP_ALG_PKMODE_SRC_REG_SHIFT	17
 #define OP_ALG_PKMODE_SRC_REG_MASK	(7 << OP_ALG_PKMODE_SRC_REG_SHIFT)
 #define OP_ALG_PKMODE_DST_REG_SHIFT	10
 #define OP_ALG_PKMODE_DST_REG_MASK	(7 << OP_ALG_PKMODE_DST_REG_SHIFT)
-- 
2.18.0


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[PATCH 17/18] crypto: caam - staticize caam_get_era()

[Marcin Niestroj]

Pick commit b0039c00fbbbc3cb9c4b25852d81a2b4c193371d from Linux
upstream.

    crypto: caam - staticize caam_get_era()

    caam_get_era() is only used locally, so do not export this function
    and make it static instead.

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 3 +--
 drivers/crypto/caam/ctrl.h | 1 -
 2 files changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 24c98df5a..3b24c5ea2 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -286,7 +286,7 @@ start_rng:
  * caam_get_era() - Return the ERA of the SEC on SoC, based
  * on "sec-era" propery in the DTS. This property is updated by u-boot.
  **/
-int caam_get_era(void)
+static int caam_get_era(void)
 {
 	struct device_node *caam_node;
 	int ret;
@@ -297,7 +297,6 @@ int caam_get_era(void)
 
 	return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
 }
-EXPORT_SYMBOL(caam_get_era);
 
 /* Probe routine for CAAM top (controller) level */
 static int caam_probe(struct device_d *dev)
diff --git a/drivers/crypto/caam/ctrl.h b/drivers/crypto/caam/ctrl.h
index cac5402a4..22b6ad5a7 100644
--- a/drivers/crypto/caam/ctrl.h
+++ b/drivers/crypto/caam/ctrl.h
@@ -8,6 +8,5 @@
 #define CTRL_H
 
 /* Prototypes for backend-level services exposed to APIs */
-int caam_get_era(void);
 
 #endif /* CTRL_H */
-- 
2.18.0


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[PATCH 18/18] crypto: caam - allow retrieving 'era' from register

[Marcin Niestroj]

Pick commit 654f2b937b389295581bcb4aa26011a63db7bc8f from Linux
upstream.

    crypto: caam - allow retrieving 'era' from register

    The 'era' information can be retrieved from CAAM registers, so
    introduce a caam_get_era_from_hw() function that gets it via register
    reads in case the 'fsl,sec-era' property is not passed in the device
    tree.

    This function is based on the U-Boot implementation from
    drivers/crypto/fsl/sec.c

    Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
    Reviewed-by: Horia Geantă <horia.geanta@nxp.com>
    Tested-by: Breno Lima <breno.lima@nxp.com>
    Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>

Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
---
 drivers/crypto/caam/ctrl.c | 56 +++++++++++++++++++++++++++++++++++---
 drivers/crypto/caam/regs.h |  6 ++++
 2 files changed, 58 insertions(+), 4 deletions(-)

diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
index 3b24c5ea2..9e62bd6fd 100644
--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -282,11 +282,56 @@ start_rng:
 	clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC);
 }
 
+static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
+{
+	static const struct {
+		u16 ip_id;
+		u8 maj_rev;
+		u8 era;
+	} id[] = {
+		{0x0A10, 1, 1},
+		{0x0A10, 2, 2},
+		{0x0A12, 1, 3},
+		{0x0A14, 1, 3},
+		{0x0A14, 2, 4},
+		{0x0A16, 1, 4},
+		{0x0A10, 3, 4},
+		{0x0A11, 1, 4},
+		{0x0A18, 1, 4},
+		{0x0A11, 2, 5},
+		{0x0A12, 2, 5},
+		{0x0A13, 1, 5},
+		{0x0A1C, 1, 5}
+	};
+	u32 ccbvid, id_ms;
+	u8 maj_rev, era;
+	u16 ip_id;
+	int i;
+
+	ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
+	era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
+	if (era)	/* This is '0' prior to CAAM ERA-6 */
+		return era;
+
+	id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
+	ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
+	maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
+
+	for (i = 0; i < ARRAY_SIZE(id); i++)
+		if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
+			return id[i].era;
+
+	return -ENOTSUPP;
+}
+
 /**
  * caam_get_era() - Return the ERA of the SEC on SoC, based
- * on "sec-era" propery in the DTS. This property is updated by u-boot.
+ * on "sec-era" optional property in the DTS. This property is updated
+ * by u-boot.
+ * In case this property is not passed an attempt to retrieve the CAAM
+ * era via register reads will be made.
  **/
-static int caam_get_era(void)
+static int caam_get_era(struct caam_ctrl __iomem *ctrl)
 {
 	struct device_node *caam_node;
 	int ret;
@@ -295,7 +340,10 @@ static int caam_get_era(void)
 	caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
 	ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
 
-	return IS_ERR_VALUE(ret) ? -ENOTSUPP : prop;
+	if (!ret)
+		return prop;
+	else
+		return caam_get_era_from_hw(ctrl);
 }
 
 /* Probe routine for CAAM top (controller) level */
@@ -593,7 +641,7 @@ static int caam_probe(struct device_d *dev)
 
 	/* Report "alive" for developer to see */
 	dev_dbg(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
-		 caam_get_era());
+		 caam_get_era(ctrl));
 	dev_dbg(dev, "job rings = %d, qi = %d\n",
 		 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
 
diff --git a/drivers/crypto/caam/regs.h b/drivers/crypto/caam/regs.h
index d50e9ad69..6c9d6d75a 100644
--- a/drivers/crypto/caam/regs.h
+++ b/drivers/crypto/caam/regs.h
@@ -307,11 +307,17 @@ struct caam_perfmon {
 
 	/* Component Instantiation Parameters			fe0-fff */
 	u32 rtic_id;		/* RVID - RTIC Version ID	*/
+#define CCBVID_ERA_MASK		0xff000000
+#define CCBVID_ERA_SHIFT	24
 	u32 ccb_id;		/* CCBVID - CCB Version ID	*/
 	u32 cha_id_ms;		/* CHAVID - CHA Version ID Most Significant*/
 	u32 cha_id_ls;		/* CHAVID - CHA Version ID Least Significant*/
 	u32 cha_num_ms;		/* CHANUM - CHA Number Most Significant	*/
 	u32 cha_num_ls;		/* CHANUM - CHA Number Least Significant*/
+#define SECVID_MS_IPID_MASK	0xffff0000
+#define SECVID_MS_IPID_SHIFT	16
+#define SECVID_MS_MAJ_REV_MASK	0x0000ff00
+#define SECVID_MS_MAJ_REV_SHIFT	8
 	u32 caam_id_ms;		/* CAAMVID - CAAM Version ID MS	*/
 	u32 caam_id_ls;		/* CAAMVID - CAAM Version ID LS	*/
 };
-- 
2.18.0


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Re: [PATCH 00/18] crypto: caam: Pull CAAM support improvements from Linux

[Sascha Hauer]

Hi Marcin,

On Mon, Sep 03, 2018 at 01:23:50PM +0200, Marcin Niestroj wrote:
> Hi,
> 
> This is a set of patches, which improve CAAM support. They sync CAAM
> support with Linux v4.19-rc1. Applying them allows to use CAAM on
> ARM IMX devices. Some of these patches had to be adapted to match
> Barebox.

Not sure what you mean with "Applying them allows to use CAAM on
ARM IMX devices". i.MX is the only architecture we ever tested the CAAM
on, so it's supposed to work there without your patches.

Anyway, the patches look good and syncing to Linux is good, so applied.

Sascha


> 
> Marcin Niestroj (18):
>   crypto: caam - fix RNG init descriptor ret. code checking
>   crypto: caam - fix warning in APPEND_MATH_IMM_u64
>   crypto: caam - fix writing to JQCR_MS when using service interface
>   crypto: caam - handle core endianness != caam endianness
>   crypto: caam - add support for iMX6UL
>   crypto: caam - fix sparse warnings
>   crypto: caam - trivial code clean-up
>   crypto: caam - remove unreachable code in report_ccb_status()
>   crypto: caam - constify pointer to descriptor buffer
>   crypto: caam - avoid double inclusion in desc_constr.h
>   crypto: caam - clean-up in caam_init_rng()
>   crypto: caam - fix incorrect define
>   crypto: caam - constify key data
>   crypto: caam - fix endless loop when DECO acquire fails
>   crypto: caam - do not use mem and emi_slow clock for imx7x
>   crypto: caam - sync desc.h with Linux
>   crypto: caam - staticize caam_get_era()
>   crypto: caam - allow retrieving 'era' from register
> 
>  drivers/crypto/caam/caamrng.c     |   9 +-
>  drivers/crypto/caam/ctrl.c        | 240 +++++++++++++++++++-----------
>  drivers/crypto/caam/ctrl.h        |   1 -
>  drivers/crypto/caam/desc.h        |  35 ++---
>  drivers/crypto/caam/desc_constr.h | 118 +++++++++------
>  drivers/crypto/caam/error.c       |   5 +-
>  drivers/crypto/caam/jr.c          |  64 +++-----
>  drivers/crypto/caam/regs.h        | 123 ++++++++++++++-
>  8 files changed, 374 insertions(+), 221 deletions(-)
> 
> -- 
> 2.18.0
> 
> 
> _______________________________________________
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> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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