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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v3 6/8] ARM: nxp-imx8mq-evk: Add FEC's PHY configuration code
Date: Thu, 20 Sep 2018 23:01:00 -0700	[thread overview]
Message-ID: <20180921060102.16341-7-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20180921060102.16341-1-andrew.smirnov@gmail.com>

Add appropriate DT and PHY fixup code needed for i.MX8MQ EVK board.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/board.c | 24 ++++++++++++++++++++++++
 arch/arm/dts/imx8mq-evk.dts            |  1 +
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index 3645e5e71..aae6970d8 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -21,8 +21,30 @@
 #include <init.h>
 #include <asm/memory.h>
 #include <linux/sizes.h>
+#include <linux/phy.h>
 #include <mach/bbu.h>
 
+#include <envfs.h>
+
+#define PHY_ID_AR8031	0x004dd074
+#define AR_PHY_ID_MASK	0xffffffff
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	/*
+	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	 * Phy control debug reg 0
+	 */
+	phy_write(phydev, 0x1d, 0x1f);
+	phy_write(phydev, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, 0x1d, 0x05);
+	phy_write(phydev, 0x1e, 0x100);
+
+	return 0;
+}
+
 static int imx8mq_evk_mem_init(void)
 {
 	if (!of_machine_is_compatible("fsl,imx8mq-evk"))
@@ -45,6 +67,8 @@ static int nxp_imx8mq_evk_init(void)
 
 	imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0);
 
+	phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
+				   ar8031_phy_fixup);
 	return 0;
 }
 device_initcall(nxp_imx8mq_evk_init);
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 3ac13baa1..d6d5d843c 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -43,6 +43,7 @@
 	            <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
 	            <&pinctrl_fec1_phy_reset>;
 	phy-mode = "rgmii-id";
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
-- 
2.17.1


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  parent reply	other threads:[~2018-09-21  6:02 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-09-21  6:00 [PATCH v3 0/8] i.MX8MQ EVK miscellanea Andrey Smirnov
2018-09-21  6:00 ` [PATCH v3 1/8] clk: i.MX8MQ: Bump refcounters of various important clocks Andrey Smirnov
2018-09-21  6:00 ` [PATCH v3 2/8] ARM: i.MX8MQ: Add missing node for ECSPI1 Andrey Smirnov
2018-09-21  6:00 ` [PATCH v3 3/8] ARM: i.MX8MQ: Configure USDHC1,2 clocks Andrey Smirnov
2018-09-21  6:00 ` [PATCH v3 4/8] ARM: i.MX8MQ: Configure FEC1 clocks Andrey Smirnov
2018-09-21  6:00 ` [PATCH v3 5/8] ARM: nxp-imx8mq-evk: Add missing compatibility check Andrey Smirnov
2018-09-21  6:01 ` Andrey Smirnov [this message]
2018-09-21  6:01 ` [PATCH v3 7/8] ARM: i.MX: esdctl: Add memory size detection for i.MX8MQ Andrey Smirnov
2018-09-21  6:01 ` [PATCH v3 8/8] ARM: nxp-imx8mq-evk: Make use of memory size detection code Andrey Smirnov
2018-09-24  7:00 ` [PATCH v3 0/8] i.MX8MQ EVK miscellanea Sascha Hauer

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