[PATCH v3 0/8] i.MX8MQ EVK miscellanea

[PATCH v3 0/8] i.MX8MQ EVK miscellanea

[Andrey Smirnov]

Everyone:

This is a number of i.MX8MQ or EVK related changes that are sitting in
my repo that I am hoping to upstream:

    - Pactches 1, 3, 4 are clock related fixes needed to get FEC,
      USDHC1 and USDHC2 to work.

    - Patch 2 was made while working custom i.MX8MQ board (not
      upstreamed yet) that made use of that controller

    - Patch 5 should be self-explanatory bug fix

    - Patch 6 is PHY configuration code need to use FEC on EVK

    - Patch 7 and 8 are both conveninece code to avoid having to
      specify memory size explicitly as well as a second part of a fix
      for a problem discussed in [1]

Changes since [v1]:

    - Removed redundant DT code in patch 6

Changes since [v2]:

    - Patch 7 re-written such that the code could also be re-used for
      i.MX7 (will be submitted in a separate series)

[1] http://lists.infradead.org/pipermail/barebox/2018-August/034402.html
[v1] http://lists.infradead.org/pipermail/barebox/2018-September/034742.html
[v2] http://lists.infradead.org/pipermail/barebox/2018-September/034772.html

Andrey Smirnov (8):
  clk: i.MX8MQ: Bump refcounters of various important clocks
  ARM: i.MX8MQ: Add missing node for ECSPI1
  ARM: i.MX8MQ: Configure USDHC1,2 clocks
  ARM: i.MX8MQ: Configure FEC1 clocks
  ARM: nxp-imx8mq-evk: Add missing compatibility check
  ARM: nxp-imx8mq-evk: Add FEC's PHY configuration code
  ARM: i.MX: esdctl: Add memory size detection for i.MX8MQ
  ARM: nxp-imx8mq-evk: Make use of memory size detection code

 arch/arm/boards/nxp-imx8mq-evk/board.c    |  27 ++-
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c |   4 +-
 arch/arm/dts/imx8mq-ddrc.dtsi             |  17 ++
 arch/arm/dts/imx8mq-evk.dts               |   7 +-
 arch/arm/dts/imx8mq.dtsi                  |  42 +++++
 arch/arm/mach-imx/esdctl.c                | 191 ++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/esdctl.h   |   1 +
 drivers/clk/imx/clk-imx8mq.c              |  12 ++
 8 files changed, 293 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/dts/imx8mq-ddrc.dtsi

-- 
2.17.1


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[PATCH v3 1/8] clk: i.MX8MQ: Bump refcounters of various important clocks

[Andrey Smirnov]

Bump refcounters of various important clocks in order to make sure
their parents are not disabled during clock re-configuration added by
commits that follow.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/clk/imx/clk-imx8mq.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/clk/imx/clk-imx8mq.c b/drivers/clk/imx/clk-imx8mq.c
index 92d49d44e..782bbc256 100644
--- a/drivers/clk/imx/clk-imx8mq.c
+++ b/drivers/clk/imx/clk-imx8mq.c
@@ -185,6 +185,15 @@ static const char *imx8mq_clko2_sels[] = {"osc_25m", "sys2_pll_200m", "sys1_pll_
 
 static struct clk_onecell_data clk_data;
 
+static int const clks_init_on[] = {
+       IMX8MQ_CLK_DRAM_CORE, IMX8MQ_CLK_AHB_CG,
+       IMX8MQ_CLK_NOC_DIV, IMX8MQ_CLK_NOC_APB_DIV,
+       IMX8MQ_CLK_NAND_USDHC_BUS_SRC,
+       IMX8MQ_CLK_MAIN_AXI_SRC, IMX8MQ_CLK_A53_CG,
+       IMX8MQ_CLK_AUDIO_AHB_DIV, IMX8MQ_CLK_TMU_ROOT,
+       IMX8MQ_CLK_DRAM_APB_SRC,
+};
+
 static void __init imx8mq_clocks_init(struct device_node *ccm_node)
 {
 	struct device_node *np;
@@ -572,6 +581,9 @@ static void __init imx8mq_clocks_init(struct device_node *ccm_node)
 			pr_err("i.MX8mq clk %u register failed with %ld\n",
 			       i, PTR_ERR(clks[i]));
 
+	for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
+		clk_enable(clks[clks_init_on[i]]);
+
 	clk_data.clks = clks;
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-- 
2.17.1


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[PATCH v3 2/8] ARM: i.MX8MQ: Add missing node for ECSPI1

[Andrey Smirnov]

Add node for ECSPI1 that is missing from imx8mq.dtsi

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/dts/imx8mq.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index c67438a48..6f860c3d6 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -288,6 +288,16 @@
 			#size-cells = <1>;
 			ranges = <0x30800000 0x30800000 0x400000>;
 
+			ecspi1: ecspi@30820000 {
+				compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
+				reg = <0x30820000 0x10000>;
+				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>,
+				<&clk IMX8MQ_CLK_ECSPI1_ROOT>;
+				clock-names = "ipg", "per";
+				status = "disabled";
+			};
+
 			uart1: serial@30860000 {
 				compatible = "fsl,imx8mq-uart",
 				             "fsl,imx6q-uart";
-- 
2.17.1


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[PATCH v3 3/8] ARM: i.MX8MQ: Configure USDHC1,2 clocks

[Andrey Smirnov]

Select appropriate parents as well as clock rates for USDHC1 and
USDHC2 related clocks.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/dts/imx8mq.dtsi | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 6f860c3d6..8bdf4efb7 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -632,3 +632,23 @@
 		};
 	};
 };
+
+
+
+&clk {
+	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_SRC>,
+			  <&clk IMX8MQ_CLK_USDHC1_DIV>,
+			  <&clk IMX8MQ_CLK_USDHC2_SRC>,
+			  <&clk IMX8MQ_CLK_USDHC2_DIV>;
+
+	assigned-clock-parents =  <&clk IMX8MQ_SYS1_PLL_400M>,
+				  <0>,
+				  <&clk IMX8MQ_SYS1_PLL_400M>,
+				  <0>;
+
+	assigned-clock-rates = <400000000>,
+			       <200000000>,
+			       <400000000>,
+			       <200000000>;
+};
+
-- 
2.17.1


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[PATCH v3 4/8] ARM: i.MX8MQ: Configure FEC1 clocks

[Andrey Smirnov]

Select proper parents as well as rates for FEC1 related clocks.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/dts/imx8mq.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 8bdf4efb7..763005217 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -639,16 +639,28 @@
 	assigned-clocks = <&clk IMX8MQ_CLK_USDHC1_SRC>,
 			  <&clk IMX8MQ_CLK_USDHC1_DIV>,
 			  <&clk IMX8MQ_CLK_USDHC2_SRC>,
-			  <&clk IMX8MQ_CLK_USDHC2_DIV>;
+			  <&clk IMX8MQ_CLK_USDHC2_DIV>,
+			  <&clk IMX8MQ_CLK_ENET_AXI_SRC>,
+			  <&clk IMX8MQ_CLK_ENET_TIMER_SRC>,
+			  <&clk IMX8MQ_CLK_ENET_REF_SRC>,
+			  <&clk IMX8MQ_CLK_ENET_TIMER_DIV>;
 
 	assigned-clock-parents =  <&clk IMX8MQ_SYS1_PLL_400M>,
 				  <0>,
 				  <&clk IMX8MQ_SYS1_PLL_400M>,
+				  <0>,
+				  <&clk IMX8MQ_SYS1_PLL_266M>,
+				  <&clk IMX8MQ_SYS2_PLL_100M>,
+				  <&clk IMX8MQ_SYS2_PLL_125M>,
 				  <0>;
 
 	assigned-clock-rates = <400000000>,
 			       <200000000>,
 			       <400000000>,
-			       <200000000>;
+			       <200000000>,
+			       <266000000>,
+			       <0>,
+			       <125000000>,
+			       <25000000>;
 };
 
-- 
2.17.1


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[PATCH v3 5/8] ARM: nxp-imx8mq-evk: Add missing compatibility check

[Andrey Smirnov]

Add missing compatibility check to imx8mq_evk_mem_init() to prevent it
from being executed for other i.MX8MQ boards.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/board.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index 868c25ebb..3645e5e71 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -25,6 +25,9 @@
 
 static int imx8mq_evk_mem_init(void)
 {
+	if (!of_machine_is_compatible("fsl,imx8mq-evk"))
+		return 0;
+
 	arm_add_mem_device("ram0", 0x40000000, SZ_2G);
 
 	request_sdram_region("ATF", 0x40000000, SZ_128K);
-- 
2.17.1


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[PATCH v3 6/8] ARM: nxp-imx8mq-evk: Add FEC's PHY configuration code

[Andrey Smirnov]

Add appropriate DT and PHY fixup code needed for i.MX8MQ EVK board.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/board.c | 24 ++++++++++++++++++++++++
 arch/arm/dts/imx8mq-evk.dts            |  1 +
 2 files changed, 25 insertions(+)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index 3645e5e71..aae6970d8 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -21,8 +21,30 @@
 #include <init.h>
 #include <asm/memory.h>
 #include <linux/sizes.h>
+#include <linux/phy.h>
 #include <mach/bbu.h>
 
+#include <envfs.h>
+
+#define PHY_ID_AR8031	0x004dd074
+#define AR_PHY_ID_MASK	0xffffffff
+
+static int ar8031_phy_fixup(struct phy_device *phydev)
+{
+	/*
+	 * Enable 1.8V(SEL_1P5_1P8_POS_REG) on
+	 * Phy control debug reg 0
+	 */
+	phy_write(phydev, 0x1d, 0x1f);
+	phy_write(phydev, 0x1e, 0x8);
+
+	/* rgmii tx clock delay enable */
+	phy_write(phydev, 0x1d, 0x05);
+	phy_write(phydev, 0x1e, 0x100);
+
+	return 0;
+}
+
 static int imx8mq_evk_mem_init(void)
 {
 	if (!of_machine_is_compatible("fsl,imx8mq-evk"))
@@ -45,6 +67,8 @@ static int nxp_imx8mq_evk_init(void)
 
 	imx8mq_bbu_internal_mmc_register_handler("eMMC", "/dev/mmc0", 0);
 
+	phy_register_fixup_for_uid(PHY_ID_AR8031, AR_PHY_ID_MASK,
+				   ar8031_phy_fixup);
 	return 0;
 }
 device_initcall(nxp_imx8mq_evk_init);
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index 3ac13baa1..d6d5d843c 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -43,6 +43,7 @@
 	            <&pinctrl_fec1_data_tx>, <&pinctrl_fec1_data_rx>,
 	            <&pinctrl_fec1_phy_reset>;
 	phy-mode = "rgmii-id";
+	phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
-- 
2.17.1


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[PATCH v3 7/8] ARM: i.MX: esdctl: Add memory size detection for i.MX8MQ

[Andrey Smirnov]

Add memory size detection for i.MX8MQ. Only basic LPDDR4
configurations are supported for now. Support for other types of
memory can be added later once we have any boards that use it.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/dts/imx8mq-ddrc.dtsi           |  17 +++
 arch/arm/mach-imx/esdctl.c              | 191 ++++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/esdctl.h |   1 +
 3 files changed, 209 insertions(+)
 create mode 100644 arch/arm/dts/imx8mq-ddrc.dtsi

diff --git a/arch/arm/dts/imx8mq-ddrc.dtsi b/arch/arm/dts/imx8mq-ddrc.dtsi
new file mode 100644
index 000000000..26d3da857
--- /dev/null
+++ b/arch/arm/dts/imx8mq-ddrc.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Include file to switch board DTS form using hardcoded memory node
+ * to dynamic memory size detection based on DDR controller settings
+ */
+
+/ {
+
+	/delete-node/ memory@40000000;
+
+	peripherals@0 {
+		ddrc@3d400000 {
+			compatible = "fsl,imx8mq-ddrc";
+			reg = <0x3d400000 0x400000>;
+		};
+	};
+};
+
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 875e942de..14945bc7b 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -23,6 +23,7 @@
 #include <init.h>
 #include <of.h>
 #include <linux/err.h>
+#include <linux/bitfield.h>
 #include <asm/barebox-arm.h>
 #include <asm/memory.h>
 #include <mach/esdctl.h>
@@ -38,6 +39,7 @@
 #include <mach/imx53-regs.h>
 #include <mach/imx6-regs.h>
 #include <mach/vf610-ddrmc.h>
+#include <mach/imx8mq-regs.h>
 
 struct imx_esdctl_data {
 	unsigned long base0;
@@ -319,6 +321,169 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 			   vf610_ddrmc_sdram_size(mmdcbase));
 }
 
+#define DDRC_ADDRMAP(n)				(0x200 + 4 * (n))
+#define DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB	GENMASK(30, 29)
+#define DDRC_ADDRMAP0_CS_BIT0			GENMASK(4, 0)
+
+#define DDRC_MSTR				0x0000
+#define DDRC_MSTR_LPDDR4			BIT(5)
+#define DDRC_MSTR_DATA_BUS_WIDTH		GENMASK(13, 12)
+#define DDRC_MSTR_ACTIVE_RANKS			GENMASK(27, 24)
+
+#define DDRC_ADDRMAP0_CS_BIT1			GENMASK(12,  8)
+
+#define DDRC_ADDRMAP1_BANK_B2			GENMASK(20, 16)
+
+#define DDRC_ADDRMAP2_COL_B5			GENMASK(27, 24)
+#define DDRC_ADDRMAP2_COL_B4			GENMASK(19, 16)
+
+#define DDRC_ADDRMAP3_COL_B9			GENMASK(27, 24)
+#define DDRC_ADDRMAP3_COL_B8			GENMASK(19, 16)
+#define DDRC_ADDRMAP3_COL_B7			GENMASK(11,  8)
+#define DDRC_ADDRMAP3_COL_B6			GENMASK( 3,  0)
+
+#define DDRC_ADDRMAP4_COL_B10			GENMASK(3, 0)
+#define DDRC_ADDRMAP4_COL_B11			GENMASK(11, 8)
+
+#define DDRC_ADDRMAP5_ROW_B11			GENMASK(27, 24)
+
+#define DDRC_ADDRMAP6_ROW_B15			GENMASK(27, 24)
+#define DDRC_ADDRMAP6_ROW_B14			GENMASK(19, 16)
+#define DDRC_ADDRMAP6_ROW_B13			GENMASK(11,  8)
+#define DDRC_ADDRMAP6_ROW_B12			GENMASK( 3,  0)
+
+#define DDRC_ADDRMAP7_ROW_B17			GENMASK(11,  8)
+#define DDRC_ADDRMAP7_ROW_B16			GENMASK( 3,  0)
+
+static unsigned int
+imx_ddrc_count_bits(unsigned int bits, const u8 config[],
+		     unsigned int config_num)
+{
+	unsigned int i;
+	for (i = 0; i < config_num && config[i] == 0b1111; i++)
+		bits--;
+
+	return bits;
+}
+
+static resource_size_t
+imx_ddrc_sdram_size(void __iomem *ddrc, const u32 addrmap[],
+		    u8 col_max, const u8 col_b[], unsigned int col_b_num,
+		    u8 row_max, const u8 row_b[], unsigned int row_b_num,
+		    bool reduced_adress_space)
+{
+	const u32 mstr = readl(ddrc + DDRC_MSTR);
+	unsigned int banks, ranks, columns, rows, active_ranks, width;
+	resource_size_t size;
+
+	banks = 2;
+	ranks = 0;
+
+	switch (FIELD_GET(DDRC_MSTR_ACTIVE_RANKS, mstr)) {
+	case 0b0001:
+		active_ranks = 1;
+		break;
+	case 0b0011:
+		active_ranks = 2;
+		break;
+	case 0b1111:
+		active_ranks = 4;
+		break;
+	default:
+		BUG();
+	}
+
+	switch (FIELD_GET(DDRC_MSTR_DATA_BUS_WIDTH, mstr)) {
+	case 0b00:	/* Full DQ bus  */
+		width = 4;
+		break;
+	case 0b01:      /* Half DQ bus  */
+		width = 2;
+		break;
+	case 0b10:	/* Quarter DQ bus  */
+		width = 1;
+		break;
+	default:
+		BUG();
+	}
+
+	if (active_ranks == 4 &&
+	    FIELD_GET(DDRC_ADDRMAP0_CS_BIT1, addrmap[0]) != 0b11111)
+		ranks++;
+
+	if (active_ranks > 1  &&
+	    FIELD_GET(DDRC_ADDRMAP0_CS_BIT0, addrmap[0]) != 0b11111)
+		ranks++;
+
+	if (FIELD_GET(DDRC_ADDRMAP1_BANK_B2, addrmap[1]) != 0b11111)
+		banks++;
+
+	columns = imx_ddrc_count_bits(col_max, col_b, col_b_num);
+	rows    = imx_ddrc_count_bits(row_max, row_b, row_b_num);
+
+	size = memory_sdram_size(columns, rows, 1 << banks, width) << ranks;
+
+	return reduced_adress_space ? size * 3 / 4 : size;
+}
+
+static resource_size_t imx8mq_ddrc_sdram_size(void __iomem *ddrc)
+{
+	const u32 addrmap[] = {
+		readl(ddrc + DDRC_ADDRMAP(0)),
+		readl(ddrc + DDRC_ADDRMAP(1)),
+		readl(ddrc + DDRC_ADDRMAP(2)),
+		readl(ddrc + DDRC_ADDRMAP(3)),
+		readl(ddrc + DDRC_ADDRMAP(4)),
+		readl(ddrc + DDRC_ADDRMAP(5)),
+		readl(ddrc + DDRC_ADDRMAP(6)),
+		readl(ddrc + DDRC_ADDRMAP(7))
+	};
+	const u8 col_b[] = {
+		/*
+		 * FIXME: DDR register spreadsheet mentiones that B10
+		 * and B11 are 5-bit fields instead of 4. Needs to be
+		 * clarified.
+		 */
+		FIELD_GET(DDRC_ADDRMAP4_COL_B11, addrmap[4]),
+		FIELD_GET(DDRC_ADDRMAP4_COL_B10, addrmap[4]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B9,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B8,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B7,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B6,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP2_COL_B5,  addrmap[2]),
+		FIELD_GET(DDRC_ADDRMAP2_COL_B4,  addrmap[2]),
+	};
+	const u8 row_b[] = {
+		/*
+		 * FIXME: RM mentions the following fields as being
+		 * present, but looking at the code generated by DDR
+		 * tool it doesn't look like those registers are
+		 * really implemented/used.
+		 *
+		 * FIELD_GET(DDRC_ADDRMAP7_ROW_B17, addrmap[7]),
+		 * FIELD_GET(DDRC_ADDRMAP7_ROW_B16, addrmap[7]),
+		 */
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B12, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP5_ROW_B11, addrmap[5]),
+	};
+	const bool reduced_adress_space =
+		FIELD_GET(DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB, addrmap[6]);
+
+	return imx_ddrc_sdram_size(ddrc, addrmap,
+				   12, ARRAY_AND_SIZE(col_b),
+				   16, ARRAY_AND_SIZE(row_b),
+				   reduced_adress_space);
+}
+
+static void imx8mq_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+	arm_add_mem_device("ram0", data->base0,
+			   imx8mq_ddrc_sdram_size(mmdcbase));
+}
+
 static int imx_esdctl_probe(struct device_d *dev)
 {
 	struct resource *iores;
@@ -405,6 +570,11 @@ static __maybe_unused struct imx_esdctl_data vf610_data = {
 	.add_mem = vf610_ddrmc_add_mem,
 };
 
+static __maybe_unused struct imx_esdctl_data imx8mq_data = {
+	.base0 = MX8MQ_DDR_CSD1_BASE_ADDR,
+	.add_mem = imx8mq_ddrc_add_mem,
+};
+
 static struct platform_device_id imx_esdctl_ids[] = {
 #ifdef CONFIG_ARCH_IMX1
 	{
@@ -469,6 +639,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 	}, {
 		.compatible = "fsl,vf610-ddrmc",
 		.data = &vf610_data
+	}, {
+		.compatible = "fsl,imx8mq-ddrc",
+		.data = &imx8mq_data
 	}, {
 		/* sentinel */
 	}
@@ -643,3 +816,21 @@ void __noreturn vf610_barebox_entry(void *boarddata)
 			  vf610_ddrmc_sdram_size(IOMEM(VF610_DDR_BASE_ADDR)),
 			  boarddata);
 }
+
+void __noreturn imx8mq_barebox_entry(void *boarddata)
+{
+	resource_size_t size;
+
+	size = imx8mq_ddrc_sdram_size(IOMEM(MX8MQ_DDRC_CTL_BASE_ADDR));
+	/*
+	 * We artificially limit detected memory size to force malloc
+	 * pool placement to be within 4GiB address space, so as to
+	 * make it accessible to 32-bit limited DMA.
+	 *
+	 * This limitation affects only early boot code and malloc
+	 * pool placement. The rest of the system should be able to
+	 * detect and utilize full amount of memory.
+	 */
+	size = min_t(resource_size_t, SZ_4G - MX8MQ_DDR_CSD1_BASE_ADDR, size);
+	barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR, size, boarddata);
+}
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index 117e2bbad..ff109aa10 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -139,6 +139,7 @@ void __noreturn imx53_barebox_entry(void *boarddata);
 void __noreturn imx6q_barebox_entry(void *boarddata);
 void __noreturn imx6ul_barebox_entry(void *boarddata);
 void __noreturn vf610_barebox_entry(void *boarddata);
+void __noreturn imx8mq_barebox_entry(void *boarddata);
 void imx_esdctl_disable(void);
 #endif
 
-- 
2.17.1


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[PATCH v3 8/8] ARM: nxp-imx8mq-evk: Make use of memory size detection code

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/nxp-imx8mq-evk/board.c    | 2 --
 arch/arm/boards/nxp-imx8mq-evk/lowlevel.c | 4 ++--
 arch/arm/dts/imx8mq-evk.dts               | 6 +-----
 3 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/arch/arm/boards/nxp-imx8mq-evk/board.c b/arch/arm/boards/nxp-imx8mq-evk/board.c
index aae6970d8..764eadb76 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/board.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/board.c
@@ -50,8 +50,6 @@ static int imx8mq_evk_mem_init(void)
 	if (!of_machine_is_compatible("fsl,imx8mq-evk"))
 		return 0;
 
-	arm_add_mem_device("ram0", 0x40000000, SZ_2G);
-
 	request_sdram_region("ATF", 0x40000000, SZ_128K);
 
 	return 0;
diff --git a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
index 438c70c87..1dff4b4d3 100644
--- a/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
+++ b/arch/arm/boards/nxp-imx8mq-evk/lowlevel.c
@@ -24,6 +24,7 @@
 #include <asm/sections.h>
 #include <asm/mmu.h>
 #include <mach/atf.h>
+#include <mach/esdctl.h>
 
 #include "ddr.h"
 
@@ -121,7 +122,6 @@ ENTRY_FUNCTION(start_nxp_imx8mq_evk, r0, r1, r2)
 	/*
 	 * Standard entry we hit once we initialized both DDR and ATF
 	 */
-	barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR,
-			  SZ_2G + SZ_1G, __dtb_imx8mq_evk_start);
+	imx8mq_barebox_entry(__dtb_imx8mq_evk_start);
 }
 
diff --git a/arch/arm/dts/imx8mq-evk.dts b/arch/arm/dts/imx8mq-evk.dts
index d6d5d843c..a6e724e2e 100644
--- a/arch/arm/dts/imx8mq-evk.dts
+++ b/arch/arm/dts/imx8mq-evk.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include "imx8mq.dtsi"
+#include "imx8mq-ddrc.dtsi"
 
 / {
 	model = "NXP i.MX8MQ EVK";
@@ -16,11 +17,6 @@
 		stdout-path = &uart1;
 	};
 
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x00000000 0x40000000 0 0xc0000000>;
-	};
-
 	reg_usdhc2_vmmc: regulator-vsd-3v3 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_reg_usdhc2>;
-- 
2.17.1


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Re: [PATCH v3 0/8] i.MX8MQ EVK miscellanea

[Sascha Hauer]

On Thu, Sep 20, 2018 at 11:00:54PM -0700, Andrey Smirnov wrote:
> Everyone:
> 
> This is a number of i.MX8MQ or EVK related changes that are sitting in
> my repo that I am hoping to upstream:
> 
>     - Pactches 1, 3, 4 are clock related fixes needed to get FEC,
>       USDHC1 and USDHC2 to work.
> 
>     - Patch 2 was made while working custom i.MX8MQ board (not
>       upstreamed yet) that made use of that controller
> 
>     - Patch 5 should be self-explanatory bug fix
> 
>     - Patch 6 is PHY configuration code need to use FEC on EVK
> 
>     - Patch 7 and 8 are both conveninece code to avoid having to
>       specify memory size explicitly as well as a second part of a fix
>       for a problem discussed in [1]
> 
> Changes since [v1]:
> 
>     - Removed redundant DT code in patch 6
> 
> Changes since [v2]:
> 
>     - Patch 7 re-written such that the code could also be re-used for
>       i.MX7 (will be submitted in a separate series)
> 
> [1] http://lists.infradead.org/pipermail/barebox/2018-August/034402.html
> [v1] http://lists.infradead.org/pipermail/barebox/2018-September/034742.html
> [v2] http://lists.infradead.org/pipermail/barebox/2018-September/034772.html
> 
> Andrey Smirnov (8):
>   clk: i.MX8MQ: Bump refcounters of various important clocks
>   ARM: i.MX8MQ: Add missing node for ECSPI1
>   ARM: i.MX8MQ: Configure USDHC1,2 clocks
>   ARM: i.MX8MQ: Configure FEC1 clocks
>   ARM: nxp-imx8mq-evk: Add missing compatibility check
>   ARM: nxp-imx8mq-evk: Add FEC's PHY configuration code
>   ARM: i.MX: esdctl: Add memory size detection for i.MX8MQ
>   ARM: nxp-imx8mq-evk: Make use of memory size detection code

Applied, thanks

Sascha


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