[PATCH v2 0/6] ZII RPU2 i.MX7D board support

[PATCH v2 0/6] ZII RPU2 i.MX7D board support

[Andrey Smirnov]

Everyone:

This series is a number of small patches I developed while adding
support for ZII's RPU2 board. Hopefully all of them are self-explanatory.

Feedback is welcome!

Changes since [v1]:

    - Renamed flash-header-mx7-default.imxcfg to flash-header-mx7-sabresd.imxcfg

Thanks,
Andrey Smirnov

[v1] http://lists.infradead.org/pipermail/barebox/2018-September/034845.html

Andrey Smirnov (6):
  ARM: i.MX: esdctl: Add memory size detection for i.MX7D
  ARM: freescale-mx7-sabresd: Make use of imx7d_barebox_entry()
  i.MX7D: DCD: Create shared DDR configuration header
  ARM: i.MX7: bbu: Add MMC boot handler
  ARM: i.MX7: bbu: Add I2C and SPI handler
  i.MX: Add support for ZII's i.MX7D-based RPU2 board

 arch/arm/boards/Makefile                      |   1 +
 .../flash-header-mx7-sabresd.imxcfg           |  79 +--
 .../boards/freescale-mx7-sabresd/lowlevel.c   |   7 +-
 arch/arm/boards/zii-imx7d-rpu2/Makefile       |   2 +
 arch/arm/boards/zii-imx7d-rpu2/board.c        |  49 ++
 .../flash-header-zii-imx7d-rpu2.imxcfg        |   6 +
 arch/arm/boards/zii-imx7d-rpu2/lowlevel.c     |  50 ++
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/imx7d-ddrc.dtsi                  |  15 +
 arch/arm/dts/imx7d-zii-rpu2.dts               | 613 ++++++++++++++++++
 arch/arm/mach-imx/Kconfig                     |   4 +
 arch/arm/mach-imx/esdctl.c                    |  61 ++
 arch/arm/mach-imx/imx-bbu-internal.c          |  11 +
 arch/arm/mach-imx/include/mach/bbu.h          |  20 +
 arch/arm/mach-imx/include/mach/esdctl.h       |   1 +
 .../flash-header/imx7d-ddr-sabresd.imxcfg     |  78 +++
 arch/arm/mach-imx/include/mach/imx7-regs.h    |   2 +
 images/Makefile.imx                           |   5 +
 18 files changed, 923 insertions(+), 83 deletions(-)
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/Makefile
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/board.c
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
 create mode 100644 arch/arm/dts/imx7d-ddrc.dtsi
 create mode 100644 arch/arm/dts/imx7d-zii-rpu2.dts
 create mode 100644 arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg

-- 
2.17.1


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[PATCH v2 1/6] ARM: i.MX: esdctl: Add memory size detection for i.MX7D

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/dts/imx7d-ddrc.dtsi               | 15 ++++++
 arch/arm/mach-imx/esdctl.c                 | 61 ++++++++++++++++++++++
 arch/arm/mach-imx/include/mach/esdctl.h    |  1 +
 arch/arm/mach-imx/include/mach/imx7-regs.h |  2 +
 4 files changed, 79 insertions(+)
 create mode 100644 arch/arm/dts/imx7d-ddrc.dtsi

diff --git a/arch/arm/dts/imx7d-ddrc.dtsi b/arch/arm/dts/imx7d-ddrc.dtsi
new file mode 100644
index 000000000..b4cd597be
--- /dev/null
+++ b/arch/arm/dts/imx7d-ddrc.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Include file to switch board DTS form using hardcoded memory node
+ * to dynamic memory size detection based on DDR controller settings
+ */
+
+/ {
+	/delete-node/ memory;
+};
+
+&aips2 {
+	ddrc@307a0000 {
+		compatible = "fsl,imx7d-ddrc";
+		reg = <0x307a0000 0x10000>;
+	};
+};
\ No newline at end of file
diff --git a/arch/arm/mach-imx/esdctl.c b/arch/arm/mach-imx/esdctl.c
index 14945bc7b..074e3ac5a 100644
--- a/arch/arm/mach-imx/esdctl.c
+++ b/arch/arm/mach-imx/esdctl.c
@@ -40,6 +40,7 @@
 #include <mach/imx6-regs.h>
 #include <mach/vf610-ddrmc.h>
 #include <mach/imx8mq-regs.h>
+#include <mach/imx7-regs.h>
 
 struct imx_esdctl_data {
 	unsigned long base0;
@@ -323,6 +324,7 @@ static void vf610_ddrmc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 
 #define DDRC_ADDRMAP(n)				(0x200 + 4 * (n))
 #define DDRC_ADDRMAP6_LPDDR4_6GB_12GB_24GB	GENMASK(30, 29)
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB		BIT(31)
 #define DDRC_ADDRMAP0_CS_BIT0			GENMASK(4, 0)
 
 #define DDRC_MSTR				0x0000
@@ -484,6 +486,48 @@ static void imx8mq_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
 			   imx8mq_ddrc_sdram_size(mmdcbase));
 }
 
+static resource_size_t imx7d_ddrc_sdram_size(void __iomem *ddrc)
+{
+	const u32 addrmap[] = {
+		readl(ddrc + DDRC_ADDRMAP(0)),
+		readl(ddrc + DDRC_ADDRMAP(1)),
+		readl(ddrc + DDRC_ADDRMAP(2)),
+		readl(ddrc + DDRC_ADDRMAP(3)),
+		readl(ddrc + DDRC_ADDRMAP(4)),
+		readl(ddrc + DDRC_ADDRMAP(5)),
+		readl(ddrc + DDRC_ADDRMAP(6))
+	};
+	const u8 col_b[] = {
+		FIELD_GET(DDRC_ADDRMAP4_COL_B10, addrmap[4]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B9,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B8,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B7,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP3_COL_B6,  addrmap[3]),
+		FIELD_GET(DDRC_ADDRMAP2_COL_B5,  addrmap[2]),
+		FIELD_GET(DDRC_ADDRMAP2_COL_B4,  addrmap[2]),
+	};
+	const u8 row_b[] = {
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B15, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B14, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B13, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP6_ROW_B12, addrmap[6]),
+		FIELD_GET(DDRC_ADDRMAP5_ROW_B11, addrmap[5]),
+	};
+	const bool reduced_adress_space =
+		FIELD_GET(DDRC_ADDRMAP6_LPDDR3_6GB_12GB, addrmap[6]);
+
+	return imx_ddrc_sdram_size(ddrc, addrmap,
+				   11, ARRAY_AND_SIZE(col_b),
+				   15, ARRAY_AND_SIZE(row_b),
+				   reduced_adress_space);
+}
+
+static void imx7d_ddrc_add_mem(void *mmdcbase, struct imx_esdctl_data *data)
+{
+	arm_add_mem_device("ram0", data->base0,
+			   imx7d_ddrc_sdram_size(mmdcbase));
+}
+
 static int imx_esdctl_probe(struct device_d *dev)
 {
 	struct resource *iores;
@@ -575,6 +619,11 @@ static __maybe_unused struct imx_esdctl_data imx8mq_data = {
 	.add_mem = imx8mq_ddrc_add_mem,
 };
 
+static __maybe_unused struct imx_esdctl_data imx7d_data = {
+	.base0 = MX7_DDR_BASE_ADDR,
+	.add_mem = imx7d_ddrc_add_mem,
+};
+
 static struct platform_device_id imx_esdctl_ids[] = {
 #ifdef CONFIG_ARCH_IMX1
 	{
@@ -642,6 +691,9 @@ static __maybe_unused struct of_device_id imx_esdctl_dt_ids[] = {
 	}, {
 		.compatible = "fsl,imx8mq-ddrc",
 		.data = &imx8mq_data
+	}, {
+		.compatible = "fsl,imx7d-ddrc",
+		.data = &imx7d_data
 	}, {
 		/* sentinel */
 	}
@@ -834,3 +886,12 @@ void __noreturn imx8mq_barebox_entry(void *boarddata)
 	size = min_t(resource_size_t, SZ_4G - MX8MQ_DDR_CSD1_BASE_ADDR, size);
 	barebox_arm_entry(MX8MQ_DDR_CSD1_BASE_ADDR, size, boarddata);
 }
+
+void __noreturn imx7d_barebox_entry(void *boarddata)
+{
+	barebox_arm_entry(MX7_DDR_BASE_ADDR,
+			  imx7d_ddrc_sdram_size(IOMEM(MX7_DDRC_BASE_ADDR)),
+			  boarddata);
+}
+
+
diff --git a/arch/arm/mach-imx/include/mach/esdctl.h b/arch/arm/mach-imx/include/mach/esdctl.h
index ff109aa10..bc6c73395 100644
--- a/arch/arm/mach-imx/include/mach/esdctl.h
+++ b/arch/arm/mach-imx/include/mach/esdctl.h
@@ -140,6 +140,7 @@ void __noreturn imx6q_barebox_entry(void *boarddata);
 void __noreturn imx6ul_barebox_entry(void *boarddata);
 void __noreturn vf610_barebox_entry(void *boarddata);
 void __noreturn imx8mq_barebox_entry(void *boarddata);
+void __noreturn imx7d_barebox_entry(void *boarddata);
 void imx_esdctl_disable(void);
 #endif
 
diff --git a/arch/arm/mach-imx/include/mach/imx7-regs.h b/arch/arm/mach-imx/include/mach/imx7-regs.h
index 8625d0b61..21e2830b9 100644
--- a/arch/arm/mach-imx/include/mach/imx7-regs.h
+++ b/arch/arm/mach-imx/include/mach/imx7-regs.h
@@ -116,4 +116,6 @@
 #define MX7_ENET1_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3E0000)
 #define MX7_ENET2_BASE_ADDR		(MX7_AIPS3_BASE_ADDR + 0x3F0000)
 
+#define MX7_DDR_BASE_ADDR		0x80000000
+
 #endif /* __MACH_IMX7_REGS_H */
-- 
2.17.1


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[PATCH v2 2/6] ARM: freescale-mx7-sabresd: Make use of imx7d_barebox_entry()

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/freescale-mx7-sabresd/lowlevel.c | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
index 43aa61075..f718ea73b 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
+++ b/arch/arm/boards/freescale-mx7-sabresd/lowlevel.c
@@ -9,6 +9,7 @@
 #include <mach/iomux-mx7.h>
 #include <mach/debug_ll.h>
 #include <asm/cache.h>
+#include <mach/esdctl.h>
 
 extern char __dtb_imx7d_sdb_start[];
 
@@ -33,14 +34,10 @@ static inline void setup_uart(void)
 
 ENTRY_FUNCTION(start_imx7d_sabresd, r0, r1, r2)
 {
-	void *fdt;
-
 	imx7_cpu_lowlevel_init();
 
 	if (IS_ENABLED(CONFIG_DEBUG_LL))
 		setup_uart();
 
-	fdt = __dtb_imx7d_sdb_start + get_runtime_offset();
-
-	barebox_arm_entry(0x80000000, SZ_1G, fdt);
+	imx7d_barebox_entry(__dtb_imx7d_sdb_start + get_runtime_offset());
 }
-- 
2.17.1


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[PATCH v2 3/6] i.MX7D: DCD: Create shared DDR configuration header

[Andrey Smirnov]

Create a shared DDR configuration header based on configuration used
by i.MX7D SabreSD board.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 .../flash-header-mx7-sabresd.imxcfg           | 79 +------------------
 .../flash-header/imx7d-ddr-sabresd.imxcfg     | 78 ++++++++++++++++++
 2 files changed, 79 insertions(+), 78 deletions(-)
 create mode 100644 arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg

diff --git a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
index 83ed2dc06..f4920bc13 100644
--- a/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
+++ b/arch/arm/boards/freescale-mx7-sabresd/flash-header-mx7-sabresd.imxcfg
@@ -1,82 +1,5 @@
-/*
- * Copyright (C) 2016 NXP Semiconductors
- *
- * SPDX-License-Identifier:	GPL-2.0
- *
- * Refer docs/README.imxmage for more details about how-to configure
- * and create imximage boot image
- *
- * The syntax is taken as close as possible with the kwbimage
- *
- * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit
- * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d
- */
-
 soc imx7
 loadaddr 0x80000000
 dcdofs 0x400
 
-#include <mach/imx7-ddr-regs.h>
-
-wm 32 0x30340004 0x4F400005
-
-wm 32 0x30391000 0x00000002
-
-wm 32 MX7_DDRC_MSTR 0x01040001
-wm 32 MX7_DDRC_DFIUPD0 0x80400003
-wm 32 MX7_DDRC_DFIUPD1 0x00100020
-wm 32 MX7_DDRC_DFIUPD2 0x80100004
-wm 32 MX7_DDRC_RFSHTMG 0x00400046
-wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001
-wm 32 MX7_DDRC_INIT0 0x00020083
-wm 32 MX7_DDRC_INIT1 0x00690000
-wm 32 MX7_DDRC_INIT3 0x09300004
-wm 32 MX7_DDRC_INIT4 0x04080000
-wm 32 MX7_DDRC_INIT5 0x00100004
-wm 32 MX7_DDRC_RANKCTL 0x0000033f
-wm 32 MX7_DDRC_DRAMTMG0 0x09081109
-wm 32 MX7_DDRC_DRAMTMG1 0x0007020d
-wm 32 MX7_DDRC_DRAMTMG2 0x03040407
-wm 32 MX7_DDRC_DRAMTMG3 0x00002006
-wm 32 MX7_DDRC_DRAMTMG4 0x04020205
-wm 32 MX7_DDRC_DRAMTMG5 0x03030202
-wm 32 MX7_DDRC_DRAMTMG8 0x00000803
-wm 32 MX7_DDRC_ZQCTL0 0x00800020
-wm 32 MX7_DDRC_ZQCTL1 0x02000100
-wm 32 MX7_DDRC_DFITMG0 0x02098204
-wm 32 MX7_DDRC_DFITMG1 0x00030303
-wm 32 MX7_DDRC_ADDRMAP0 0x00000016
-wm 32 MX7_DDRC_ADDRMAP1 0x00171717
-wm 32 MX7_DDRC_ADDRMAP5 0x04040404
-wm 32 MX7_DDRC_ADDRMAP6 0x0f040404
-wm 32 MX7_DDRC_ODTCFG 0x06000604
-wm 32 MX7_DDRC_ODTMAP 0x00000001
-
-wm 32 0x30391000 0x00000000
-
-wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40
-wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100
-wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807
-wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e
-wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e
-wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808
-wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808
-wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010
-wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010
-
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
-
-check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1
-
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
-wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
-
-wm 32 0x30384130 0x00000000
-wm 32 0x30340020 0x00000178
-wm 32 0x30384130 0x00000002
-
-wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
-
-check 32 until_any_bit_set MX7_DDRC_STAT 0x1
+#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
\ No newline at end of file
diff --git a/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg b/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg
new file mode 100644
index 000000000..e98f055ee
--- /dev/null
+++ b/arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016 NXP Semiconductors
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ *
+ * Taken from upstream U-Boot git://git.denx.de/u-boot.git, commit
+ * 1a8150d4b16fbafa6f1d207ddb85eda7dc399e2d
+ */
+
+#include <mach/imx7-ddr-regs.h>
+
+wm 32 0x30340004 0x4F400005
+
+wm 32 0x30391000 0x00000002
+
+wm 32 MX7_DDRC_MSTR 0x01040001
+wm 32 MX7_DDRC_DFIUPD0 0x80400003
+wm 32 MX7_DDRC_DFIUPD1 0x00100020
+wm 32 MX7_DDRC_DFIUPD2 0x80100004
+wm 32 MX7_DDRC_RFSHTMG 0x00400046
+wm 32 MX7_DDRC_MP_PCTRL_0 0x00000001
+wm 32 MX7_DDRC_INIT0 0x00020083
+wm 32 MX7_DDRC_INIT1 0x00690000
+wm 32 MX7_DDRC_INIT3 0x09300004
+wm 32 MX7_DDRC_INIT4 0x04080000
+wm 32 MX7_DDRC_INIT5 0x00100004
+wm 32 MX7_DDRC_RANKCTL 0x0000033f
+wm 32 MX7_DDRC_DRAMTMG0 0x09081109
+wm 32 MX7_DDRC_DRAMTMG1 0x0007020d
+wm 32 MX7_DDRC_DRAMTMG2 0x03040407
+wm 32 MX7_DDRC_DRAMTMG3 0x00002006
+wm 32 MX7_DDRC_DRAMTMG4 0x04020205
+wm 32 MX7_DDRC_DRAMTMG5 0x03030202
+wm 32 MX7_DDRC_DRAMTMG8 0x00000803
+wm 32 MX7_DDRC_ZQCTL0 0x00800020
+wm 32 MX7_DDRC_ZQCTL1 0x02000100
+wm 32 MX7_DDRC_DFITMG0 0x02098204
+wm 32 MX7_DDRC_DFITMG1 0x00030303
+wm 32 MX7_DDRC_ADDRMAP0 0x00000016
+wm 32 MX7_DDRC_ADDRMAP1 0x00171717
+wm 32 MX7_DDRC_ADDRMAP5 0x04040404
+wm 32 MX7_DDRC_ADDRMAP6 0x0f040404
+wm 32 MX7_DDRC_ODTCFG 0x06000604
+wm 32 MX7_DDRC_ODTMAP 0x00000001
+
+wm 32 0x30391000 0x00000000
+
+wm 32 MX7_DDR_PHY_PHY_CON0 0x17420f40
+wm 32 MX7_DDR_PHY_PHY_CON1 0x10210100
+wm 32 MX7_DDR_PHY_PHY_CON4 0x00060807
+wm 32 MX7_DDR_PHY_MDLL_CON0 0x1010007e
+wm 32 MX7_DDR_PHY_DRVDS_CON0 0x00000d6e
+wm 32 MX7_DDR_PHY_OFFSET_RD_CON0 0x08080808
+wm 32 MX7_DDR_PHY_OFFSET_WR_CON0 0x08080808
+wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x01000010
+wm 32 MX7_DDR_PHY_CMD_SDLL_CON0 0x00000010
+
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447306
+
+check 32 until_any_bit_set MX7_DDR_PHY_ZQ_CON1 0x1
+
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e447304
+wm 32 MX7_DDR_PHY_ZQ_CON0 0x0e407304
+
+wm 32 0x30384130 0x00000000
+wm 32 0x30340020 0x00000178
+wm 32 0x30384130 0x00000002
+
+wm 32 MX7_DDR_PHY_LP_CON0 0x0000000f
+
+check 32 until_any_bit_set MX7_DDRC_STAT 0x1
-- 
2.17.1


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[PATCH v2 4/6] ARM: i.MX7: bbu: Add MMC boot handler

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/imx-bbu-internal.c |  5 +++++
 arch/arm/mach-imx/include/mach/bbu.h | 10 ++++++++++
 2 files changed, 15 insertions(+)

diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index 799b97361..77e0b86bc 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -624,6 +624,11 @@ int vf610_bbu_internal_mmcboot_register_handler(const char *name,
 						unsigned long flags)
 	__alias(imx_bbu_internal_mmcboot_register_handler);
 
+int imx7_bbu_internal_mmcboot_register_handler(const char *name,
+						const char *devicefile,
+						unsigned long flags)
+	__alias(imx_bbu_internal_mmcboot_register_handler);
+
 /*
  * Register an i.MX53 internal boot update handler for i2c/spi
  * EEPROMs / flashes. Nearly the same as MMC/SD, but we do not need to
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index bc1fc4ba6..1174c21d2 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -59,6 +59,9 @@ int imx51_bbu_internal_mmcboot_register_handler(const char *name, const char *de
 int vf610_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
 						unsigned long flags);
 
+int imx7_bbu_internal_mmcboot_register_handler(const char *name, const char *devicefile,
+						unsigned long flags);
+
 int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
 		unsigned long flags);
 
@@ -134,6 +137,13 @@ static inline int vf610_bbu_internal_mmcboot_register_handler(const char *name,
 	return -ENOSYS;
 }
 
+static inline int imx7_bbu_internal_mmcboot_register_handler(const char *name,
+							     const char *devicefile,
+							     unsigned long flags)
+{
+	return -ENOSYS;
+}
+
 static inline int imx6_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
 		unsigned long flags)
 {
-- 
2.17.1


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[PATCH v2 5/6] ARM: i.MX7: bbu: Add I2C and SPI handler

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/mach-imx/imx-bbu-internal.c |  6 ++++++
 arch/arm/mach-imx/include/mach/bbu.h | 10 ++++++++++
 2 files changed, 16 insertions(+)

diff --git a/arch/arm/mach-imx/imx-bbu-internal.c b/arch/arm/mach-imx/imx-bbu-internal.c
index 77e0b86bc..5f85b13dc 100644
--- a/arch/arm/mach-imx/imx-bbu-internal.c
+++ b/arch/arm/mach-imx/imx-bbu-internal.c
@@ -649,6 +649,12 @@ int vf610_bbu_internal_spi_i2c_register_handler(const char *name,
 						unsigned long flags)
 	__alias(imx6_bbu_internal_spi_i2c_register_handler);
 
+
+int imx7_bbu_internal_spi_i2c_register_handler(const char *name,
+						const char *devicefile,
+						unsigned long flags)
+	__alias(imx6_bbu_internal_spi_i2c_register_handler);
+
 int imx_bbu_external_nor_register_handler(const char *name,
 					  const char *devicefile,
 					  unsigned long flags)
diff --git a/arch/arm/mach-imx/include/mach/bbu.h b/arch/arm/mach-imx/include/mach/bbu.h
index 1174c21d2..c8223c840 100644
--- a/arch/arm/mach-imx/include/mach/bbu.h
+++ b/arch/arm/mach-imx/include/mach/bbu.h
@@ -71,6 +71,9 @@ int vf610_bbu_internal_mmc_register_handler(const char *name, const char *device
 int vf610_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
 						unsigned long flags);
 
+int imx7_bbu_internal_spi_i2c_register_handler(const char *name, const char *devicefile,
+					       unsigned long flags);
+
 int imx8mq_bbu_internal_mmc_register_handler(const char *name, const char *devicefile,
 					     unsigned long flags);
 
@@ -175,6 +178,13 @@ vf610_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
 	return -ENOSYS;
 }
 
+static inline int
+imx7_bbu_internal_spi_i2c_register_handler(const char *name, char *devicefile,
+					   unsigned long flags)
+{
+	return -ENOSYS;
+}
+
 #endif
 
 #if defined(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND)
-- 
2.17.1


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[PATCH v2 6/6] i.MX: Add support for ZII's i.MX7D-based RPU2 board

[Andrey Smirnov]

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/boards/Makefile                      |   1 +
 arch/arm/boards/zii-imx7d-rpu2/Makefile       |   2 +
 arch/arm/boards/zii-imx7d-rpu2/board.c        |  49 ++
 .../flash-header-zii-imx7d-rpu2.imxcfg        |   6 +
 arch/arm/boards/zii-imx7d-rpu2/lowlevel.c     |  50 ++
 arch/arm/dts/Makefile                         |   2 +
 arch/arm/dts/imx7d-zii-rpu2.dts               | 613 ++++++++++++++++++
 arch/arm/mach-imx/Kconfig                     |   4 +
 images/Makefile.imx                           |   5 +
 9 files changed, 732 insertions(+)
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/Makefile
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/board.c
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
 create mode 100644 arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
 create mode 100644 arch/arm/dts/imx7d-zii-rpu2.dts

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index b9bf67f0a..b6766616a 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -156,3 +156,4 @@ obj-$(CONFIG_MACH_ZII_RDU1)			+= zii-imx51-rdu1/
 obj-$(CONFIG_MACH_ZII_RDU2)			+= zii-imx6q-rdu2/
 obj-$(CONFIG_MACH_ZII_RDU3)			+= zii-imx8mq-rdu3/
 obj-$(CONFIG_MACH_ZII_VF610_DEV)		+= zii-vf610-dev/
+obj-$(CONFIG_MACH_ZII_IMX7D_RPU2)		+= zii-imx7d-rpu2/
diff --git a/arch/arm/boards/zii-imx7d-rpu2/Makefile b/arch/arm/boards/zii-imx7d-rpu2/Makefile
new file mode 100644
index 000000000..01c7a259e
--- /dev/null
+++ b/arch/arm/boards/zii-imx7d-rpu2/Makefile
@@ -0,0 +1,2 @@
+obj-y += board.o
+lwl-y += lowlevel.o
diff --git a/arch/arm/boards/zii-imx7d-rpu2/board.c b/arch/arm/boards/zii-imx7d-rpu2/board.c
new file mode 100644
index 000000000..0a99976b7
--- /dev/null
+++ b/arch/arm/boards/zii-imx7d-rpu2/board.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovation
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <gpio.h>
+#include <mach/imx7-regs.h>
+#include <mfd/imx7-iomuxc-gpr.h>
+#include <environment.h>
+#include <envfs.h>
+#include <mach/bbu.h>
+
+static void zii_imx7d_rpu2_init_fec(void)
+{
+	void __iomem *gpr = IOMEM(MX7_IOMUXC_GPR_BASE_ADDR);
+	uint32_t gpr1;
+
+	/*
+	 * Make sure we do not drive ENETn_TX_CLK signal
+	 */
+	gpr1 = readl(gpr + IOMUXC_GPR1);
+	gpr1 &= ~(IMX7D_GPR1_ENET1_TX_CLK_SEL_MASK |
+		  IMX7D_GPR1_ENET1_CLK_DIR_MASK |
+		  IMX7D_GPR1_ENET2_TX_CLK_SEL_MASK |
+		  IMX7D_GPR1_ENET2_CLK_DIR_MASK);
+	writel(gpr1, gpr + IOMUXC_GPR1);
+}
+
+static int zii_imx7d_rpu2_coredevices_init(void)
+{
+	if (!of_machine_is_compatible("zii,imx7d-zii-rpu2"))
+		return 0;
+
+	zii_imx7d_rpu2_init_fec();
+
+	imx7_bbu_internal_spi_i2c_register_handler("SPI", "/dev/m25p0.barebox",
+						   BBU_HANDLER_FLAG_DEFAULT);
+
+	imx7_bbu_internal_mmcboot_register_handler("eMMC", "/dev/mmc2", 0);
+
+	return 0;
+}
+coredevice_initcall(zii_imx7d_rpu2_coredevices_init);
+
diff --git a/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg b/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
new file mode 100644
index 000000000..46f3d9504
--- /dev/null
+++ b/arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
@@ -0,0 +1,6 @@
+soc imx7
+loadaddr 0x80000000
+dcdofs 0x400
+
+#include <mach/flash-header/imx7d-ddr-sabresd.imxcfg>
+
diff --git a/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c b/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
new file mode 100644
index 000000000..1eeab7d21
--- /dev/null
+++ b/arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovation
+ * Author: Andrey Smirnov <andrew.smirnov@gmail.com>
+ */
+
+#include <debug_ll.h>
+#include <io.h>
+#include <common.h>
+#include <linux/sizes.h>
+#include <mach/generic.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/imx7-ccm-regs.h>
+#include <mach/iomux-mx7.h>
+#include <mach/debug_ll.h>
+#include <asm/cache.h>
+#include <mach/esdctl.h>
+
+extern char __dtb_imx7d_zii_rpu2_start[];
+
+static inline void setup_uart(void)
+{
+	void __iomem *iomux = IOMEM(MX7_IOMUXC_BASE_ADDR);
+	void __iomem *ccm   = IOMEM(MX7_CCM_BASE_ADDR);
+
+	writel(CCM_CCGR_SETTINGn_NEEDED(0),
+	       ccm + CCM_CCGRn_CLR(CCM_CCGR_UART2));
+	writel(CCM_TARGET_ROOTn_ENABLE | UART2_CLK_ROOT__OSC_24M,
+	       ccm + CCM_TARGET_ROOTn(UART2_CLK_ROOT));
+	writel(CCM_CCGR_SETTINGn_NEEDED(0),
+	       ccm + CCM_CCGRn_SET(CCM_CCGR_UART2));
+
+	mx7_setup_pad(iomux, MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX);
+
+	imx7_uart_setup_ll();
+
+	putc_ll('>');
+}
+
+ENTRY_FUNCTION(start_zii_imx7d_rpu2, r0, r1, r2)
+{
+	imx7_cpu_lowlevel_init();
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL))
+		setup_uart();
+
+	imx7d_barebox_entry(__dtb_imx7d_zii_rpu2_start + get_runtime_offset());
+}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 2361e0d6f..f8ebb6ca5 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -118,4 +118,6 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
 pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
 pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
 
+pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
+
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/arm/dts/imx7d-zii-rpu2.dts b/arch/arm/dts/imx7d-zii-rpu2.dts
new file mode 100644
index 000000000..6fba73f43
--- /dev/null
+++ b/arch/arm/dts/imx7d-zii-rpu2.dts
@@ -0,0 +1,613 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/*
+ * Copyright (C) 2018 Zodiac Inflight Innovations
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/input/input.h>
+#include <arm/imx7d.dtsi>
+
+#include "imx7d-ddrc.dtsi"
+
+/ {
+	model = "ZII RPU2 Board";
+	compatible = "zii,imx7d-zii-rpu2","fsl,imx7d";
+
+	chosen {
+		stdout-path = &uart2;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-0 = <&pinctrl_leds_debug>;
+		pinctrl-names = "default";
+
+		debug {
+			label = "zii:green:debug1";
+			gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "heartbeat";
+		};
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+		};
+
+		reg_usb_otg2_vbus: regulator@1 {
+			compatible = "regulator-fixed";
+			reg = <1>;
+			regulator-name = "usb_otg2_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+		};
+
+		reg_sd1_vmmc: regulator@3 {
+			compatible = "regulator-fixed";
+			regulator-name = "VDD_SD1";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
+			startup-delay-us = <200000>;
+			enable-active-high;
+		};
+
+		reg_can1_3v3: regulator@4 {
+			compatible = "regulator-fixed";
+			reg = <4>;
+			regulator-name = "can1-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_can2_3v3: regulator@5 {
+			compatible = "regulator-fixed";
+			reg = <5>;
+			regulator-name = "can2-3v3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			gpio = <&gpio1 9 GPIO_ACTIVE_LOW>;
+		};
+
+		reg_vref_1v8: regulator@6 {
+			compatible = "regulator-fixed";
+			reg = <6>;
+			regulator-name = "vref-1v8";
+			regulator-min-microvolt = <1800000>;
+			regulator-max-microvolt = <1800000>;
+		};
+
+		wlreg_on: fixedregulator@100 {
+			compatible = "regulator-fixed";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-name = "wlreg_on";
+			gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>;
+			startup-delay-us = <100>;
+			enable-active-high;
+		};
+
+		reg_3p3v: regulator-3p3v {
+			compatible = "regulator-fixed";
+			regulator-name = "GEN_3V3";
+			regulator-min-microvolt = <3300000>;
+			regulator-max-microvolt = <3300000>;
+			regulator-always-on;
+		};
+
+		reg_5p0v_main: regulator-5p0v-main {
+			compatible = "regulator-fixed";
+			regulator-name = "5V_MAIN";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			regulator-always-on;
+		};
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&adc2 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+&cpu0 {
+	arm-supply = <&sw1a_reg>;
+};
+
+&clks {
+	assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>;
+	assigned-clock-rates = <884736000>;
+};
+
+&ecspi1 {
+	fsl,spi-num-chipselects = <1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_ecspi1>;
+	status = "okay";
+
+	cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
+
+	nor_flash: nor-flash@0 {
+		compatible = "jedec,spi-nor";
+		spi-max-frequency = <20000000>;
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		partition@0 {
+			label = "barebox";
+			reg = <0x0 0xc0000>;
+		};
+
+		partition@c0000 {
+			label = "barebox-environment";
+			reg = <0xc0000 0x40000>;
+		};
+	};
+};
+
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet1>;
+	assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&port_fec1>;
+	status = "okay";
+
+	mdio1: mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		switch0: switch0@0 {
+			compatible = "marvell,mv88e6085";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0>;
+			eeprom-length = <512>;
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				port@0 {
+					reg = <0>;
+					label = "eth_cu_1000_1";
+				};
+				port@1 {
+					reg = <1>;
+					label = "eth_cu_1000_2";
+				};
+
+				port@2 {
+					reg = <2>;
+					label = "pic";
+
+					fixed-link {
+						speed = <100>;
+						full-duplex;
+					};
+				};
+
+				port_fec1: port@5 {
+					reg = <5>;
+					label = "cpu";
+					ethernet = <&fec1>;
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+
+				port_fec2: port@6 {
+					reg = <6>;
+					label = "data";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+				};
+			};
+		};
+	};
+};
+
+&fec2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet2>;
+	assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>,
+			  <&clks IMX7D_ENET2_TIME_ROOT_CLK>;
+	assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+	assigned-clock-rates = <0>, <100000000>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&port_fec1>;
+	fsl,magic-packet;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c1>;
+	pinctrl-1 = <&pinctrl_i2c1_gpio>;
+	scl-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	nameplate_eeprom: at24c04@50 {
+		compatible = "atmel,24c04";
+		#address-cells=<1>;
+		#size-cells=<1>;
+		reg = <0x50>;
+	};
+
+	sandbox_eeprom: at24c04@52 {
+		compatible = "atmel,24c04";
+		reg = <0x52>;
+	};
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&i2c3 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	pfuze3000@08 {
+		compatible = "fsl,pfuze3000";
+		reg = <0x08>;
+
+		regulators {
+			sw1a_reg: sw1a {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw1c_reg: sw1b {
+				regulator-min-microvolt = <700000>;
+				regulator-max-microvolt = <1475000>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <6250>;
+			};
+
+			sw2_reg: sw2 {
+				regulator-min-microvolt = <1500000>;
+				regulator-max-microvolt = <1850000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			sw3a_reg: sw3 {
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <1650000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			swbst_reg: swbst {
+				regulator-min-microvolt = <5000000>;
+				regulator-max-microvolt = <5150000>;
+			};
+
+			snvs_reg: vsnvs {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vref_reg: vrefddr {
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vgen1_reg: vldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen2_reg: vldo2 {
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <1550000>;
+				regulator-always-on;
+			};
+
+			vgen3_reg: vccsd {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen4_reg: v33 {
+				regulator-min-microvolt = <2850000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen5_reg: vldo3 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+
+			vgen6_reg: vldo4 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+&sdma {
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart2>;
+	assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart4>;
+	assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>;
+	assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>;
+	status = "okay";
+
+	rave-sp {
+		compatible = "zii,rave-sp-rdu2";
+		current-speed = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		watchdog {
+			compatible = "zii,rave-sp-watchdog";
+			nvmem-cells = <&boot_source>;
+			nvmem-cell-names = "boot-source";
+		};
+
+		eeprom@a3 {
+			compatible = "zii,rave-sp-eeprom";
+			reg = <0xa3 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			zii,eeprom-name = "main-eeprom";
+
+			boot_source: boot-source@83 {
+				reg = <0x83 1>;
+			};
+		};
+	};
+};
+
+&usbotg1 {
+	vbus-supply = <&reg_usb_otg1_vbus>;
+	srp-disable;
+	hnp-disable;
+	adp-disable;
+	status = "okay";
+};
+
+&usbotg2 {
+	vbus-supply = <&reg_usb_otg2_vbus>;
+	dr_mode = "host";
+	status = "okay";
+};
+
+&usdhc1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	keep-power-in-suspend;
+	bus-width = <4>;
+	no-1-8-v;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <8>;
+	non-removable;
+	no-1-8-v;
+	keep-power-in-suspend;
+	status = "okay";
+};
+
+&wdog1 {
+	fsl,wdog_b;
+};
+
+
+&iomuxc {
+	pinctrl_leds_debug: debuggrp {
+		fsl,pins = <
+		MX7D_PAD_EPDC_DATA08__GPIO2_IO8		0x59 /* HB_LED */
+		>;
+	};
+
+	pinctrl_enet1: enet1grp {
+		fsl,pins = <
+		MX7D_PAD_SD2_CD_B__ENET1_MDIO                           0x3
+		MX7D_PAD_SD2_WP__ENET1_MDC                              0x3
+		MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC               0x1
+		MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0               0x1
+		MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1               0x1
+		MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2               0x1
+		MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3               0x1
+		MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL         0x1
+		MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC               0x1
+		MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0               0x1
+		MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1               0x1
+		MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2               0x1
+		MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3               0x1
+		MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL         0x1
+		>;
+	};
+
+	pinctrl_enet2: enet2grp {
+		fsl,pins = <
+		MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC                     0x1
+		MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0                    0x1
+		MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1                    0x1
+		MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2                    0x1
+		MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3                     0x1
+		MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL                  0x1
+		MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC                    0x1
+		MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0                    0x1
+		MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1                     0x1
+		MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2                     0x1
+		MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3                    0x1
+		MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL                 0x1
+		MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT           0x1
+		>;
+	};
+
+	pinctrl_i2c1: i2c1grp {
+		fsl,pins = <
+		MX7D_PAD_I2C1_SDA__I2C1_SDA             0x4000007f
+		MX7D_PAD_I2C1_SCL__I2C1_SCL             0x4000007f
+		>;
+	};
+
+	pinctrl_i2c1_gpio: i2c1gpiogrp {
+		fsl,pins = <
+		MX7D_PAD_I2C1_SDA__GPIO4_IO9            0x4000007f
+		MX7D_PAD_I2C1_SCL__GPIO4_IO8            0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+		MX7D_PAD_I2C2_SDA__I2C2_SDA             0x4000007f
+		MX7D_PAD_I2C2_SCL__I2C2_SCL             0x4000007f
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2gpiogrp {
+		fsl,pins = <
+		MX7D_PAD_I2C2_SDA__GPIO4_IO11           0x4000007f
+		MX7D_PAD_I2C2_SCL__GPIO4_IO10           0x4000007f
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+		MX7D_PAD_I2C3_SDA__I2C3_SDA             0x4000007f
+		MX7D_PAD_I2C3_SCL__I2C3_SCL             0x4000007f
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+		MX7D_PAD_I2C3_SDA__GPIO4_IO13           0x4000007f
+		MX7D_PAD_I2C3_SCL__GPIO4_IO12           0x4000007f
+		>;
+	};
+
+	pinctrl_i2c4: i2c4grp {
+		fsl,pins = <
+		MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA         0x4000007f
+		MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL         0x4000007f
+		>;
+	};
+
+	pinctrl_i2c4_gpio: i2c4gpiogrp {
+		fsl,pins = <
+		MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17       0x4000007f
+		MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16       0x4000007f
+		>;
+	};
+
+	pinctrl_ecspi1: ecspi1grp {
+		fsl,pins = <
+		MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK       0x2
+		MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI       0x2
+		MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO       0x2
+		MX7D_PAD_ECSPI1_SS0__GPIO4_IO19         0x59
+		>;
+	};
+
+	pinctrl_uart2: uart2grp {
+		fsl,pins = <
+		MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX    0x79
+		MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX    0x79
+		>;
+	};
+
+	pinctrl_uart4: uart4grp {
+		fsl,pins = <
+		MX7D_PAD_SD2_DATA0__UART4_DCE_RX        0x79
+		MX7D_PAD_SD2_DATA1__UART4_DCE_TX        0x79
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+		MX7D_PAD_SD1_CMD__SD1_CMD               0x59
+		MX7D_PAD_SD1_CLK__SD1_CLK               0x19
+		MX7D_PAD_SD1_DATA0__SD1_DATA0           0x59
+		MX7D_PAD_SD1_DATA1__SD1_DATA1           0x59
+		MX7D_PAD_SD1_DATA2__SD1_DATA2           0x59
+		MX7D_PAD_SD1_DATA3__SD1_DATA3           0x59
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+		MX7D_PAD_SD3_CMD__SD3_CMD               0x59
+		MX7D_PAD_SD3_CLK__SD3_CLK               0x19
+		MX7D_PAD_SD3_DATA0__SD3_DATA0           0x59
+		MX7D_PAD_SD3_DATA1__SD3_DATA1           0x59
+		MX7D_PAD_SD3_DATA2__SD3_DATA2           0x59
+		MX7D_PAD_SD3_DATA3__SD3_DATA3           0x59
+		MX7D_PAD_SD3_DATA4__SD3_DATA4           0x59
+		MX7D_PAD_SD3_DATA5__SD3_DATA5           0x59
+		MX7D_PAD_SD3_DATA6__SD3_DATA6           0x59
+		MX7D_PAD_SD3_DATA7__SD3_DATA7           0x59
+		MX7D_PAD_SD3_RESET_B__SD3_RESET_B       0x59
+		>;
+	};
+};
+
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 535c08e47..4a56fb9f4 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -435,6 +435,10 @@ config MACH_ZII_VF610_DEV
 	select ARCH_VF610
 	select CLKDEV_LOOKUP
 
+config MACH_ZII_IMX7D_RPU2
+	bool "ZII i.MX7D RPU2"
+	select ARCH_IMX7
+
 config MACH_PHYTEC_PHYCORE_IMX7
 	bool "Phytec phyCORE i.MX7"
 	select ARCH_IMX7
diff --git a/images/Makefile.imx b/images/Makefile.imx
index eb3ed492e..e91976996 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -532,6 +532,11 @@ CFG_start_imx7d_sabresd.pblx.imximg = $(board)/freescale-mx7-sabresd/flash-heade
 FILE_barebox-freescale-mx7-sabresd.img = start_imx7d_sabresd.pblx.imximg
 image-$(CONFIG_MACH_FREESCALE_MX7_SABRESD) += barebox-freescale-mx7-sabresd.img
 
+pblx-$(CONFIG_MACH_ZII_IMX7D_RPU2) += start_zii_imx7d_rpu2
+CFG_start_zii_imx7d_rpu2.pblx.imximg = $(board)/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
+FILE_barebox-zii-imx7d-rpu2.img = start_zii_imx7d_rpu2.pblx.imximg
+image-$(CONFIG_MACH_ZII_IMX7D_RPU2) += barebox-zii-imx7d-rpu2.img
+
 # ----------------------- i.MX8mq based boards --------------------------
 pblx-$(CONFIG_MACH_NXP_IMX8MQ_EVK) += start_nxp_imx8mq_evk
 CFG_start_nxp_imx8mq_evk.imx-sram-img = $(board)/nxp-imx8mq-evk/flash-header-imx8mq-evk.imxcfg
-- 
2.17.1


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Re: [PATCH v2 0/6] ZII RPU2 i.MX7D board support

[Sascha Hauer]

On Sun, Oct 07, 2018 at 11:34:03PM -0700, Andrey Smirnov wrote:
> Everyone:
> 
> This series is a number of small patches I developed while adding
> support for ZII's RPU2 board. Hopefully all of them are self-explanatory.
> 
> Feedback is welcome!
> 
> Changes since [v1]:
> 
>     - Renamed flash-header-mx7-default.imxcfg to flash-header-mx7-sabresd.imxcfg
> 
> Thanks,
> Andrey Smirnov
> 
> [v1] http://lists.infradead.org/pipermail/barebox/2018-September/034845.html
> 
> Andrey Smirnov (6):
>   ARM: i.MX: esdctl: Add memory size detection for i.MX7D
>   ARM: freescale-mx7-sabresd: Make use of imx7d_barebox_entry()
>   i.MX7D: DCD: Create shared DDR configuration header
>   ARM: i.MX7: bbu: Add MMC boot handler
>   ARM: i.MX7: bbu: Add I2C and SPI handler
>   i.MX: Add support for ZII's i.MX7D-based RPU2 board

Applied, thanks

Sascha

> 
>  arch/arm/boards/Makefile                      |   1 +
>  .../flash-header-mx7-sabresd.imxcfg           |  79 +--
>  .../boards/freescale-mx7-sabresd/lowlevel.c   |   7 +-
>  arch/arm/boards/zii-imx7d-rpu2/Makefile       |   2 +
>  arch/arm/boards/zii-imx7d-rpu2/board.c        |  49 ++
>  .../flash-header-zii-imx7d-rpu2.imxcfg        |   6 +
>  arch/arm/boards/zii-imx7d-rpu2/lowlevel.c     |  50 ++
>  arch/arm/dts/Makefile                         |   2 +
>  arch/arm/dts/imx7d-ddrc.dtsi                  |  15 +
>  arch/arm/dts/imx7d-zii-rpu2.dts               | 613 ++++++++++++++++++
>  arch/arm/mach-imx/Kconfig                     |   4 +
>  arch/arm/mach-imx/esdctl.c                    |  61 ++
>  arch/arm/mach-imx/imx-bbu-internal.c          |  11 +
>  arch/arm/mach-imx/include/mach/bbu.h          |  20 +
>  arch/arm/mach-imx/include/mach/esdctl.h       |   1 +
>  .../flash-header/imx7d-ddr-sabresd.imxcfg     |  78 +++
>  arch/arm/mach-imx/include/mach/imx7-regs.h    |   2 +
>  images/Makefile.imx                           |   5 +
>  18 files changed, 923 insertions(+), 83 deletions(-)
>  create mode 100644 arch/arm/boards/zii-imx7d-rpu2/Makefile
>  create mode 100644 arch/arm/boards/zii-imx7d-rpu2/board.c
>  create mode 100644 arch/arm/boards/zii-imx7d-rpu2/flash-header-zii-imx7d-rpu2.imxcfg
>  create mode 100644 arch/arm/boards/zii-imx7d-rpu2/lowlevel.c
>  create mode 100644 arch/arm/dts/imx7d-ddrc.dtsi
>  create mode 100644 arch/arm/dts/imx7d-zii-rpu2.dts
>  create mode 100644 arch/arm/mach-imx/include/mach/flash-header/imx7d-ddr-sabresd.imxcfg
> 
> -- 
> 2.17.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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