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From: Lucas Stach <l.stach@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH v4 03/11] ARM: safely switch from HYP to SVC mode if required
Date: Thu,  1 Nov 2018 10:18:38 +0100	[thread overview]
Message-ID: <20181101091846.10882-3-l.stach@pengutronix.de> (raw)
In-Reply-To: <20181101091846.10882-1-l.stach@pengutronix.de>

This is a port of the Linux safe_svcmode_maskall macro to
the Barebox lowlevel init.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Tested-by: Roland Hieber <r.hieber@pengutronix.de>
---
v3: fix whitespace
---
 arch/arm/cpu/lowlevel.S       | 18 +++++++++++++++---
 arch/arm/include/asm/system.h | 26 ++++++++++++++++++++++++++
 2 files changed, 41 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/lowlevel.S b/arch/arm/cpu/lowlevel.S
index 7696a198e764..43665981e48b 100644
--- a/arch/arm/cpu/lowlevel.S
+++ b/arch/arm/cpu/lowlevel.S
@@ -1,16 +1,28 @@
 #include <linux/linkage.h>
 #include <init.h>
 #include <asm/system.h>
+#include <asm/opcodes-virt.h>
 
 .section ".text_bare_init_","ax"
 ENTRY(arm_cpu_lowlevel_init)
 	/* save lr, since it may be banked away with a processor mode change */
 	mov	r2, lr
+
 	/* set the cpu to SVC32 mode, mask irq and fiq */
 	mrs	r12, cpsr
-	bic	r12, r12, #0x1f
-	orr	r12, r12, #0xd3
-	msr	cpsr, r12
+	eor	r12, r12, #HYP_MODE
+	tst	r12, #MODE_MASK
+	bic	r12, r12, #MODE_MASK
+	orr	r12, r12, #(PSR_I_BIT | PSR_F_BIT | SVC_MODE)
+THUMB(	orr	r12, r12, #PSR_T_BIT	)
+	bne	1f
+	orr	r12, r12, #PSR_A_BIT
+	adr	lr, 2f
+	msr	spsr_cxsf, r12
+	__MSR_ELR_HYP(14)
+	__ERET
+1:	msr	cpsr_c, r12
+2:
 
 #if __LINUX_ARM_ARCH__ >= 6
 	/*
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5cf828ea36cb..48242ab473f4 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -60,6 +60,32 @@
 #define CR_AFE  (1 << 29)	/* Access flag enable			*/
 #define CR_TE   (1 << 30)	/* Thumb exception enable		*/
 
+/*
+ * PSR bits
+ */
+#define USR_MODE	0x00000010
+#define FIQ_MODE	0x00000011
+#define IRQ_MODE	0x00000012
+#define SVC_MODE	0x00000013
+#define ABT_MODE	0x00000017
+#define HYP_MODE	0x0000001a
+#define UND_MODE	0x0000001b
+#define SYSTEM_MODE	0x0000001f
+#define MODE32_BIT	0x00000010
+#define MODE_MASK	0x0000001f
+
+#define PSR_T_BIT	0x00000020
+#define PSR_F_BIT	0x00000040
+#define PSR_I_BIT	0x00000080
+#define PSR_A_BIT	0x00000100
+#define PSR_E_BIT	0x00000200
+#define PSR_J_BIT	0x01000000
+#define PSR_Q_BIT	0x08000000
+#define PSR_V_BIT	0x10000000
+#define PSR_C_BIT	0x20000000
+#define PSR_Z_BIT	0x40000000
+#define PSR_N_BIT	0x80000000
+
 #ifndef __ASSEMBLY__
 #if __LINUX_ARM_ARCH__ >= 7
 static inline unsigned int current_el(void)
-- 
2.19.1


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  parent reply	other threads:[~2018-11-01  9:19 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-01  9:18 [PATCH v4 01/11] ARM: pass architecture flag for SMCC also to PBL compilation unit Lucas Stach
2018-11-01  9:18 ` [PATCH v4 02/11] ARM: import opcode helpers from Linux kernel Lucas Stach
2018-11-01  9:18 ` Lucas Stach [this message]
2018-11-01  9:18 ` [PATCH v4 04/11] ARM: allow secure monitor code to be built without PSCI Lucas Stach
2018-11-02 22:27   ` Sam Ravnborg
2018-11-03  0:04     ` Andrey Smirnov
2018-11-03  7:56       ` Sam Ravnborg
2018-11-01  9:18 ` [PATCH v4 05/11] ARM: add file for HYP mode related setup Lucas Stach
2018-11-01  9:18 ` [PATCH v4 06/11] ARM: don't try to install secure monitor when entered in HYP mode Lucas Stach
2018-11-01  9:18 ` [PATCH v4 07/11] ARM: default to starting kernel in HYP mode when entered in HYP Lucas Stach
2018-11-01  9:18 ` [PATCH v4 08/11] ARM: install HYP vectors at PBL and Barebox entry Lucas Stach
2018-11-01  9:18 ` [PATCH v4 09/11] ARM: rpi: add revision IDs for Pi 3 Model B and Pi Zero Lucas Stach
2018-11-01 18:35   ` Lucas Stach
2018-11-02  6:26     ` Sascha Hauer
2018-11-01  9:18 ` [PATCH v4 10/11] ARM: rpi: add raspberry pi 3 support Lucas Stach
2018-11-01  9:18 ` [PATCH v4 11/11] ARM: rpi: autosize malloc area Lucas Stach

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