* [PATCH] arm: at91: fix sdram controller init
@ 2018-11-05 7:28 Sascha Hauer
2018-11-05 13:56 ` Sam Ravnborg
0 siblings, 1 reply; 2+ messages in thread
From: Sascha Hauer @ 2018-11-05 7:28 UTC (permalink / raw)
To: Barebox List; +Cc: Ahmad Fatoum, Sam Ravnborg
From: Ahmad Fatoum <a.fatoum@pengutronix.de>
e739663535 confused parameters to __raw_writel. The value and the base
address was mixed up.
Fixes: e739663535 (arm: at91: code cleanup in at91sam926x_board_init)
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../include/mach/at91sam926x_board_init.h | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 70ae903374..7cacc0c8d7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -82,38 +82,38 @@ static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg
return;
/* SDRAMC_MR : Normal Mode */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL);
+ __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
/* SDRAMC_TR - Refresh Timer register */
- __raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr1);
+ __raw_writel(cfg->sdrc_tr1, cfg->sdramc + AT91_SDRAMC_TR);
/* SDRAMC_CR - Configuration register*/
- __raw_writel(AT91_SDRAMC_CR, cfg->sdramc + cfg->sdrc_cr);
+ __raw_writel(cfg->sdrc_cr, cfg->sdramc + AT91_SDRAMC_CR);
/* Memory Device Type */
- __raw_writel(AT91_SDRAMC_MDR, cfg->sdramc + cfg->sdrc_mdr);
+ __raw_writel(cfg->sdrc_mdr, cfg->sdramc + AT91_SDRAMC_MDR);
/* SDRAMC_MR : Precharge All */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_PRECHARGE);
+ __raw_writel(AT91_SDRAMC_MODE_PRECHARGE, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_MR : refresh */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_REFRESH);
+ __raw_writel(AT91_SDRAMC_MODE_REFRESH, cfg->sdramc + AT91_SDRAMC_MR);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRAMC_MR : Load Mode Register */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_LMR);
+ __raw_writel(AT91_SDRAMC_MODE_LMR, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_MR : Normal Mode */
- __raw_writel(AT91_SDRAMC_MR, cfg->sdramc + AT91_SDRAMC_MODE_NORMAL);
+ __raw_writel(AT91_SDRAMC_MODE_NORMAL, cfg->sdramc + AT91_SDRAMC_MR);
access_sdram();
/* SDRAMC_TR : Refresh Timer Counter */
- __raw_writel(AT91_SDRAMC_TR, cfg->sdramc + cfg->sdrc_tr2);
+ __raw_writel(cfg->sdrc_tr2, cfg->sdramc + AT91_SDRAMC_TR);
access_sdram();
}
--
2.19.1
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2018-11-05 7:28 [PATCH] arm: at91: fix sdram controller init Sascha Hauer
2018-11-05 13:56 ` Sam Ravnborg
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