* [PATCH 00/22] AT91 header cleanup
@ 2018-11-05 15:50 Sascha Hauer
2018-11-05 15:50 ` [PATCH 01/22] ARM: at91: remove unused AT_DMA_ID_ defines Sascha Hauer
` (23 more replies)
0 siblings, 24 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
The following series contains a bigger at91 header file cleanup. With
this the SoC header files become completely SoC namespaced which means
they can all be included as desired without conflicts. This makes the
way free for more at91 multiboard support.
I don't have that much AT91 hardware on my desk, so I am unable to test
this properly. Testing feedback very much appreciated. Sam maybe?
Sascha
Sascha Hauer (22):
ARM: at91: remove unused AT_DMA_ID_ defines
ARM: at91: remove unused CONSISTENT_DMA_SIZE defines
ARM: at91rm9200ek: Use SoC specific defines
ARM: at91sam926x: Add header for at91sam926x common base addresses
ARM: at91: remove unused defines
ARM: at91: drop AT91_NB_USART
ARM: at91: remove AT91_SDRAM_BASE
ARM: at91: consolidate phy reset functions
ARM: at91: remove common matrix header file
ARM: at91: Add SoC namespace to matrix defines
ARM: at91: Use SoC specific base addresses where appropriate
ARM: at91rm9200: Add SoC namespace to memory controller defines
ARM: at91: remove unused header file
ARM: at91rm9200 timer: remove unused include
ARM: at91rm9200 timer: Make system timer defines SoC specific
ARM: at91: remove mach/io.h
ARM: at91sam926x use writel rather than pmc accessor function
ARM: at91rm9200ek: use plain readl/writel for pmc accesses
ARM: at91: drop at91_pmc_write()/at91_pmc_read()
ARM: at91: make at91sam926x_board_init board specific
ARM: at91: separate restart handler registration into SoC specific
code
ARM: at91: remove unused defines
arch/arm/boards/animeo_ip/init.c | 23 +-
arch/arm/boards/at91rm9200ek/config.h | 26 +-
arch/arm/boards/at91rm9200ek/init.c | 1 -
arch/arm/boards/at91rm9200ek/lowlevel.c | 44 +--
arch/arm/boards/at91sam9260ek/init.c | 22 +-
arch/arm/boards/at91sam9261ek/init.c | 1 -
arch/arm/boards/at91sam9261ek/lowlevel_init.c | 6 +-
arch/arm/boards/at91sam9263ek/init.c | 1 -
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 8 +-
arch/arm/boards/at91sam9263ek/of_init.c | 8 +-
arch/arm/boards/at91sam9m10g45ek/init.c | 1 -
arch/arm/boards/at91sam9m10ihd/init.c | 1 -
arch/arm/boards/at91sam9n12ek/init.c | 1 -
arch/arm/boards/at91sam9x5ek/init.c | 17 +-
arch/arm/boards/dss11/init.c | 23 +-
arch/arm/boards/haba-knx/init.c | 24 +-
arch/arm/boards/pm9261/init.c | 1 -
arch/arm/boards/pm9261/lowlevel_init.c | 8 +-
arch/arm/boards/pm9263/init.c | 1 -
arch/arm/boards/pm9263/lowlevel_init.c | 8 +-
arch/arm/boards/pm9g45/init.c | 1 -
arch/arm/boards/qil-a926x/init.c | 23 +-
arch/arm/boards/sama5d3_xplained/init.c | 1 -
arch/arm/boards/sama5d3xek/init.c | 1 -
arch/arm/boards/telit-evk-pro3/init.c | 22 +-
arch/arm/boards/tny-a926x/init.c | 1 -
.../arm/boards/tny-a926x/tny_a9263_lowlevel.c | 8 +-
arch/arm/boards/usb-a926x/init.c | 25 +-
.../arm/boards/usb-a926x/usb_a9263_lowlevel.c | 8 +-
arch/arm/mach-at91/Kconfig | 14 -
arch/arm/mach-at91/Makefile | 6 +-
arch/arm/mach-at91/at91rm9200_devices.c | 21 +-
arch/arm/mach-at91/at91rm9200_time.c | 17 +-
arch/arm/mach-at91/at91sam9260.c | 11 +
arch/arm/mach-at91/at91sam9260_devices.c | 12 +-
arch/arm/mach-at91/at91sam9261.c | 11 +
arch/arm/mach-at91/at91sam9261_devices.c | 8 +-
arch/arm/mach-at91/at91sam9263.c | 11 +
arch/arm/mach-at91/at91sam9263_devices.c | 12 +-
arch/arm/mach-at91/at91sam9_reset.S | 12 +-
arch/arm/mach-at91/at91sam9g45.c | 12 +-
arch/arm/mach-at91/at91sam9g45_devices.c | 12 +-
arch/arm/mach-at91/at91sam9g45_reset.S | 12 +-
arch/arm/mach-at91/at91sam9n12.c | 12 +-
arch/arm/mach-at91/at91sam9n12_devices.c | 23 +-
arch/arm/mach-at91/at91sam9x5.c | 20 ++
arch/arm/mach-at91/at91sam9x5_devices.c | 16 +-
arch/arm/mach-at91/clock.c | 22 +-
arch/arm/mach-at91/include/mach/at91_pmc.h | 6 -
arch/arm/mach-at91/include/mach/at91_rstc.h | 6 +-
arch/arm/mach-at91/include/mach/at91_st.h | 49 ----
arch/arm/mach-at91/include/mach/at91_tc.h | 146 ---------
arch/arm/mach-at91/include/mach/at91rm9200.h | 39 +--
.../mach-at91/include/mach/at91rm9200_mc.h | 277 +++++++++---------
.../mach-at91/include/mach/at91rm9200_st.h | 49 ++++
arch/arm/mach-at91/include/mach/at91sam9260.h | 44 ---
.../include/mach/at91sam9260_matrix.h | 114 +++----
arch/arm/mach-at91/include/mach/at91sam9261.h | 30 --
.../include/mach/at91sam9261_matrix.h | 82 +++---
arch/arm/mach-at91/include/mach/at91sam9263.h | 40 ---
.../include/mach/at91sam9263_matrix.h | 208 ++++++-------
arch/arm/mach-at91/include/mach/at91sam926x.h | 8 +
.../include/mach/at91sam926x_board_init.h | 65 ++--
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 6 +-
.../mach-at91/include/mach/at91sam9_matrix.h | 30 --
.../mach-at91/include/mach/at91sam9_sdramc.h | 5 +-
.../arm/mach-at91/include/mach/at91sam9_smc.h | 6 -
arch/arm/mach-at91/include/mach/at91sam9g45.h | 56 ----
.../include/mach/at91sam9g45_matrix.h | 246 ++++++++--------
arch/arm/mach-at91/include/mach/at91sam9n12.h | 67 -----
.../include/mach/at91sam9n12_matrix.h | 146 ++++-----
arch/arm/mach-at91/include/mach/at91sam9x5.h | 74 +----
.../include/mach/at91sam9x5_matrix.h | 228 +++++++-------
arch/arm/mach-at91/include/mach/board.h | 9 +-
arch/arm/mach-at91/include/mach/hardware.h | 7 -
arch/arm/mach-at91/include/mach/io.h | 38 ---
arch/arm/mach-at91/include/mach/sama5d3.h | 44 +--
arch/arm/mach-at91/include/mach/sama5d4.h | 10 +-
arch/arm/mach-at91/sam9_smc.c | 1 -
arch/arm/mach-at91/sama5d3.c | 12 +-
arch/arm/mach-at91/sama5d3_devices.c | 1 -
arch/arm/mach-at91/sama5d4.c | 12 +-
arch/arm/mach-at91/sama5d4_devices.c | 1 -
arch/arm/mach-at91/setup.c | 33 ++-
drivers/clocksource/timer-atmel-pit.c | 1 -
drivers/spi/atmel_spi.c | 1 -
drivers/usb/gadget/at91_udc.c | 21 +-
drivers/video/atmel_hlcdfb.c | 1 -
drivers/video/atmel_lcdfb.c | 1 -
89 files changed, 1082 insertions(+), 1717 deletions(-)
create mode 100644 arch/arm/mach-at91/at91sam9x5.c
delete mode 100644 arch/arm/mach-at91/include/mach/at91_st.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91_tc.h
create mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_st.h
create mode 100644 arch/arm/mach-at91/include/mach/at91sam926x.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9_matrix.h
delete mode 100644 arch/arm/mach-at91/include/mach/io.h
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 01/22] ARM: at91: remove unused AT_DMA_ID_ defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 02/22] ARM: at91: remove unused CONSISTENT_DMA_SIZE defines Sascha Hauer
` (22 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
The defines are unused and not properly namespaced, so remove them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91sam9g45.h | 17 --------
arch/arm/mach-at91/include/mach/at91sam9n12.h | 34 ---------------
arch/arm/mach-at91/include/mach/at91sam9x5.h | 41 -------------------
arch/arm/mach-at91/include/mach/sama5d3.h | 28 -------------
4 files changed, 120 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index ff12ce458a..591ea9fedd 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -155,23 +155,6 @@
#define CONSISTENT_DMA_SIZE SZ_4M
-/*
- * DMA peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI0 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_SPI1_TX 3
-#define AT_DMA_ID_SPI1_RX 4
-#define AT_DMA_ID_SSC0_TX 5
-#define AT_DMA_ID_SSC0_RX 6
-#define AT_DMA_ID_SSC1_TX 7
-#define AT_DMA_ID_SSC1_RX 8
-#define AT_DMA_ID_AC97_TX 9
-#define AT_DMA_ID_AC97_RX 10
-#define AT_DMA_ID_MCI1 13
-
/*
* Cpu Name
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 249bde466b..5693402935 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -147,38 +147,4 @@
#define CONSISTENT_DMA_SIZE (14 * SZ_1M)
-/*
- * DMA0 peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_SPI1_TX 3
-#define AT_DMA_ID_SPI1_RX 4
-#define AT_DMA_ID_USART0_TX 5
-#define AT_DMA_ID_USART0_RX 6
-#define AT_DMA_ID_USART1_TX 7
-#define AT_DMA_ID_USART1_RX 8
-#define AT_DMA_ID_USART2_TX 9
-#define AT_DMA_ID_USART2_RX 10
-#define AT_DMA_ID_USART3_TX 11
-#define AT_DMA_ID_USART3_RX 12
-#define AT_DMA_ID_TWI0_TX 13
-#define AT_DMA_ID_TWI0_RX 14
-#define AT_DMA_ID_TWI1_TX 15
-#define AT_DMA_ID_TWI1_RX 16
-#define AT_DMA_ID_UART0_TX 17
-#define AT_DMA_ID_UART0_RX 18
-#define AT_DMA_ID_UART1_TX 19
-#define AT_DMA_ID_UART1_RX 20
-#define AT_DMA_ID_SSC_TX 21
-#define AT_DMA_ID_SSC_RX 22
-#define AT_DMA_ID_ADC_RX 23
-#define AT_DMA_ID_DBGU_TX 24
-#define AT_DMA_ID_DBGU_RX 25
-#define AT_DMA_ID_AES_TX 26
-#define AT_DMA_ID_AES_RX 27
-#define AT_DMA_ID_SHA_RX 28
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index e23057736e..47f88fb15c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -154,45 +154,4 @@
#define CONSISTENT_DMA_SIZE SZ_4M
-/*
- * DMA0 peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI0 0
-#define AT_DMA_ID_SPI0_TX 1
-#define AT_DMA_ID_SPI0_RX 2
-#define AT_DMA_ID_USART0_TX 3
-#define AT_DMA_ID_USART0_RX 4
-#define AT_DMA_ID_USART1_TX 5
-#define AT_DMA_ID_USART1_RX 6
-#define AT_DMA_ID_TWI0_TX 7
-#define AT_DMA_ID_TWI0_RX 8
-#define AT_DMA_ID_TWI2_TX 9
-#define AT_DMA_ID_TWI2_RX 10
-#define AT_DMA_ID_UART0_TX 11
-#define AT_DMA_ID_UART0_RX 12
-#define AT_DMA_ID_SSC_TX 13
-#define AT_DMA_ID_SSC_RX 14
-
-/*
- * DMA1 peripheral identifiers
- * for hardware handshaking interface
- */
-#define AT_DMA_ID_MCI1 0
-#define AT_DMA_ID_SPI1_TX 1
-#define AT_DMA_ID_SPI1_RX 2
-#define AT_DMA_ID_SMD_TX 3
-#define AT_DMA_ID_SMD_RX 4
-#define AT_DMA_ID_TWI1_TX 5
-#define AT_DMA_ID_TWI1_RX 6
-#define AT_DMA_ID_ADC_RX 7
-#define AT_DMA_ID_DBGU_TX 8
-#define AT_DMA_ID_DBGU_RX 9
-#define AT_DMA_ID_UART1_TX 10
-#define AT_DMA_ID_UART1_RX 11
-#define AT_DMA_ID_USART2_TX 12
-#define AT_DMA_ID_USART2_RX 13
-#define AT_DMA_ID_USART3_TX 14
-#define AT_DMA_ID_USART3_RX 15
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index e98b101ee0..d53bcaee1a 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -123,32 +123,4 @@
#define SAMA5D3_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */
#define SAMA5D3_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */
-/*
- * DMA0 peripheral identifiers
- * for hardware handshaking interface
- */
-#define SAMA5_DMA_ID_MCI0 0
-#define SAMA5_DMA_ID_SPI0_TX 1
-#define SAMA5_DMA_ID_SPI0_RX 2
-#define SAMA5_DMA_ID_USART0_TX 3
-#define SAMA5_DMA_ID_USART0_RX 4
-#define SAMA5_DMA_ID_USART1_TX 5
-#define SAMA5_DMA_ID_USART1_RX 6
-#define SAMA5_DMA_ID_TWI0_TX 7
-#define SAMA5_DMA_ID_TWI0_RX 8
-#define SAMA5_DMA_ID_TWI1_TX 9
-#define SAMA5_DMA_ID_TWI1_RX 10
-#define SAMA5_DMA_ID_UART0_TX 11
-#define SAMA5_DMA_ID_UART0_RX 12
-#define SAMA5_DMA_ID_SSC0_TX 13
-#define SAMA5_DMA_ID_SSC0_RX 14
-#define SAMA5_DMA_ID_SMD_TX 15
-#define SAMA5_DMA_ID_SMD_RX 16
-
-/*
- * DMA1 peripheral identifiers
- * for hardware handshaking interface
- */
-#define SAMA5_DMA_ID_MCI1 0
-
#endif
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 02/22] ARM: at91: remove unused CONSISTENT_DMA_SIZE defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
2018-11-05 15:50 ` [PATCH 01/22] ARM: at91: remove unused AT_DMA_ID_ defines Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 03/22] ARM: at91rm9200ek: Use SoC specific defines Sascha Hauer
` (21 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
CONSISTENT_DMA_SIZE is unused, remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 --
3 files changed, 6 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 591ea9fedd..7faa435b83 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -153,8 +153,6 @@
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
-#define CONSISTENT_DMA_SIZE SZ_4M
-
/*
* Cpu Name
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 5693402935..cbb4f81da8 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -145,6 +145,4 @@
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_1
-#define CONSISTENT_DMA_SIZE (14 * SZ_1M)
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 47f88fb15c..0c26eab7e6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -152,6 +152,4 @@
#define AT91SAM9X5_OHCI_BASE 0x00600000 /* USB Host controller (OHCI) */
#define AT91SAM9X5_EHCI_BASE 0x00700000 /* USB Host controller (EHCI) */
-#define CONSISTENT_DMA_SIZE SZ_4M
-
#endif
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 03/22] ARM: at91rm9200ek: Use SoC specific defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
2018-11-05 15:50 ` [PATCH 01/22] ARM: at91: remove unused AT_DMA_ID_ defines Sascha Hauer
2018-11-05 15:50 ` [PATCH 02/22] ARM: at91: remove unused CONSISTENT_DMA_SIZE defines Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 04/22] ARM: at91sam926x: Add header for at91sam926x common base addresses Sascha Hauer
` (20 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
Use AT91RM9200_BASE_PIOC rather than AT91_BASE_PIOC so we can get rid of
the latter later.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91rm9200ek/lowlevel.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index a85a22e797..905f5999d6 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -86,11 +86,11 @@ void __naked __bare_init barebox_arm_reset_vector(void)
*/
/* PIOC_ASR: Configure PIOC as peripheral (D16/D31) */
- __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91_BASE_PIOC + PIO_ASR);
+ __raw_writel(CONFIG_SYS_PIOC_ASR_VAL, AT91RM9200_BASE_PIOC + PIO_ASR);
/* PIOC_BSR */
- __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91_BASE_PIOC + PIO_BSR);
+ __raw_writel(CONFIG_SYS_PIOC_BSR_VAL, AT91RM9200_BASE_PIOC + PIO_BSR);
/* PIOC_PDR */
- __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91_BASE_PIOC + PIO_PDR);
+ __raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
/* EBI_CSA : CS1=SDRAM */
at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL);
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 04/22] ARM: at91sam926x: Add header for at91sam926x common base addresses
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (2 preceding siblings ...)
2018-11-05 15:50 ` [PATCH 03/22] ARM: at91rm9200ek: Use SoC specific defines Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 05/22] ARM: at91: remove unused defines Sascha Hauer
` (19 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
There are some base addresses common to at91sam926x. Add a separate
header for these.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91sam926x.h | 8 ++++++++
1 file changed, 8 insertions(+)
create mode 100644 arch/arm/mach-at91/include/mach/at91sam926x.h
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x.h b/arch/arm/mach-at91/include/mach/at91sam926x.h
new file mode 100644
index 0000000000..ab5cf515ef
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91sam926x.h
@@ -0,0 +1,8 @@
+#ifndef __MACH_AT91SAM926X_H
+#define __MACH_AT91SAM926X_H
+
+#define AT91SAM926X_BASE_PMC 0xfffffc00
+#define AT91SAM926X_BASE_RSTC 0xfffffd00
+#define AT91SAM926X_BASE_WDT 0xfffffd40
+
+#endif /* __MACH_AT91SAM926X_H */
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 05/22] ARM: at91: remove unused defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (3 preceding siblings ...)
2018-11-05 15:50 ` [PATCH 04/22] ARM: at91sam926x: Add header for at91sam926x common base addresses Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 06/22] ARM: at91: drop AT91_NB_USART Sascha Hauer
` (18 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91rm9200.h | 20 -------------
arch/arm/mach-at91/include/mach/at91sam9260.h | 29 +------------------
arch/arm/mach-at91/include/mach/at91sam9261.h | 14 ---------
arch/arm/mach-at91/include/mach/at91sam9263.h | 23 +--------------
.../include/mach/at91sam926x_board_init.h | 3 +-
arch/arm/mach-at91/include/mach/at91sam9g45.h | 17 -----------
arch/arm/mach-at91/include/mach/at91sam9n12.h | 11 -------
arch/arm/mach-at91/include/mach/at91sam9x5.h | 11 -------
arch/arm/mach-at91/include/mach/sama5d3.h | 2 --
9 files changed, 4 insertions(+), 126 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 4fe8fd891c..8e323ea615 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -19,8 +19,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripheral */
#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
@@ -99,21 +97,8 @@
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
-#define AT91_BASE_PIOA AT91RM9200_BASE_PIOA /* PIO Controller A */
-#define AT91_BASE_PIOB AT91RM9200_BASE_PIOB /* PIO Controller B */
-#define AT91_BASE_PIOC AT91RM9200_BASE_PIOC /* PIO Controller C */
-#define AT91_BASE_PIOD AT91RM9200_BASE_PIOD /* PIO Controller D */
-
-#define AT91_USART0 AT91RM9200_BASE_US0
-#define AT91_USART1 AT91RM9200_BASE_US1
-#define AT91_USART2 AT91RM9200_BASE_US2
-#define AT91_USART3 AT91RM9200_BASE_US3
#define AT91_NB_USART 5
-#define AT91_BASE_SPI AT91RM9200_BASE_SPI
-#define AT91_BASE_TWI AT91RM9200_BASE_TWI
-#define AT91_ID_UHP AT91RM9200_ID_UHP
-#define AT91_PMC_UHP AT91RM9200_PMC_UHP
#define AT91_TC (AT91RM9200_BASE_TC0 - AT91_BASE_SYS)
#define AT91_MATRIX 0 /* not supported */
@@ -133,9 +118,4 @@
#define AT91_VA_BASE_EMAC AT91RM9200_BASE_EMAC
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91RM9200"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 919901d6da..1cff76b4ee 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
@@ -105,25 +103,9 @@
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_BASE_WDT AT91SAM9260_BASE_WDT
#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
-#define AT91_BASE_PIOA AT91SAM9260_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9260_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9260_BASE_PIOC
-
-#define AT91_USART0 AT91SAM9260_BASE_US0
-#define AT91_USART1 AT91SAM9260_BASE_US1
-#define AT91_USART2 AT91SAM9260_BASE_US2
-#define AT91_USART3 AT91SAM9260_BASE_US3
-#define AT91_USART4 AT91SAM9260_BASE_US4
-#define AT91_USART5 AT91SAM9260_BASE_US5
-#define AT91_NB_USART 7
-#define AT91_BASE_SPI AT91SAM9260_BASE_SPI0
-#define AT91_BASE_TWI AT91SAM9260_BASE_TWI
-#define AT91_ID_UHP AT91SAM9260_ID_UHP
-#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
+#define AT91_NB_USART 7
#define AT91_PMC 0xfffffc00
@@ -157,13 +139,4 @@
#define AT91SAM9G20_UHP_BASE 0x00500000 /* USB Host controller */
-/*
- * Cpu Name
- */
-#if defined(CONFIG_AT91SAM9260)
-#define AT91_CPU_NAME "AT91SAM9260"
-#elif defined(CONFIG_AT91SAM9G20)
-#define AT91_CPU_NAME "AT91SAM9G20"
-#endif
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index 9124df5caa..d9172879b9 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
@@ -91,15 +89,8 @@
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_BASE_WDT AT91SAM9261_BASE_WDT
#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9261_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9261_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9261_BASE_PIOC
-#define AT91_USART0 AT91SAM9261_BASE_US0
-#define AT91_USART1 AT91SAM9261_BASE_US1
-#define AT91_USART2 AT91SAM9261_BASE_US2
#define AT91_NB_USART 4
#define AT91_PMC 0xfffffc00
@@ -119,9 +110,4 @@
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91SAM9261"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index e7ca8b63aa..f1dd848cc0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9263_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9263_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9263_ID_PIOCDE 4 /* Parallel IO Controller C, D and E */
@@ -109,26 +107,12 @@
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_BASE_WDT AT91SAM9263_BASE_WDT
#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
-#define AT91_BASE_PIOA AT91SAM9263_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9263_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9263_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9263_BASE_PIOD
-#define AT91_BASE_PIOE AT91SAM9263_BASE_PIOE
-
-#define AT91_USART0 AT91SAM9263_BASE_US0
-#define AT91_USART1 AT91SAM9263_BASE_US1
-#define AT91_USART2 AT91SAM9263_BASE_US2
+
#define AT91_NB_USART 4
#define AT91_SDRAMC AT91_SDRAMC0
-#define AT91_BASE_SPI AT91SAM9263_BASE_SPI0
-#define AT91_BASE_TWI AT91SAM9263_BASE_TWI
-#define AT91_ID_UHP AT91SAM9263_ID_UHP
-#define AT91_PMC_UHP AT91SAM926x_PMC_UHP
-
#define AT91_PMC 0xfffffc00
/*
@@ -147,9 +131,4 @@
#define AT91SAM9263_DMAC_BASE 0x00800000 /* DMA Controller */
#define AT91SAM9263_UHP_BASE 0x00a00000 /* USB Host controller */
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91SAM9263"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 7cacc0c8d7..749baaa8a6 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -18,6 +18,7 @@
#include <mach/at91_wdt.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
+#include <mach/at91sam926x.h>
struct at91sam926x_board_cfg {
/* SoC specific */
@@ -124,7 +125,7 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT))
return;
- __raw_writel(cfg->wdt_mr, AT91_BASE_WDT + AT91_WDT_MR);
+ __raw_writel(cfg->wdt_mr, AT91SAM926X_BASE_WDT + AT91_WDT_MR);
/* configure PIOx as EBI0 D[16-31] */
at91_mux_gpio_disable(cfg->pio, cfg->ebi_pio_pdr);
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 7faa435b83..2847541f9a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Controller Interrupt */
#define AT91SAM9G45_ID_PIOA 2 /* Parallel I/O Controller A */
#define AT91SAM9G45_ID_PIOB 3 /* Parallel I/O Controller B */
#define AT91SAM9G45_ID_PIOC 4 /* Parallel I/O Controller C */
@@ -120,18 +118,8 @@
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-#define AT91_BASE_WDT AT91SAM9G45_BASE_WDT
#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9G45_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9G45_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9G45_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9G45_BASE_PIOD
-#define AT91_BASE_PIOE AT91SAM9G45_BASE_PIOE
-#define AT91_USART0 AT91SAM9G45_BASE_US0
-#define AT91_USART1 AT91SAM9G45_BASE_US1
-#define AT91_USART2 AT91SAM9G45_BASE_US2
-#define AT91_USART3 AT91SAM9G45_BASE_US3
#define AT91_NB_USART 5
#define AT91_PMC 0xfffffc00
@@ -153,9 +141,4 @@
#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
-/*
- * Cpu Name
- */
-#define AT91_CPU_NAME "AT91SAM9G45"
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index cbb4f81da8..7fdd7528a0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Controller Interrupt */
#define AT91SAM9N12_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9N12_ID_PIOCD 3 /* Parallel I/O Controller C and D */
/* Reserved 4 */
@@ -116,17 +114,8 @@
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-#define AT91_BASE_WDT AT91SAM9N12_BASE_WDT
#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9N12_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9N12_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9N12_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9N12_BASE_PIOD
-#define AT91_USART0 AT91SAM9X5_BASE_US0
-#define AT91_USART1 AT91SAM9X5_BASE_US1
-#define AT91_USART2 AT91SAM9X5_BASE_US2
-#define AT91_USART3 AT91SAM9X5_BASE_US3
#define AT91_NB_USART 5
#define AT91_PMC 0xfffffc00
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 0c26eab7e6..112cda0aef 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -18,8 +18,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Controller Interrupt */
#define AT91SAM9X5_ID_PIOAB 2 /* Parallel I/O Controller A and B */
#define AT91SAM9X5_ID_PIOCD 3 /* Parallel I/O Controller C and D */
#define AT91SAM9X5_ID_SMD 4 /* SMD Soft Modem (SMD) */
@@ -123,17 +121,8 @@
#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-#define AT91_BASE_WDT AT91SAM9X5_BASE_WDT
#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
-#define AT91_BASE_PIOA AT91SAM9X5_BASE_PIOA
-#define AT91_BASE_PIOB AT91SAM9X5_BASE_PIOB
-#define AT91_BASE_PIOC AT91SAM9X5_BASE_PIOC
-#define AT91_BASE_PIOD AT91SAM9X5_BASE_PIOD
-#define AT91_USART0 AT91SAM9X5_BASE_US0
-#define AT91_USART1 AT91SAM9X5_BASE_US1
-#define AT91_USART2 AT91SAM9X5_BASE_US2
-#define AT91_USART3 AT91SAM9X5_BASE_US3
#define AT91_NB_USART 5
#define AT91_PMC 0xfffffc00
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index d53bcaee1a..00fd88dd72 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -15,8 +15,6 @@
/*
* Peripheral identifiers/interrupts.
*/
-#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
-#define AT91_ID_SYS 1 /* System Peripherals */
#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */
#define SAMA5D3_ID_PIT 3 /* Periodic Interval Timer Interrupt */
#define SAMA5D3_ID_WDT 4 /* Watchdog timer Interrupt */
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 06/22] ARM: at91: drop AT91_NB_USART
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (4 preceding siblings ...)
2018-11-05 15:50 ` [PATCH 05/22] ARM: at91: remove unused defines Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 07/22] ARM: at91: remove AT91_SDRAM_BASE Sascha Hauer
` (17 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
AT91_NB_USART only used to return an error from at91_register_uart() if
an invalid UART number is passed. This will never happen as the linker
fails earlier in that case, so the runtime check can be removed and with
it the now unused AT91_NB_USART define.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91rm9200.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9260.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9261.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9263.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 --
arch/arm/mach-at91/include/mach/board.h | 3 ---
arch/arm/mach-at91/include/mach/sama5d3.h | 2 --
arch/arm/mach-at91/include/mach/sama5d4.h | 1 -
10 files changed, 20 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index 8e323ea615..d06dfa7388 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -97,8 +97,6 @@
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
-#define AT91_NB_USART 5
-
#define AT91_TC (AT91RM9200_BASE_TC0 - AT91_BASE_SYS)
#define AT91_MATRIX 0 /* not supported */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index 1cff76b4ee..a816c448ba 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -105,8 +105,6 @@
#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
-#define AT91_NB_USART 7
-
#define AT91_PMC 0xfffffc00
/*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index d9172879b9..acd39f28de 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -91,8 +91,6 @@
#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
-#define AT91_NB_USART 4
-
#define AT91_PMC 0xfffffc00
/*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index f1dd848cc0..ef3424a6c5 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -109,8 +109,6 @@
#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
-#define AT91_NB_USART 4
-
#define AT91_SDRAMC AT91_SDRAMC0
#define AT91_PMC 0xfffffc00
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 2847541f9a..e9c7d7572a 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -120,8 +120,6 @@
#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
-#define AT91_NB_USART 5
-
#define AT91_PMC 0xfffffc00
/*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 7fdd7528a0..cb84e4cf76 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -116,8 +116,6 @@
#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
-#define AT91_NB_USART 5
-
#define AT91_PMC 0xfffffc00
/*
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 112cda0aef..3ea2501b4c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -123,8 +123,6 @@
#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
-#define AT91_NB_USART 5
-
#define AT91_PMC 0xfffffc00
/*
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 5d76e00aef..7735a6f38b 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -107,9 +107,6 @@ static inline struct device_d * at91_register_uart(unsigned id, unsigned pins)
resource_size_t start;
resource_size_t size = SZ_16K;
- if (id >= AT91_NB_USART)
- return NULL;
-
switch (id) {
case 0: /* DBGU */
start = at91_configure_dbgu();
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 00fd88dd72..2c64fdf48a 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -104,8 +104,6 @@
#define SAMA5D3_BASE_PMECC 0xffffc070
#define SAMA5D3_BASE_PMERRLOC 0xffffc500
-#define AT91_NB_USART 3
-
#define AT91_PMC 0xfffffc00
/*
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 046fdb0426..5ff0ffa131 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -122,7 +122,6 @@
#define SAMA5D4_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define SAMA5D4_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size */
-#define AT91_NB_USART 7
#define AT91_BASE_SYS 0xf0000000
#define AT91_PMC SAMA5D4_BASE_PMC
#define AT91_DDRSDRC0 (0xf0010000 - AT91_BASE_SYS)
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 07/22] ARM: at91: remove AT91_SDRAM_BASE
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (5 preceding siblings ...)
2018-11-05 15:50 ` [PATCH 06/22] ARM: at91: drop AT91_NB_USART Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:50 ` [PATCH 08/22] ARM: at91: consolidate phy reset functions Sascha Hauer
` (16 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
AT91_SDRAM_BASE is only used in board code which known the SDRAM base
address, so we do not need a common define.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91rm9200ek/lowlevel.c | 2 +-
arch/arm/mach-at91/include/mach/at91sam926x_board_init.h | 2 +-
arch/arm/mach-at91/include/mach/at91sam9g45.h | 2 --
arch/arm/mach-at91/include/mach/at91sam9n12.h | 2 --
arch/arm/mach-at91/include/mach/hardware.h | 7 -------
5 files changed, 2 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index 905f5999d6..acff615779 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -18,7 +18,7 @@
void static inline access_sdram(void)
{
- writel(0x00000000, AT91_SDRAM_BASE);
+ writel(0x00000000, AT91_CHIPSELECT_1);
}
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 749baaa8a6..b93b37d8c7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -51,7 +51,7 @@ struct at91sam926x_board_cfg {
static void __always_inline access_sdram(void)
{
- writel(0x00000000, AT91_SDRAM_BASE);
+ writel(0x00000000, AT91_CHIPSELECT_1);
}
static void __always_inline pmc_check_mckrdy(void)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index e9c7d7572a..7b19d92ad3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -137,6 +137,4 @@
#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index cb84e4cf76..0bb105b910 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -130,6 +130,4 @@
#define AT91SAM9N12_SMD_BASE 0x00400000 /* SMD Controller */
#define AT91SAM9N12_OHCI_BASE 0x00500000 /* USB Host controller (OHCI) */
-#define CONFIG_DRAM_BASE AT91_CHIPSELECT_1
-
#endif
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index bbaad714cf..e2e01343d4 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -66,13 +66,6 @@
#define SAMA5_CHIPSELECT_2 0x50000000
#define SAMA5_CHIPSELECT_3 0x60000000
-/* SDRAM */
-#ifdef CONFIG_DRAM_BASE
-#define AT91_SDRAM_BASE CONFIG_DRAM_BASE
-#else
-#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
-#endif
-
/* Clocks */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
--
2.19.1
_______________________________________________
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 08/22] ARM: at91: consolidate phy reset functions
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (6 preceding siblings ...)
2018-11-05 15:50 ` [PATCH 07/22] ARM: at91: remove AT91_SDRAM_BASE Sascha Hauer
@ 2018-11-05 15:50 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 09/22] ARM: at91: remove common matrix header file Sascha Hauer
` (15 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:50 UTC (permalink / raw)
To: Barebox List
Many boards have the same ethernet phy reset function, so share the code
in a common function.
While at it remove the AT91_RSTC offset from the rstc register defines.
AT91_RSTC was the offset between the AT91_SYSTEM_BASE and the reset
controller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/animeo_ip/init.c | 20 +--------------
arch/arm/boards/at91sam9260ek/init.c | 21 +---------------
arch/arm/boards/dss11/init.c | 22 +---------------
arch/arm/boards/haba-knx/init.c | 23 +----------------
arch/arm/boards/qil-a926x/init.c | 22 +---------------
arch/arm/boards/telit-evk-pro3/init.c | 21 +---------------
arch/arm/boards/usb-a926x/init.c | 24 +++---------------
arch/arm/mach-at91/at91sam9_reset.S | 2 +-
arch/arm/mach-at91/at91sam9g45_reset.S | 2 +-
arch/arm/mach-at91/include/mach/at91_rstc.h | 6 ++---
.../include/mach/at91sam926x_board_init.h | 2 +-
arch/arm/mach-at91/include/mach/board.h | 3 +++
arch/arm/mach-at91/setup.c | 25 +++++++++++++++++++
13 files changed, 43 insertions(+), 150 deletions(-)
diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index 847417398a..775c818df6 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -231,30 +231,12 @@ static void animeo_ip_power_control(void)
static void animeo_ip_phy_reset(void)
{
- unsigned long rstc;
int i;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
for (i = AT91_PIN_PA12; i <= AT91_PIN_PA29; i++)
at91_set_gpio_input(i, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
#define MACB_SA1B 0x0098
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index 5a21ac12fe..de74835d78 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -125,11 +125,6 @@ static struct macb_platform_data macb_pdata = {
static void at91sam9260ek_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -137,21 +132,7 @@ static void at91sam9260ek_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
/*
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 321c383ffc..432613ff4a 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -80,11 +80,6 @@ static struct macb_platform_data macb_pdata = {
static void dss11_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -92,22 +87,7 @@ static void dss11_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
static struct atmel_mci_platform_data dss11_mci_data = {
diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c
index 36f1e8b741..4a000d9aed 100644
--- a/arch/arm/boards/haba-knx/init.c
+++ b/arch/arm/boards/haba-knx/init.c
@@ -91,33 +91,12 @@ static struct macb_platform_data macb_pdata = {
static void haba_knx_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
at91_set_gpio_input(AT91_PIN_PA18, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
#define MACB_SA1B 0x0098
diff --git a/arch/arm/boards/qil-a926x/init.c b/arch/arm/boards/qil-a926x/init.c
index 3ef9872797..6fa0df033e 100644
--- a/arch/arm/boards/qil-a926x/init.c
+++ b/arch/arm/boards/qil-a926x/init.c
@@ -118,11 +118,6 @@ static struct macb_platform_data macb_pdata = {
static void qil_a9260_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -130,22 +125,7 @@ static void qil_a9260_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
/*
diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c
index ea63b1a094..4f536079cc 100644
--- a/arch/arm/boards/telit-evk-pro3/init.c
+++ b/arch/arm/boards/telit-evk-pro3/init.c
@@ -72,11 +72,6 @@ static struct macb_platform_data macb_pdata = {
static void evk_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -84,21 +79,7 @@ static void evk_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
- ;
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN);
+ at91sam_phy_reset(IOMEM(AT91SAM9260_BASE_RSTC));
}
/*
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index 12e8f4e0d6..e431cd4603 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -26,6 +26,7 @@
#include <io.h>
#include <envfs.h>
#include <mach/hardware.h>
+#include <mach/at91sam926x.h>
#include <nand.h>
#include <linux/sizes.h>
#include <linux/mtd/nand.h>
@@ -128,11 +129,6 @@ static struct macb_platform_data macb_pdata = {
static void usb_a9260_phy_reset(void)
{
- unsigned long rstc;
- struct clk *clk = clk_get(NULL, "macb_clk");
-
- clk_enable(clk);
-
at91_set_gpio_input(AT91_PIN_PA14, 0);
at91_set_gpio_input(AT91_PIN_PA15, 0);
at91_set_gpio_input(AT91_PIN_PA17, 0);
@@ -140,22 +136,8 @@ static void usb_a9260_phy_reset(void)
at91_set_gpio_input(AT91_PIN_PA26, 0);
at91_set_gpio_input(AT91_PIN_PA28, 0);
- rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
-
- /* Need to reset PHY -> 500ms reset */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (AT91_RSTC_ERSTL & (0x0d << 8)) |
- AT91_RSTC_URSTEN);
-
- at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
-
- /* Wait for end hardware reset */
- while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
-
- /* Restore NRST value */
- at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
- (rstc) |
- AT91_RSTC_URSTEN);
+ /* same address for the different supported SoCs */
+ at91sam_phy_reset(IOMEM(AT91SAM926X_BASE_RSTC));
}
static void usb_a9260_add_device_eth(void)
diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S
index 890545edbf..c10674aa40 100644
--- a/arch/arm/mach-at91/at91sam9_reset.S
+++ b/arch/arm/mach-at91/at91sam9_reset.S
@@ -40,4 +40,4 @@ restart_sam9: ldr r0, .at91_va_base_sdramc @ preload constants
.at91_va_base_sdramc:
.word AT91_BASE_SYS + AT91_SDRAMC
.at91_va_base_rstc_cr:
- .word AT91_BASE_SYS + AT91_RSTC_CR
+ .word AT91_BASE_SYS + AT91_RSTC + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 2cb113cdb4..be2ad9d396 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -37,4 +37,4 @@ restart_sam9g45: ldr r0, .at91_va_base_sdramc @ preload constants
.at91_va_base_sdramc:
.word AT91_BASE_SYS + AT91_DDRSDRC0
.at91_va_base_rstc_cr:
- .word AT91_BASE_SYS + AT91_RSTC_CR
+ .word AT91_BASE_SYS + AT91_RSTC + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/include/mach/at91_rstc.h b/arch/arm/mach-at91/include/mach/at91_rstc.h
index e49caef921..d67bed5213 100644
--- a/arch/arm/mach-at91/include/mach/at91_rstc.h
+++ b/arch/arm/mach-at91/include/mach/at91_rstc.h
@@ -16,13 +16,13 @@
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
-#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
+#define AT91_RSTC_CR (0x00) /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT91_RSTC_KEY (0xa5 << 24) /* KEY Password */
-#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
+#define AT91_RSTC_SR (0x04) /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
@@ -33,7 +33,7 @@
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
-#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
+#define AT91_RSTC_MR (0x08) /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index b93b37d8c7..42bb6a04c1 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -170,7 +170,7 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
at91sam926x_sdramc_init(cfg);
/* User reset enable*/
- at91_sys_write(AT91_RSTC_MR, cfg->rstc_rmr);
+ writel(cfg->rstc_rmr, AT91SAM926X_BASE_RSTC + AT91_RSTC_MR);
/*
* When boot from external boot
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 7735a6f38b..56c86f0bfb 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -164,4 +164,7 @@ struct at91_spi_platform_data {
void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata);
void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data);
+
+void at91sam_phy_reset(void __iomem *rstc_base);
+
#endif
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 7a19c45ea4..0cc3cc3dec 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -9,10 +9,12 @@
#include <io.h>
#include <init.h>
#include <restart.h>
+#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
#include <mach/at91_dbgu.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
@@ -300,3 +302,26 @@ static int at91_soc_device(void)
return 0;
}
coredevice_initcall(at91_soc_device);
+
+void at91sam_phy_reset(void __iomem *rstc_base)
+{
+ unsigned long rstc;
+ struct clk *clk = clk_get(NULL, "macb_clk");
+
+ clk_enable(clk);
+
+ rstc = readl(rstc_base + AT91_RSTC_MR) & AT91_RSTC_ERSTL;
+
+ /* Need to reset PHY -> 500ms reset */
+ writel(AT91_RSTC_KEY | (AT91_RSTC_ERSTL & (0x0d << 8)) | AT91_RSTC_URSTEN,
+ rstc_base + AT91_RSTC_MR);
+
+ writel(AT91_RSTC_KEY | AT91_RSTC_EXTRST, rstc_base + AT91_RSTC_CR);
+
+ /* Wait for end hardware reset */
+ while (!(readl(rstc_base + AT91_RSTC_SR) & AT91_RSTC_NRSTL))
+ ;
+
+ /* Restore NRST value */
+ writel(AT91_RSTC_KEY | (rstc) | AT91_RSTC_URSTEN, rstc_base + AT91_RSTC_MR);
+}
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 09/22] ARM: at91: remove common matrix header file
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (7 preceding siblings ...)
2018-11-05 15:50 ` [PATCH 08/22] ARM: at91: consolidate phy reset functions Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 10/22] ARM: at91: Add SoC namespace to matrix defines Sascha Hauer
` (14 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
The common matrix header file can be removed when the users include the
SoC specific one. Fix the only user and remove the file.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/pm9261/lowlevel_init.c | 2 +-
.../mach-at91/include/mach/at91sam9_matrix.h | 30 -------------------
2 files changed, 1 insertion(+), 31 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9_matrix.h
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
index a4cb8af697..dbb58ee313 100644
--- a/arch/arm/boards/pm9261/lowlevel_init.c
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -7,7 +7,7 @@
#include <asm/barebox-arm.h>
#include <mach/at91sam926x_board_init.h>
-#include <mach/at91sam9_matrix.h>
+#include <mach/at91sam9261_matrix.h>
#define MASTER_PLL_DIV 15
#define MASTER_PLL_MUL 162
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9_matrix.h
deleted file mode 100644
index 1d1d9059a5..0000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_matrix.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jrosoft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#ifndef __ASM_ARCH_AT91SAM9_MATRIX_H
-#define __ASM_ARCH_AT91SAM9_MATRIX_H
-
-#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9G20)
-#include <mach/at91sam9260_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9261) || defined(CONFIG_ARCH_AT91SAM9G10)
-#include <mach/at91sam9261_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9263)
-#include <mach/at91sam9263_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9RL)
-#include <mach/at91sam9rl_matrix.h>
-#elif defined(CONFIG_ARCH_AT91CAP9)
-#include <mach/at91cap9_matrix.h>
-#elif defined(CONFIG_ARCH_AT91SAM9G45) || defined(CONFIG_ARCH_AT91SAM9M10G45)
-#include <mach/at91sam9g45_matrix.h>
-#else
-#error "Unsupported AT91SAM9/CAP9 processor"
-#endif
-
-#endif /* __ASM_ARCH_AT91SAM9_MATRIX_H */
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 10/22] ARM: at91: Add SoC namespace to matrix defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (8 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 09/22] ARM: at91: remove common matrix header file Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 11/22] ARM: at91: Use SoC specific base addresses where appropriate Sascha Hauer
` (13 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
Add SoC namespace to matrix define so we have one source less of
conflicting defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91sam9261ek/lowlevel_init.c | 4 +-
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 6 +-
arch/arm/boards/at91sam9263ek/of_init.c | 6 +-
arch/arm/boards/at91sam9x5ek/init.c | 16 +-
arch/arm/boards/pm9261/lowlevel_init.c | 4 +-
arch/arm/boards/pm9263/lowlevel_init.c | 6 +-
.../arm/boards/tny-a926x/tny_a9263_lowlevel.c | 6 +-
.../arm/boards/usb-a926x/usb_a9263_lowlevel.c | 6 +-
arch/arm/mach-at91/at91sam9260_devices.c | 5 +-
arch/arm/mach-at91/at91sam9261_devices.c | 5 +-
arch/arm/mach-at91/at91sam9263_devices.c | 5 +-
arch/arm/mach-at91/at91sam9g45_devices.c | 5 +-
arch/arm/mach-at91/at91sam9n12_devices.c | 12 +-
arch/arm/mach-at91/at91sam9x5_devices.c | 5 +-
.../include/mach/at91sam9260_matrix.h | 114 ++++----
.../include/mach/at91sam9261_matrix.h | 82 +++---
.../include/mach/at91sam9263_matrix.h | 208 +++++++--------
.../include/mach/at91sam926x_board_init.h | 4 +-
.../include/mach/at91sam9g45_matrix.h | 246 +++++++++---------
.../include/mach/at91sam9n12_matrix.h | 146 +++++------
.../include/mach/at91sam9x5_matrix.h | 228 ++++++++--------
drivers/usb/gadget/at91_udc.c | 19 +-
22 files changed, 575 insertions(+), 563 deletions(-)
diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
index c4e4957ca7..2ade3191d4 100644
--- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
@@ -34,7 +34,7 @@ static void __bare_init at91sam9261ek_board_config(struct at91sam926x_board_cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+ AT91SAM9261_MATRIX_DBPUC | AT91SAM9261_MATRIX_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
@@ -108,7 +108,7 @@ static void __bare_init at91sam9261ek_init(void)
cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC);
cfg.ebi_pio_is_peripha = false;
- cfg.matrix_csa = AT91_MATRIX_EBICSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
at91sam9261ek_board_config(&cfg);
at91sam926x_board_init(&cfg);
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
index 30c14089d1..af4b62c7a4 100644
--- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -29,8 +29,8 @@ static void __bare_init at91sam9263ek_board_config(struct at91sam926x_board_cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
@@ -106,7 +106,7 @@ static void __bare_init at91sam9263ek_init(void *fdt)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
at91sam9263ek_board_config(&cfg);
at91sam926x_board_init(&cfg);
diff --git a/arch/arm/boards/at91sam9263ek/of_init.c b/arch/arm/boards/at91sam9263ek/of_init.c
index b4d216fa3e..98af5adfc0 100644
--- a/arch/arm/boards/at91sam9263ek/of_init.c
+++ b/arch/arm/boards/at91sam9263ek/of_init.c
@@ -66,9 +66,9 @@ static int at91sam9263_smc_init(void)
else
ek_nand_smc_config.mode |= AT91_SMC_DBW_8;
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- csa |= AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
- at91_sys_write(AT91_MATRIX_EBI0CSA, csa);
+ csa = readl(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+ csa |= AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
/* configure chip-select 3 (NAND) */
sam9_smc_configure(0, 3, &ek_nand_smc_config);
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index 649545e8a7..7ed6f58595 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -70,16 +70,16 @@ static int ek_add_device_smc(void)
if (!of_machine_is_compatible("atmel,at91sam9x5ek"))
return 0;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ csa = readl(AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
/* Enable CS3 */
- csa |= AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH;
+ csa |= AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH;
/* NAND flash on D16 */
- csa |= AT91_MATRIX_NFD0_ON_D16;
+ csa |= AT91SAM9X5_MATRIX_NFD0_ON_D16;
/* Configure IO drive */
- csa &= ~AT91_MATRIX_EBI_EBI_IOSR_NORMAL;
- at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ csa &= ~AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL;
+ writel(csa, AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
add_generic_device("at91sam9-smc",
DEVICE_ID_SINGLE, NULL,
@@ -96,9 +96,9 @@ static int ek_add_device_smc(void)
sam9_smc_configure(0, 3, &cm_nand_smc_config);
if (at91sam9x5ek_cm_is_vendor(VENDOR_COGENT)) {
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- csa |= AT91_MATRIX_EBI_VDDIOMSEL_1_8V;
- at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ csa = readl(AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
+ csa |= AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V;
+ writel(csa, AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
}
return 0;
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
index dbb58ee313..5464fda90c 100644
--- a/arch/arm/boards/pm9261/lowlevel_init.c
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -28,7 +28,7 @@ static void __bare_init pm9261_board_config(struct at91sam926x_board_cfg *cfg)
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_DBPUC | AT91_MATRIX_CS1A_SDRAMC;
+ AT91SAM9261_MATRIX_DBPUC | AT91SAM9261_MATRIX_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
@@ -102,7 +102,7 @@ static void __bare_init pm9261_init(void)
cfg.pio = IOMEM(AT91SAM9261_BASE_PIOC);
cfg.sdramc = IOMEM(AT91SAM9261_BASE_SDRAMC);
cfg.ebi_pio_is_peripha = false;
- cfg.matrix_csa = AT91_MATRIX_EBICSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
pm9261_board_config(&cfg);
at91sam926x_board_init(&cfg);
diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c
index 6849f0a5bf..bcbcf7d6ab 100644
--- a/arch/arm/boards/pm9263/lowlevel_init.c
+++ b/arch/arm/boards/pm9263/lowlevel_init.c
@@ -30,8 +30,8 @@ static void __bare_init pm9263_board_config(struct at91sam926x_board_cfg *cfg)
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 0;
cfg->smc_mode =
@@ -123,7 +123,7 @@ static void __bare_init pm9263_board_init(void)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
pm9263_board_config(&cfg);
at91sam926x_board_init(&cfg);
diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
index 4b57b74e13..b7630d4d6c 100644
--- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
+++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
@@ -33,8 +33,8 @@ static void __bare_init tny_a9263_board_config(struct at91sam926x_board_cfg *cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
@@ -107,7 +107,7 @@ static void __bare_init tny_a9263_init(void)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
tny_a9263_board_config(&cfg);
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
index 066452b956..6a3e7ca365 100644
--- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
+++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
@@ -35,8 +35,8 @@ static void __bare_init usb_a9263_board_config(struct at91sam926x_board_cfg *cfg
cfg->ebi_pio_ppudr = 0xFFFF0000;
/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
cfg->ebi_csa =
- AT91_MATRIX_EBI0_DBPUC | AT91_MATRIX_EBI0_VDDIOMSEL_3_3V |
- AT91_MATRIX_EBI0_CS1A_SDRAMC;
+ AT91SAM9263_MATRIX_EBI0_DBPUC | AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V |
+ AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC;
cfg->smc_cs = 3;
cfg->smc_mode =
@@ -113,7 +113,7 @@ static void __bare_init usb_a9263_init(void)
cfg.pio = IOMEM(AT91SAM9263_BASE_PIOD);
cfg.sdramc = IOMEM(AT91SAM9263_BASE_SDRAMC0);
cfg.ebi_pio_is_peripha = true;
- cfg.matrix_csa = AT91_MATRIX_EBI0CSA;
+ cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
usb_a9263_board_config(&cfg);
at91sam926x_board_init(&cfg);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 1cb8983514..c5323e2cb2 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -145,8 +145,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9260_BASE_MATRIX + AT91SAM9260_MATRIX_EBICSA);
+ csa |= AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9260_BASE_MATRIX + AT91SAM9260_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 6be390937d..9b7703ee97 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -94,8 +94,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
+ csa |= AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 6302684b2d..ab3968eae2 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -139,8 +139,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
- at91_sys_write(AT91_MATRIX_EBI0CSA, csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
+ csa |= AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 67ca3590c3..b44273a0de 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -141,8 +141,9 @@ void at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91SAM9G45_BASE_MATRIX + AT91SAM9G45_MATRIX_EBICSA);
+ csa |= AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91SAM9G45_BASE_MATRIX + AT91SAM9G45_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index 84c871c6e8..e38fc77363 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -158,19 +158,19 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
data->pmecc_lookup_table_offset = 0x8000;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
+ csa = readl(AT91SAM9N12_BASE_MATRIX + AT91SAM9N12_MATRIX_EBICSA);
/* Assign CS3 to NAND/SmartMedia Interface */
- csa |= AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH;
+ csa |= AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH;
/* Configure databus */
if (!data->bus_on_d0)
- csa |= AT91_MATRIX_NFD0_ON_D16;
+ csa |= AT91SAM9N12_MATRIX_NFD0_ON_D16;
else
- csa &= ~AT91_MATRIX_NFD0_ON_D16;
+ csa &= ~AT91SAM9N12_MATRIX_NFD0_ON_D16;
/* Configure IO drive */
- csa |= AT91_MATRIX_EBI_HIGH_DRIVE;
+ csa |= AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE;
- at91_sys_write(AT91_MATRIX_EBICSA, csa);
+ writel(csa, AT91SAM9N12_BASE_MATRIX + AT91SAM9N12_MATRIX_EBICSA);
/* enable pin */
if (gpio_is_valid(data->enable_pin))
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index d7ddda47c6..e21bd598c9 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -248,8 +248,9 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
if (!data)
return;
- csa = at91_sys_read(AT91_MATRIX_EBICSA);
- at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH);
+ csa = readl(AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
+ csa |= AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH;
+ writel(csa, AT91SAM9X5_BASE_MATRIX + AT91SAM9X5_MATRIX_EBICSA);
data->pmecc_lookup_table_offset = 0x8000;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
index 020f02ed92..792afa39b7 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260_matrix.h
@@ -15,66 +15,66 @@
#ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9260_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9260_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9260_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9260_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9260_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9260_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9260_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9260_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9260_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9260_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9260_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9260_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+#define AT91SAM9260_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9260_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9260_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9260_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9260_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9260_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9260_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9260_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91SAM9260_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91SAM9260_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91SAM9260_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9260_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9260_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9260_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9260_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9260_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9260_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9260_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9260_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9260_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9260_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9260_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9260_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9260_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9260_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9260_MATRIX_EBICSA (0x11C) /* EBI Chip Select Assignment Register */
+#define AT91SAM9260_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9260_MATRIX_CS1A_SMC (0 << 1)
+#define AT91SAM9260_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9260_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9260_MATRIX_CS3A_SMC (0 << 3)
+#define AT91SAM9260_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9260_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9260_MATRIX_CS4A_SMC (0 << 4)
+#define AT91SAM9260_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91SAM9260_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9260_MATRIX_CS5A_SMC (0 << 5)
+#define AT91SAM9260_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91SAM9260_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9260_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9260_MATRIX_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9260_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
index 7de01573a3..63e92ccd22 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261_matrix.h
@@ -15,50 +15,50 @@
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
-#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9261_MATRIX_MCFG (0x00) /* Master Configuration Register */
+#define AT91SAM9261_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9261_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
+#define AT91SAM9261_MATRIX_SCFG0 (0x04) /* Slave Configuration Register 0 */
+#define AT91SAM9261_MATRIX_SCFG1 (0x08) /* Slave Configuration Register 1 */
+#define AT91SAM9261_MATRIX_SCFG2 (0x0C) /* Slave Configuration Register 2 */
+#define AT91SAM9261_MATRIX_SCFG3 (0x10) /* Slave Configuration Register 3 */
+#define AT91SAM9261_MATRIX_SCFG4 (0x14) /* Slave Configuration Register 4 */
+#define AT91SAM9261_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9261_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9261_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_16 (5 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_ITCM_64 (7 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_16 (5 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
-#define AT91_MATRIX_DTCM_64 (7 << 4)
+#define AT91SAM9261_MATRIX_TCR (0x24) /* TCM Configuration Register */
+#define AT91SAM9261_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91SAM9261_MATRIX_ITCM_0 (0 << 0)
+#define AT91SAM9261_MATRIX_ITCM_16 (5 << 0)
+#define AT91SAM9261_MATRIX_ITCM_32 (6 << 0)
+#define AT91SAM9261_MATRIX_ITCM_64 (7 << 0)
+#define AT91SAM9261_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91SAM9261_MATRIX_DTCM_0 (0 << 4)
+#define AT91SAM9261_MATRIX_DTCM_16 (5 << 4)
+#define AT91SAM9261_MATRIX_DTCM_32 (6 << 4)
+#define AT91SAM9261_MATRIX_DTCM_64 (7 << 4)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9261_MATRIX_EBICSA (0x30) /* EBI Chip Select Assignment Register */
+#define AT91SAM9261_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9261_MATRIX_CS1A_SMC (0 << 1)
+#define AT91SAM9261_MATRIX_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9261_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9261_MATRIX_CS3A_SMC (0 << 3)
+#define AT91SAM9261_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9261_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9261_MATRIX_CS4A_SMC (0 << 4)
+#define AT91SAM9261_MATRIX_CS4A_SMC_CF1 (1 << 4)
+#define AT91SAM9261_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9261_MATRIX_CS5A_SMC (0 << 5)
+#define AT91SAM9261_MATRIX_CS5A_SMC_CF2 (1 << 5)
+#define AT91SAM9261_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
-#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
+#define AT91SAM9261_MATRIX_USBPUCR (0x34) /* USB Pad Pull-Up Control Register */
+#define AT91SAM9261_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
index 83aaaab773..0082666cd3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263_matrix.h
@@ -15,115 +15,115 @@
#ifndef AT91SAM9263_MATRIX_H
#define AT91SAM9263_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9263_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9263_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9263_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9263_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9263_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9263_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9263_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */
+#define AT91SAM9263_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */
+#define AT91SAM9263_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */
+#define AT91SAM9263_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9263_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9263_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9263_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9263_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9263_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
-#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
-#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
+#define AT91SAM9263_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9263_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9263_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9263_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9263_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9263_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
+#define AT91SAM9263_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
+#define AT91SAM9263_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
+#define AT91SAM9263_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9263_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9263_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9263_MATRIX_ARBT (3 << 24) /* Arbitration Type */
+#define AT91SAM9263_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
+#define AT91SAM9263_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9263_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9263_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */
+#define AT91SAM9263_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9263_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */
+#define AT91SAM9263_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9263_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */
+#define AT91SAM9263_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9263_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */
+#define AT91SAM9263_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9263_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */
+#define AT91SAM9263_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */
+#define AT91SAM9263_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */
+#define AT91SAM9263_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */
+#define AT91SAM9263_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */
+#define AT91SAM9263_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
+#define AT91SAM9263_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
+#define AT91SAM9263_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9263_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9263_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9263_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9263_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9263_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9263_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9263_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9263_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
+#define AT91SAM9263_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9263_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9263_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9263_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9263_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9263_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9263_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9263_MATRIX_RCB6 (1 << 6)
+#define AT91SAM9263_MATRIX_RCB7 (1 << 7)
+#define AT91SAM9263_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_16 (5 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_16 (5 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
+#define AT91SAM9263_MATRIX_TCMR (0x114) /* TCM Configuration Register */
+#define AT91SAM9263_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91SAM9263_MATRIX_ITCM_0 (0 << 0)
+#define AT91SAM9263_MATRIX_ITCM_16 (5 << 0)
+#define AT91SAM9263_MATRIX_ITCM_32 (6 << 0)
+#define AT91SAM9263_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91SAM9263_MATRIX_DTCM_0 (0 << 4)
+#define AT91SAM9263_MATRIX_DTCM_16 (5 << 4)
+#define AT91SAM9263_MATRIX_DTCM_32 (6 << 4)
-#define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
-#define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
-#define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
-#define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9263_MATRIX_EBI0CSA (0x120) /* EBI0 Chip Select Assignment Register */
+#define AT91SAM9263_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS1A_SMC (0 << 1)
+#define AT91SAM9263_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9263_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC (0 << 3)
+#define AT91SAM9263_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9263_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC (0 << 4)
+#define AT91SAM9263_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
+#define AT91SAM9263_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC (0 << 5)
+#define AT91SAM9263_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
+#define AT91SAM9263_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9263_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
-#define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
-#define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9263_MATRIX_EBI1CSA (0x124) /* EBI1 Chip Select Assignment Register */
+#define AT91SAM9263_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9263_MATRIX_EBI1_CS1A_SMC (0 << 1)
+#define AT91SAM9263_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9263_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC (0 << 3)
+#define AT91SAM9263_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9263_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9263_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 42bb6a04c1..4141e80ddb 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -25,7 +25,7 @@ struct at91sam926x_board_cfg {
void __iomem *pio;
void __iomem *sdramc;
u32 ebi_pio_is_peripha;
- u32 matrix_csa;
+ void __iomem *matrix_csa;
/* board specific */
u32 wdt_mr;
@@ -133,7 +133,7 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
if (cfg->ebi_pio_is_peripha)
at91_mux_set_A_periph(cfg->pio, cfg->ebi_pio_ppudr);
- at91_sys_write(cfg->matrix_csa, cfg->ebi_csa);
+ writel(cfg->ebi_csa, cfg->matrix_csa);
/* flash */
at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
index c972d60e0a..53f50fef8f 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45_matrix.h
@@ -15,139 +15,139 @@
#ifndef AT91SAM9G45_MATRIX_H
#define AT91SAM9G45_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
+#define AT91SAM9G45_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9G45_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9G45_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9G45_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9G45_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9G45_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9G45_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */
+#define AT91SAM9G45_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */
+#define AT91SAM9G45_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */
+#define AT91SAM9G45_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */
+#define AT91SAM9G45_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */
+#define AT91SAM9G45_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */
+#define AT91SAM9G45_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9G45_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91SAM9G45_MATRIX_ULBT_128 (7 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9G45_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9G45_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9G45_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9G45_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9G45_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9G45_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
+#define AT91SAM9G45_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
+#define AT91SAM9G45_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
+#define AT91SAM9G45_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9G45_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9G45_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9G45_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */
+#define AT91SAM9G45_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9G45_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */
+#define AT91SAM9G45_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9G45_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */
+#define AT91SAM9G45_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9G45_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */
+#define AT91SAM9G45_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9G45_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */
+#define AT91SAM9G45_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */
+#define AT91SAM9G45_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */
+#define AT91SAM9G45_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */
+#define AT91SAM9G45_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */
+#define AT91SAM9G45_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
+#define AT91SAM9G45_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
+#define AT91SAM9G45_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9G45_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9G45_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9G45_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9G45_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9G45_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9G45_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9G45_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9G45_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
+#define AT91SAM9G45_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
+#define AT91SAM9G45_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9G45_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9G45_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9G45_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9G45_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9G45_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9G45_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9G45_MATRIX_RCB6 (1 << 6)
+#define AT91SAM9G45_MATRIX_RCB7 (1 << 7)
+#define AT91SAM9G45_MATRIX_RCB8 (1 << 8)
+#define AT91SAM9G45_MATRIX_RCB9 (1 << 9)
+#define AT91SAM9G45_MATRIX_RCB10 (1 << 10)
+#define AT91SAM9G45_MATRIX_RCB11 (1 << 11)
-#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
-#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
-#define AT91_MATRIX_ITCM_0 (0 << 0)
-#define AT91_MATRIX_ITCM_32 (6 << 0)
-#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
-#define AT91_MATRIX_DTCM_0 (0 << 4)
-#define AT91_MATRIX_DTCM_32 (6 << 4)
-#define AT91_MATRIX_DTCM_64 (7 << 4)
-#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
-#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
-#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
+#define AT91SAM9G45_MATRIX_TCMR (0x110) /* TCM Configuration Register */
+#define AT91SAM9G45_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
+#define AT91SAM9G45_MATRIX_ITCM_0 (0 << 0)
+#define AT91SAM9G45_MATRIX_ITCM_32 (6 << 0)
+#define AT91SAM9G45_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
+#define AT91SAM9G45_MATRIX_DTCM_0 (0 << 4)
+#define AT91SAM9G45_MATRIX_DTCM_32 (6 << 4)
+#define AT91SAM9G45_MATRIX_DTCM_64 (7 << 4)
+#define AT91SAM9G45_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
+#define AT91SAM9G45_MATRIX_TCM_NO_WS (0x0 << 11)
+#define AT91SAM9G45_MATRIX_TCM_ONE_WS (0x1 << 11)
-#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
+#define AT91SAM9G45_MATRIX_VIDEO (0x118) /* Video Mode Configuration Register */
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
#define AT91C_VDEC_SEL_OFF (0 << 0)
#define AT91C_VDEC_SEL_ON (1 << 0)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
-#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
-#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
-#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
-#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
-#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
-#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
-#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
-#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
+#define AT91SAM9G45_MATRIX_EBICSA (0x128) /* EBI Chip Select Assignment Register */
+#define AT91SAM9G45_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91SAM9G45_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9G45_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91SAM9G45_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91SAM9G45_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC (0 << 4)
+#define AT91SAM9G45_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
+#define AT91SAM9G45_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
+#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC (0 << 5)
+#define AT91SAM9G45_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
+#define AT91SAM9G45_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9G45_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91SAM9G45_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9G45_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
+#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91SAM9G45_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
+#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
+#define AT91SAM9G45_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
-#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
-#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
-#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
-#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91SAM9G45_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */
+#define AT91SAM9G45_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91SAM9G45_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91SAM9G45_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91SAM9G45_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
-#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
-#define AT91_MATRIX_WPSR_WPV (1 << 0)
-#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+#define AT91SAM9G45_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */
+#define AT91SAM9G45_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91SAM9G45_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91SAM9G45_MATRIX_WPSR_WPV (1 << 0)
+#define AT91SAM9G45_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
index 0e42918f65..bdb0211abc 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12_matrix.h
@@ -15,84 +15,84 @@
#ifndef _AT91SAM9N12_MATRIX_H_
#define _AT91SAM9N12_MATRIX_H_
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
+#define AT91SAM9N12_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9N12_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9N12_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9N12_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9N12_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9N12_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9N12_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9N12_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91SAM9N12_MATRIX_ULBT_128 (7 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9N12_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9N12_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9N12_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9N12_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9N12_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9N12_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9N12_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9N12_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9N12_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9N12_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9N12_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9N12_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9N12_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9N12_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9N12_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9N12_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9N12_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9N12_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9N12_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9N12_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9N12_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9N12_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9N12_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9N12_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9N12_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9N12_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x118) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPD_ON (0 << 9)
-#define AT91_MATRIX_EBI_DBPD_OFF (1 << 9)
-#define AT91_MATRIX_EBI_DRIVE (1 << 17) /* EBI I/O Drive Configuration */
-#define AT91_MATRIX_EBI_LOW_DRIVE (0 << 17)
-#define AT91_MATRIX_EBI_HIGH_DRIVE (1 << 17)
-#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
-#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
-#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
+#define AT91SAM9N12_MATRIX_EBICSA (0x118) /* EBI Chip Select Assignment Register */
+#define AT91SAM9N12_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9N12_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91SAM9N12_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9N12_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91SAM9N12_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
+#define AT91SAM9N12_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9N12_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91SAM9N12_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91SAM9N12_MATRIX_EBI_DBPDC (1 << 9) /* Data Bus Pull-up Configuration */
+#define AT91SAM9N12_MATRIX_EBI_DBPD_ON (0 << 9)
+#define AT91SAM9N12_MATRIX_EBI_DBPD_OFF (1 << 9)
+#define AT91SAM9N12_MATRIX_EBI_DRIVE (1 << 17) /* EBI I/O Drive Configuration */
+#define AT91SAM9N12_MATRIX_EBI_LOW_DRIVE (0 << 17)
+#define AT91SAM9N12_MATRIX_EBI_HIGH_DRIVE (1 << 17)
+#define AT91SAM9N12_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
+#define AT91SAM9N12_MATRIX_NFD0_ON_D0 (0 << 24)
+#define AT91SAM9N12_MATRIX_NFD0_ON_D16 (1 << 24)
-#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
-#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
-#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
-#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91SAM9N12_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */
+#define AT91SAM9N12_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91SAM9N12_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91SAM9N12_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91SAM9N12_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
-#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
-#define AT91_MATRIX_WPSR_WPV (1 << 0)
-#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+#define AT91SAM9N12_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */
+#define AT91SAM9N12_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91SAM9N12_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91SAM9N12_MATRIX_WPSR_WPV (1 << 0)
+#define AT91SAM9N12_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
index b070a407e8..fca7646d35 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5_matrix.h
@@ -15,125 +15,125 @@
#ifndef AT91SAM9X5_MATRIX_H
#define AT91SAM9X5_MATRIX_H
-#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
-#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
-#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
-#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
-#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
-#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
-#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
-#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
-#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
-#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
-#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
-#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
-#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
-#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
-#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
-#define AT91_MATRIX_ULBT_FOUR (2 << 0)
-#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
-#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
-#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
-#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
-#define AT91_MATRIX_ULBT_128 (7 << 0)
+#define AT91SAM9X5_MATRIX_MCFG0 (0x00) /* Master Configuration Register 0 */
+#define AT91SAM9X5_MATRIX_MCFG1 (0x04) /* Master Configuration Register 1 */
+#define AT91SAM9X5_MATRIX_MCFG2 (0x08) /* Master Configuration Register 2 */
+#define AT91SAM9X5_MATRIX_MCFG3 (0x0C) /* Master Configuration Register 3 */
+#define AT91SAM9X5_MATRIX_MCFG4 (0x10) /* Master Configuration Register 4 */
+#define AT91SAM9X5_MATRIX_MCFG5 (0x14) /* Master Configuration Register 5 */
+#define AT91SAM9X5_MATRIX_MCFG6 (0x18) /* Master Configuration Register 6 */
+#define AT91SAM9X5_MATRIX_MCFG7 (0x1C) /* Master Configuration Register 7 */
+#define AT91SAM9X5_MATRIX_MCFG8 (0x20) /* Master Configuration Register 8 */
+#define AT91SAM9X5_MATRIX_MCFG9 (0x24) /* Master Configuration Register 9 */
+#define AT91SAM9X5_MATRIX_MCFG10 (0x28) /* Master Configuration Register 10 */
+#define AT91SAM9X5_MATRIX_MCFG11 (0x2C) /* Master Configuration Register 11 */
+#define AT91SAM9X5_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
+#define AT91SAM9X5_MATRIX_ULBT_INFINITE (0 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_SINGLE (1 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_FOUR (2 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_EIGHT (3 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_SIXTEEN (4 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_THIRTYTWO (5 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_SIXTYFOUR (6 << 0)
+#define AT91SAM9X5_MATRIX_ULBT_128 (7 << 0)
-#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
-#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
-#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
-#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
-#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
-#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
-#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
-#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
-#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
-#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
-#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
-#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
-#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
-#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
+#define AT91SAM9X5_MATRIX_SCFG0 (0x40) /* Slave Configuration Register 0 */
+#define AT91SAM9X5_MATRIX_SCFG1 (0x44) /* Slave Configuration Register 1 */
+#define AT91SAM9X5_MATRIX_SCFG2 (0x48) /* Slave Configuration Register 2 */
+#define AT91SAM9X5_MATRIX_SCFG3 (0x4C) /* Slave Configuration Register 3 */
+#define AT91SAM9X5_MATRIX_SCFG4 (0x50) /* Slave Configuration Register 4 */
+#define AT91SAM9X5_MATRIX_SCFG5 (0x54) /* Slave Configuration Register 5 */
+#define AT91SAM9X5_MATRIX_SCFG6 (0x58) /* Slave Configuration Register 6 */
+#define AT91SAM9X5_MATRIX_SCFG7 (0x5C) /* Slave Configuration Register 7 */
+#define AT91SAM9X5_MATRIX_SCFG8 (0x60) /* Slave Configuration Register 8 */
+#define AT91SAM9X5_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
+#define AT91SAM9X5_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
+#define AT91SAM9X5_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
-#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
-#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
-#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
-#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
-#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
-#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
-#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
-#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
-#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
-#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
-#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
-#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
-#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
-#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
-#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
-#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
-#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
-#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
-#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
-#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
-#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
-#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
-#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
-#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
-#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
-#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
-#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
-#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
-#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
-#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_PRAS0 (0x80) /* Priority Register A for Slave 0 */
+#define AT91SAM9X5_MATRIX_PRBS0 (0x84) /* Priority Register B for Slave 0 */
+#define AT91SAM9X5_MATRIX_PRAS1 (0x88) /* Priority Register A for Slave 1 */
+#define AT91SAM9X5_MATRIX_PRBS1 (0x8C) /* Priority Register B for Slave 1 */
+#define AT91SAM9X5_MATRIX_PRAS2 (0x90) /* Priority Register A for Slave 2 */
+#define AT91SAM9X5_MATRIX_PRBS2 (0x94) /* Priority Register B for Slave 2 */
+#define AT91SAM9X5_MATRIX_PRAS3 (0x98) /* Priority Register A for Slave 3 */
+#define AT91SAM9X5_MATRIX_PRBS3 (0x9C) /* Priority Register B for Slave 3 */
+#define AT91SAM9X5_MATRIX_PRAS4 (0xA0) /* Priority Register A for Slave 4 */
+#define AT91SAM9X5_MATRIX_PRBS4 (0xA4) /* Priority Register B for Slave 4 */
+#define AT91SAM9X5_MATRIX_PRAS5 (0xA8) /* Priority Register A for Slave 5 */
+#define AT91SAM9X5_MATRIX_PRBS5 (0xAC) /* Priority Register B for Slave 5 */
+#define AT91SAM9X5_MATRIX_PRAS6 (0xB0) /* Priority Register A for Slave 6 */
+#define AT91SAM9X5_MATRIX_PRBS6 (0xB4) /* Priority Register B for Slave 6 */
+#define AT91SAM9X5_MATRIX_PRAS7 (0xB8) /* Priority Register A for Slave 7 */
+#define AT91SAM9X5_MATRIX_PRBS7 (0xBC) /* Priority Register B for Slave 7 */
+#define AT91SAM9X5_MATRIX_PRAS8 (0xC0) /* Priority Register A for Slave 8 */
+#define AT91SAM9X5_MATRIX_PRBS8 (0xC4) /* Priority Register B for Slave 8 */
+#define AT91SAM9X5_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
+#define AT91SAM9X5_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
+#define AT91SAM9X5_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
+#define AT91SAM9X5_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
+#define AT91SAM9X5_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
+#define AT91SAM9X5_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
+#define AT91SAM9X5_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
+#define AT91SAM9X5_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
+#define AT91SAM9X5_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
+#define AT91SAM9X5_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
-#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
-#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
-#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
-#define AT91_MATRIX_RCB2 (1 << 2)
-#define AT91_MATRIX_RCB3 (1 << 3)
-#define AT91_MATRIX_RCB4 (1 << 4)
-#define AT91_MATRIX_RCB5 (1 << 5)
-#define AT91_MATRIX_RCB6 (1 << 6)
-#define AT91_MATRIX_RCB7 (1 << 7)
-#define AT91_MATRIX_RCB8 (1 << 8)
-#define AT91_MATRIX_RCB9 (1 << 9)
-#define AT91_MATRIX_RCB10 (1 << 10)
-#define AT91_MATRIX_RCB11 (1 << 11)
+#define AT91SAM9X5_MATRIX_MRCR (0x100) /* Master Remap Control Register */
+#define AT91SAM9X5_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
+#define AT91SAM9X5_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
+#define AT91SAM9X5_MATRIX_RCB2 (1 << 2)
+#define AT91SAM9X5_MATRIX_RCB3 (1 << 3)
+#define AT91SAM9X5_MATRIX_RCB4 (1 << 4)
+#define AT91SAM9X5_MATRIX_RCB5 (1 << 5)
+#define AT91SAM9X5_MATRIX_RCB6 (1 << 6)
+#define AT91SAM9X5_MATRIX_RCB7 (1 << 7)
+#define AT91SAM9X5_MATRIX_RCB8 (1 << 8)
+#define AT91SAM9X5_MATRIX_RCB9 (1 << 9)
+#define AT91SAM9X5_MATRIX_RCB10 (1 << 10)
+#define AT91SAM9X5_MATRIX_RCB11 (1 << 11)
-#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
-#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
-#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
-#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
-#define AT91_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
-#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
-#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
-#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
-#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
-#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
-#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
-#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
-#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
-#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
-#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
-#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
-#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
-#define AT91_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
-#define AT91_MATRIX_NFD0_ON_D0 (0 << 24)
-#define AT91_MATRIX_NFD0_ON_D16 (1 << 24)
-#define AT91_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
-#define AT91_MATRIX_MP_OFF (0 << 25)
-#define AT91_MATRIX_MP_ON (1 << 25)
+#define AT91SAM9X5_MATRIX_EBICSA (0x120) /* EBI Chip Select Assignment Register */
+#define AT91SAM9X5_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91SAM9X5_MATRIX_EBI_CS1A_SMC (0 << 1)
+#define AT91SAM9X5_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91SAM9X5_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
+#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC (0 << 3)
+#define AT91SAM9X5_MATRIX_EBI_CS3A_SMC_NANDFLASH (1 << 3)
+#define AT91SAM9X5_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
+#define AT91SAM9X5_MATRIX_EBI_DBPU_ON (0 << 8)
+#define AT91SAM9X5_MATRIX_EBI_DBPU_OFF (1 << 8)
+#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
+#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
+#define AT91SAM9X5_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
+#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
+#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
+#define AT91SAM9X5_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
+#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
+#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
+#define AT91SAM9X5_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
+#define AT91SAM9X5_MATRIX_NFD0_SELECT (1 << 24) /* NAND Flash Data Bus Selection */
+#define AT91SAM9X5_MATRIX_NFD0_ON_D0 (0 << 24)
+#define AT91SAM9X5_MATRIX_NFD0_ON_D16 (1 << 24)
+#define AT91SAM9X5_MATRIX_DDR_MP_EN (1 << 25) /* DDR Multi-port Enable */
+#define AT91SAM9X5_MATRIX_MP_OFF (0 << 25)
+#define AT91SAM9X5_MATRIX_MP_ON (1 << 25)
-#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
-#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
-#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
-#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
-#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
+#define AT91SAM9X5_MATRIX_WPMR (0x1E4) /* Write Protect Mode Register */
+#define AT91SAM9X5_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
+#define AT91SAM9X5_MATRIX_WPMR_WP_WPDIS (0 << 0)
+#define AT91SAM9X5_MATRIX_WPMR_WP_WPEN (1 << 0)
+#define AT91SAM9X5_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
-#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
-#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
-#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
-#define AT91_MATRIX_WPSR_WPV (1 << 0)
-#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
+#define AT91SAM9X5_MATRIX_WPSR (0x1E8) /* Write Protect Status Register */
+#define AT91SAM9X5_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
+#define AT91SAM9X5_MATRIX_WPSR_NO_WPV (0 << 0)
+#define AT91SAM9X5_MATRIX_WPSR_WPV (1 << 0)
+#define AT91SAM9X5_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#endif
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 18427114d1..9d45323a53 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -30,6 +30,9 @@
#include <asm/byteorder.h>
#include <mach/hardware.h>
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
+#include <mach/at91sam9261.h>
+#endif
#include <mach/io.h>
#include <mach/board.h>
#include <mach/cpu.h>
@@ -691,10 +694,12 @@ static void pullup(struct at91_udc *udc, int is_on)
txvc |= AT91_UDP_TXVC_PUON;
at91_udp_write(udc, AT91_UDP_TXVC, txvc);
} else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) {
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
u32 usbpucr;
- usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR);
- usbpucr |= AT91_MATRIX_USBPUCR_PUON;
- at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr);
+ usbpucr = readl(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+ usbpucr |= AT91SAM9261_MATRIX_USBPUCR_PUON;
+ writel(usbpucr, AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+#endif
}
} else {
stop_activity(udc);
@@ -708,10 +713,12 @@ static void pullup(struct at91_udc *udc, int is_on)
txvc &= ~AT91_UDP_TXVC_PUON;
at91_udp_write(udc, AT91_UDP_TXVC, txvc);
} else if (cpu_is_at91sam9261() || cpu_is_at91sam9g10()) {
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
u32 usbpucr;
- usbpucr = at91_sys_read(AT91_MATRIX_USBPUCR);
- usbpucr &= ~AT91_MATRIX_USBPUCR_PUON;
- at91_sys_write(AT91_MATRIX_USBPUCR, usbpucr);
+ usbpucr = readl(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+ usbpucr &= ~AT91SAM9261_MATRIX_USBPUCR_PUON;
+ writel(usbpucr, AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_USBPUCR);
+#endif
}
clk_off(udc);
}
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 11/22] ARM: at91: Use SoC specific base addresses where appropriate
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (9 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 10/22] ARM: at91: Add SoC namespace to matrix defines Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 12/22] ARM: at91rm9200: Add SoC namespace to memory controller defines Sascha Hauer
` (12 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
Replace AT91_ base addresses with their SoC specific variants where
possible.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/animeo_ip/init.c | 2 +-
arch/arm/mach-at91/at91rm9200_devices.c | 2 +-
arch/arm/mach-at91/at91sam9260_devices.c | 6 +++---
arch/arm/mach-at91/at91sam9261_devices.c | 2 +-
arch/arm/mach-at91/at91sam9263_devices.c | 6 +++---
arch/arm/mach-at91/at91sam9g45_devices.c | 6 +++---
arch/arm/mach-at91/at91sam9n12_devices.c | 10 +++++-----
arch/arm/mach-at91/at91sam9x5_devices.c | 10 +++++-----
8 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index 775c818df6..117d834624 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -327,7 +327,7 @@ static void animeo_ip_shutdown(void)
* so linux can detect that we only enable the uart2
* and use it for decompress
*/
- animeo_ip_shutdown_uart(IOMEM(AT91_DBGU + AT91_BASE_SYS));
+ animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_DBGU));
animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US0));
animeo_ip_shutdown_uart(IOMEM(AT91SAM9260_BASE_US1));
}
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index a110ee3e3c..b4d7cb1e24 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -253,7 +253,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA30, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA31, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91RM9200_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index c5323e2cb2..9b8654f400 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -132,8 +132,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_ECC,
- .end = AT91_BASE_SYS + AT91_ECC + 512 - 1,
+ .start = AT91SAM9260_BASE_ECC,
+ .end = AT91SAM9260_BASE_ECC + 512 - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -266,7 +266,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PB14, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PB15, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9260_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 9b7703ee97..3b869f923c 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -270,7 +270,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9261_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index ab3968eae2..877acc0df7 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -126,8 +126,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_ECC0,
- .end = AT91_BASE_SYS + AT91_ECC0 + 512 - 1,
+ .start = AT91SAM9263_BASE_ECC0,
+ .end = AT91SAM9263_BASE_ECC0 + 512 - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -301,7 +301,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PC30, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PC31, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9263_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index b44273a0de..ae4bd50c4b 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -128,8 +128,8 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_ECC,
- .end = AT91_BASE_SYS + AT91_ECC + 512 - 1,
+ .start = AT91SAM9G45_BASE_ECC,
+ .end = AT91SAM9G45_BASE_ECC + 512 - 1,
.flags = IORESOURCE_MEM,
}
};
@@ -218,7 +218,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PB12, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PB13, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9G45_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index e38fc77363..3c606d5a4d 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -133,13 +133,13 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_PMECC,
- .end = AT91_BASE_SYS + AT91_PMECC + 0x600 - 1,
+ .start = AT91SAM9N12_BASE_PMECC,
+ .end = AT91SAM9N12_BASE_PMECC + 0x600 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = AT91_BASE_SYS + AT91_PMERRLOC,
- .end = AT91_BASE_SYS + AT91_PMERRLOC + 0x200 - 1,
+ .start = AT91SAM9N12_BASE_PMERRLOC,
+ .end = AT91SAM9N12_BASE_PMERRLOC + 0x200 - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
@@ -373,7 +373,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9N12_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index e21bd598c9..b8035c1acf 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -225,13 +225,13 @@ static struct resource nand_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = AT91_BASE_SYS + AT91_PMECC,
- .end = AT91_BASE_SYS + AT91_PMECC + 0x600 - 1,
+ .start = AT91SAM9X5_BASE_PMECC,
+ .end = AT91SAM9X5_BASE_PMECC + 0x600 - 1,
.flags = IORESOURCE_MEM,
},
[2] = {
- .start = AT91_BASE_SYS + AT91_PMERRLOC,
- .end = AT91_BASE_SYS + AT91_PMERRLOC + 0x200 - 1,
+ .start = AT91SAM9X5_BASE_PMERRLOC,
+ .end = AT91SAM9X5_BASE_PMERRLOC + 0x200 - 1,
.flags = IORESOURCE_MEM,
},
[3] = {
@@ -457,7 +457,7 @@ resource_size_t __init at91_configure_dbgu(void)
at91_set_A_periph(AT91_PIN_PA9, 1); /* DRXD */
at91_set_A_periph(AT91_PIN_PA10, 0); /* DTXD */
- return AT91_BASE_SYS + AT91_DBGU;
+ return AT91SAM9X5_BASE_DBGU;
}
resource_size_t __init at91_configure_usart0(unsigned pins)
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 12/22] ARM: at91rm9200: Add SoC namespace to memory controller defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (10 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 11/22] ARM: at91: Use SoC specific base addresses where appropriate Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 13/22] ARM: at91: remove unused header file Sascha Hauer
` (11 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91rm9200ek/config.h | 26 +-
arch/arm/boards/at91rm9200ek/lowlevel.c | 19 +-
arch/arm/mach-at91/at91rm9200_devices.c | 18 +-
.../mach-at91/include/mach/at91rm9200_mc.h | 274 +++++++++---------
4 files changed, 171 insertions(+), 166 deletions(-)
diff --git a/arch/arm/boards/at91rm9200ek/config.h b/arch/arm/boards/at91rm9200ek/config.h
index 070c9a171c..5f4f6fe1ae 100644
--- a/arch/arm/boards/at91rm9200ek/config.h
+++ b/arch/arm/boards/at91rm9200ek/config.h
@@ -30,30 +30,30 @@
/* flash */
#define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
#define CONFIG_SYS_SMC_CSR0_VAL \
- (AT91_SMC_NWS_(4) | /* Number of Wait States */ \
- AT91_SMC_WSEN | /* Wait State Enable */ \
- AT91_SMC_TDF_(2) | /* Data Float Time */ \
- AT91_SMC_BAT | /* Byte Access Type */ \
- AT91_SMC_DBW_16) /* Data Bus Width */
+ (AT91RM9200_SMC_NWS_(4) | /* Number of Wait States */ \
+ AT91RM9200_SMC_WSEN | /* Wait State Enable */ \
+ AT91RM9200_SMC_TDF_(2) | /* Data Float Time */ \
+ AT91RM9200_SMC_BAT | /* Byte Access Type */ \
+ AT91RM9200_SMC_DBW_16) /* Data Bus Width */
/* sdram */
#define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
#define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
#define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
#define CONFIG_SYS_EBI_CSA_VAL \
- (AT91_EBI_CS0A_SMC | \
- AT91_EBI_CS1A_SDRAMC | \
- AT91_EBI_CS3A_SMC | \
- AT91_EBI_CS4A_SMC) \
+ (AT91RM9200_EBI_CS0A_SMC | \
+ AT91RM9200_EBI_CS1A_SDRAMC | \
+ AT91RM9200_EBI_CS3A_SMC | \
+ AT91RM9200_EBI_CS4A_SMC) \
/* SDRAM */
/* SDRAMC_MR Mode register */
/* SDRAMC_CR - Configuration register*/
#define CONFIG_SYS_SDRC_CR_VAL \
- (AT91_SDRAMC_NC_9 | \
- AT91_SDRAMC_NR_12 | \
- AT91_SDRAMC_NB_4 | \
- AT91_SDRAMC_CAS_2 | \
+ (AT91RM9200_SDRAMC_NC_9 | \
+ AT91RM9200_SDRAMC_NR_12 | \
+ AT91RM9200_SDRAMC_NB_4 | \
+ AT91RM9200_SDRAMC_CAS_2 | \
(1 << 8) | /* Write Recovery Delay */ \
(12 << 12) | /* Row Cycle Delay */ \
(8 << 16) | /* Row Precharge Delay */ \
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index acff615779..3fb6ca3381 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -25,6 +25,7 @@ void __naked __bare_init barebox_arm_reset_vector(void)
{
u32 r;
int i;
+ void __iomem *mc = IOMEM(AT91RM9200_BASE_MC);
arm_cpu_lowlevel_init();
@@ -47,12 +48,12 @@ void __naked __bare_init barebox_arm_reset_vector(void)
/*
* EBI_CFGR
*/
- at91_sys_write(AT91_EBI_CFGR, CONFIG_SYS_EBI_CFGR_VAL);
+ __raw_writel(CONFIG_SYS_EBI_CFGR_VAL, mc + AT91RM9200_EBI_CFGR);
/*
* SMC2_CSR[0]: 16bit, 2 TDF, 4 WS
*/
- at91_sys_write(AT91_SMC_CSR(0), CONFIG_SYS_SMC_CSR0_VAL);
+ __raw_writel(CONFIG_SYS_SMC_CSR0_VAL, mc + AT91RM9200_SMC_CSR(0));
/*
* Init Clocks
@@ -93,31 +94,31 @@ void __naked __bare_init barebox_arm_reset_vector(void)
__raw_writel(CONFIG_SYS_PIOC_PDR_VAL, AT91RM9200_BASE_PIOC + PIO_PDR);
/* EBI_CSA : CS1=SDRAM */
- at91_sys_write(AT91_EBI_CSA, CONFIG_SYS_EBI_CSA_VAL);
+ __raw_writel(CONFIG_SYS_EBI_CSA_VAL, mc + AT91RM9200_EBI_CSA);
/* SDRC_CR */
- at91_sys_write(AT91_SDRAMC_CR, CONFIG_SYS_SDRC_CR_VAL);
+ __raw_writel(CONFIG_SYS_SDRC_CR_VAL, mc + AT91RM9200_SDRAMC_CR);
/* SDRC_MR : Precharge All */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_PRECHARGE);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_PRECHARGE, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
/* SDRC_MR : refresh */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_REFRESH);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_REFRESH, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM 8 times */
for (i = 0; i < 8; i++)
access_sdram();
/* SDRC_MR : Load Mode Register */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_LMR);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_LMR, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
/* SDRC_TR : Write refresh rate */
- at91_sys_write(AT91_SDRAMC_TR, CONFIG_SYS_SDRC_TR_VAL);
+ __raw_writel(CONFIG_SYS_SDRC_TR_VAL, mc + AT91RM9200_SDRAMC_TR);
/* access SDRAM */
access_sdram();
/* SDRC_MR : Normal Mode */
- at91_sys_write(AT91_SDRAMC_MR, AT91_SDRAMC_MODE_NORMAL);
+ __raw_writel(AT91RM9200_SDRAMC_MODE_NORMAL, mc + AT91RM9200_SDRAMC_MR);
/* access SDRAM */
access_sdram();
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index b4d7cb1e24..2563b6c834 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -135,15 +135,19 @@ void __init at91_add_device_nand(struct atmel_nand_data *data)
return;
/* enable the address range of CS3 */
- csa = at91_sys_read(AT91_EBI_CSA);
- at91_sys_write(AT91_EBI_CSA, csa | AT91_EBI_CS3A_SMC_SMARTMEDIA);
+ csa = readl(AT91RM9200_BASE_MC + AT91RM9200_EBI_CSA);
+ csa |= AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA;
+ writel(csa, AT91RM9200_BASE_MC + AT91RM9200_EBI_CSA);
/* set the bus interface characteristics */
- at91_sys_write(AT91_SMC_CSR(3), AT91_SMC_ACSS_STD | AT91_SMC_DBW_8 | AT91_SMC_WSEN
- | AT91_SMC_NWS_(5)
- | AT91_SMC_TDF_(1)
- | AT91_SMC_RWSETUP_(0) /* tDS Data Set up Time 30 - ns */
- | AT91_SMC_RWHOLD_(1) /* tDH Data Hold Time 20 - ns */
+ writel(AT91RM9200_SMC_ACSS_STD |
+ AT91RM9200_SMC_DBW_8 |
+ AT91RM9200_SMC_WSEN |
+ AT91RM9200_SMC_NWS_(5) |
+ AT91RM9200_SMC_TDF_(1) |
+ AT91RM9200_SMC_RWSETUP_(0) | /* tDS Data Set up Time 30 - ns */
+ AT91RM9200_SMC_RWHOLD_(1), /* tDH Data Hold Time 20 - ns */
+ AT91RM9200_BASE_MC + AT91RM9200_SMC_CSR(3)
);
/* enable pin */
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index fc44a61090..14da76b85a 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -17,145 +17,145 @@
#define AT91RM9200_MC_H
/* Memory Controller */
-#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
-#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
-
-#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
-#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
-#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
-#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
-#define AT91_MC_ABTSZ_BYTE (0 << 8)
-#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
-#define AT91_MC_ABTSZ_WORD (2 << 8)
-#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
-#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
-#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
-#define AT91_MC_ABTTYP_FETCH (2 << 10)
-#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
-#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
-#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
-#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
-#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
-#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
-#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
-#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
-
-#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
-
-#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
-#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
-#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
-#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
-#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
+#define AT91RM9200_MC_RCR (0x00) /* MC Remap Control Register */
+#define AT91RM9200_MC_RCB (1 << 0) /* Remap Command Bit */
+
+#define AT91RM9200_MC_ASR (0x04) /* MC Abort Status Register */
+#define AT91RM9200_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
+#define AT91RM9200_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
+#define AT91RM9200_MC_ABTSZ (3 << 8) /* Abort Size Status */
+#define AT91RM9200_MC_ABTSZ_BYTE (0 << 8)
+#define AT91RM9200_MC_ABTSZ_HALFWORD (1 << 8)
+#define AT91RM9200_MC_ABTSZ_WORD (2 << 8)
+#define AT91RM9200_MC_ABTTYP (3 << 10) /* Abort Type Status */
+#define AT91RM9200_MC_ABTTYP_DATAREAD (0 << 10)
+#define AT91RM9200_MC_ABTTYP_DATAWRITE (1 << 10)
+#define AT91RM9200_MC_ABTTYP_FETCH (2 << 10)
+#define AT91RM9200_MC_MST0 (1 << 16) /* ARM920T Abort Source */
+#define AT91RM9200_MC_MST1 (1 << 17) /* PDC Abort Source */
+#define AT91RM9200_MC_MST2 (1 << 18) /* UHP Abort Source */
+#define AT91RM9200_MC_MST3 (1 << 19) /* EMAC Abort Source */
+#define AT91RM9200_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
+#define AT91RM9200_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
+#define AT91RM9200_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
+#define AT91RM9200_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
+
+#define AT91RM9200_MC_AASR (0x08) /* MC Abort Address Status Register */
+
+#define AT91RM9200_MC_MPR (0x0c) /* MC Master Priority Register */
+#define AT91RM9200_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
+#define AT91RM9200_MPR_MSTP1 (7 << 4) /* PDC Priority */
+#define AT91RM9200_MPR_MSTP2 (7 << 8) /* UHP Priority */
+#define AT91RM9200_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
-#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
-#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
-#define AT91_EBI_CS0A_SMC (0 << 0)
-#define AT91_EBI_CS0A_BFC (1 << 0)
-#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
-#define AT91_EBI_CS1A_SMC (0 << 1)
-#define AT91_EBI_CS1A_SDRAMC (1 << 1)
-#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
-#define AT91_EBI_CS3A_SMC (0 << 3)
-#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
-#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
-#define AT91_EBI_CS4A_SMC (0 << 4)
-#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
-#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
-#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
+#define AT91RM9200_EBI_CSA (0x60) /* Chip Select Assignment Register */
+#define AT91RM9200_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
+#define AT91RM9200_EBI_CS0A_SMC (0 << 0)
+#define AT91RM9200_EBI_CS0A_BFC (1 << 0)
+#define AT91RM9200_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
+#define AT91RM9200_EBI_CS1A_SMC (0 << 1)
+#define AT91RM9200_EBI_CS1A_SDRAMC (1 << 1)
+#define AT91RM9200_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
+#define AT91RM9200_EBI_CS3A_SMC (0 << 3)
+#define AT91RM9200_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
+#define AT91RM9200_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
+#define AT91RM9200_EBI_CS4A_SMC (0 << 4)
+#define AT91RM9200_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
+#define AT91RM9200_EBI_CFGR (0x64) /* Configuration Register */
+#define AT91RM9200_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
-#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
-#define AT91_SMC_NWS_(x) ((x) << 0)
-#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
-#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
-#define AT91_SMC_TDF_(x) ((x) << 8)
-#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
-#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
-#define AT91_SMC_DBW_16 (1 << 13)
-#define AT91_SMC_DBW_8 (2 << 13)
-#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
-#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
-#define AT91_SMC_ACSS_STD (0 << 16)
-#define AT91_SMC_ACSS_1 (1 << 16)
-#define AT91_SMC_ACSS_2 (2 << 16)
-#define AT91_SMC_ACSS_3 (3 << 16)
-#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
-#define AT91_SMC_RWSETUP_(x) ((x) << 24)
-#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
-#define AT91_SMC_RWHOLD_(x) ((x) << 28)
+#define AT91RM9200_SMC_CSR(n) (0x70 + ((n) * 4))/* SMC Chip Select Register */
+#define AT91RM9200_SMC_NWS (0x7f << 0) /* Number of Wait States */
+#define AT91RM9200_SMC_NWS_(x) ((x) << 0)
+#define AT91RM9200_SMC_WSEN (1 << 7) /* Wait State Enable */
+#define AT91RM9200_SMC_TDF (0xf << 8) /* Data Float Time */
+#define AT91RM9200_SMC_TDF_(x) ((x) << 8)
+#define AT91RM9200_SMC_BAT (1 << 12) /* Byte Access Type */
+#define AT91RM9200_SMC_DBW (3 << 13) /* Data Bus Width */
+#define AT91RM9200_SMC_DBW_16 (1 << 13)
+#define AT91RM9200_SMC_DBW_8 (2 << 13)
+#define AT91RM9200_SMC_DPR (1 << 15) /* Data Read Protocol */
+#define AT91RM9200_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
+#define AT91RM9200_SMC_ACSS_STD (0 << 16)
+#define AT91RM9200_SMC_ACSS_1 (1 << 16)
+#define AT91RM9200_SMC_ACSS_2 (2 << 16)
+#define AT91RM9200_SMC_ACSS_3 (3 << 16)
+#define AT91RM9200_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
+#define AT91RM9200_SMC_RWSETUP_(x) ((x) << 24)
+#define AT91RM9200_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
+#define AT91RM9200_SMC_RWHOLD_(x) ((x) << 28)
/* SDRAM Controller registers */
-#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
-#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
-#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
-#define AT91_SDRAMC_MODE_NOP (1 << 0)
-#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
-#define AT91_SDRAMC_MODE_LMR (3 << 0)
-#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
-#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
-#define AT91_SDRAMC_DBW_32 (0 << 4)
-#define AT91_SDRAMC_DBW_16 (1 << 4)
-
-#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
-#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
-
-#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
-#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
-#define AT91_SDRAMC_NC_8 (0 << 0)
-#define AT91_SDRAMC_NC_9 (1 << 0)
-#define AT91_SDRAMC_NC_10 (2 << 0)
-#define AT91_SDRAMC_NC_11 (3 << 0)
-#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
-#define AT91_SDRAMC_NR_11 (0 << 2)
-#define AT91_SDRAMC_NR_12 (1 << 2)
-#define AT91_SDRAMC_NR_13 (2 << 2)
-#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
-#define AT91_SDRAMC_NB_2 (0 << 4)
-#define AT91_SDRAMC_NB_4 (1 << 4)
-#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
-#define AT91_SDRAMC_CAS_2 (2 << 5)
-#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
-#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
-#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
-#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
-#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
-#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
-
-#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
-#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
-#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
-#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
-#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
-#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
+#define AT91RM9200_SDRAMC_MR (0x90) /* Mode Register */
+#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
+#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
+#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
+#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
+#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
+#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
+#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
+#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
+#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
+
+#define AT91RM9200_SDRAMC_TR (0x94) /* Refresh Timer Register */
+#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
+
+#define AT91RM9200_SDRAMC_CR (0x98) /* Configuration Register */
+#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
+#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
+#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
+#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
+#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
+#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
+#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
+#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
+#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
+#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
+#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
+#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
+#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
+#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
+#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
+#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
+#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
+#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
+#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
+#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
+
+#define AT91RM9200_SDRAMC_SRR (0x9c) /* Self Refresh Register */
+#define AT91RM9200_SDRAMC_LPR (0xa0) /* Low Power Register */
+#define AT91RM9200_SDRAMC_IER (0xa4) /* Interrupt Enable Register */
+#define AT91RM9200_SDRAMC_IDR (0xa8) /* Interrupt Disable Register */
+#define AT91RM9200_SDRAMC_IMR (0xac) /* Interrupt Mask Register */
+#define AT91RM9200_SDRAMC_ISR (0xb0) /* Interrupt Status Register */
/* Burst Flash Controller register */
-#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
-#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
-#define AT91_BFC_BFCOM_DISABLED (0 << 0)
-#define AT91_BFC_BFCOM_ASYNC (1 << 0)
-#define AT91_BFC_BFCOM_BURST (2 << 0)
-#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
-#define AT91_BFC_BFCC_MCK (1 << 2)
-#define AT91_BFC_BFCC_DIV2 (2 << 2)
-#define AT91_BFC_BFCC_DIV4 (3 << 2)
-#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
-#define AT91_BFC_PAGES (7 << 8) /* Page Size */
-#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
-#define AT91_BFC_PAGES_16 (1 << 8)
-#define AT91_BFC_PAGES_32 (2 << 8)
-#define AT91_BFC_PAGES_64 (3 << 8)
-#define AT91_BFC_PAGES_128 (4 << 8)
-#define AT91_BFC_PAGES_256 (5 << 8)
-#define AT91_BFC_PAGES_512 (6 << 8)
-#define AT91_BFC_PAGES_1024 (7 << 8)
-#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
-#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
-#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
-#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
-#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
+#define AT91RM9200_BFC_MR (0xc0) /* Mode Register */
+#define AT91RM9200_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
+#define AT91RM9200_BFC_BFCOM_DISABLED (0 << 0)
+#define AT91RM9200_BFC_BFCOM_ASYNC (1 << 0)
+#define AT91RM9200_BFC_BFCOM_BURST (2 << 0)
+#define AT91RM9200_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
+#define AT91RM9200_BFC_BFCC_MCK (1 << 2)
+#define AT91RM9200_BFC_BFCC_DIV2 (2 << 2)
+#define AT91RM9200_BFC_BFCC_DIV4 (3 << 2)
+#define AT91RM9200_BFC_AVL (0xf << 4) /* Address Valid Latency */
+#define AT91RM9200_BFC_PAGES (7 << 8) /* Page Size */
+#define AT91RM9200_BFC_PAGES_NO_PAGE (0 << 8)
+#define AT91RM9200_BFC_PAGES_16 (1 << 8)
+#define AT91RM9200_BFC_PAGES_32 (2 << 8)
+#define AT91RM9200_BFC_PAGES_64 (3 << 8)
+#define AT91RM9200_BFC_PAGES_128 (4 << 8)
+#define AT91RM9200_BFC_PAGES_256 (5 << 8)
+#define AT91RM9200_BFC_PAGES_512 (6 << 8)
+#define AT91RM9200_BFC_PAGES_1024 (7 << 8)
+#define AT91RM9200_BFC_OEL (3 << 12) /* Output Enable Latency */
+#define AT91RM9200_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
+#define AT91RM9200_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
+#define AT91RM9200_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
+#define AT91RM9200_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#ifndef __ASSEMBLY__
#include <mach/io.h>
@@ -164,8 +164,8 @@ static inline u32 at91rm9200_get_sdram_size(void)
u32 cr, mr;
u32 size;
- cr = at91_sys_read(AT91_SDRAMC_CR);
- mr = at91_sys_read(AT91_SDRAMC_MR);
+ cr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_CR);
+ mr = readl(AT91RM9200_BASE_MC + AT91RM9200_SDRAMC_MR);
/* Formula:
* size = bank << (col + row + 1);
@@ -174,13 +174,13 @@ static inline u32 at91rm9200_get_sdram_size(void)
*/
size = 1;
/* COL */
- size += (cr & AT91_SDRAMC_NC) + 8;
+ size += (cr & AT91RM9200_SDRAMC_NC) + 8;
/* ROW */
- size += ((cr & AT91_SDRAMC_NR) >> 2) + 11;
+ size += ((cr & AT91RM9200_SDRAMC_NR) >> 2) + 11;
/* BANK */
- size = ((cr & AT91_SDRAMC_NB) ? 4 : 2) << size;
+ size = ((cr & AT91RM9200_SDRAMC_NB) ? 4 : 2) << size;
/* bandwidth */
- if (!(mr & AT91_SDRAMC_DBW))
+ if (!(mr & AT91RM9200_SDRAMC_DBW))
size <<= 1;
return size;
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 13/22] ARM: at91: remove unused header file
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (11 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 12/22] ARM: at91rm9200: Add SoC namespace to memory controller defines Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 14/22] ARM: at91rm9200 timer: remove unused include Sascha Hauer
` (10 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
nothing from mach/at91_tc.h is used, remove it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/at91rm9200_time.c | 1 -
arch/arm/mach-at91/include/mach/at91_tc.h | 146 ----------------------
2 files changed, 147 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91_tc.h
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index fd11223b6f..f09483a7cc 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -30,7 +30,6 @@
#include <clock.h>
#include <restart.h>
#include <mach/hardware.h>
-#include <mach/at91_tc.h>
#include <mach/at91_st.h>
#include <mach/at91_pmc.h>
#include <mach/io.h>
diff --git a/arch/arm/mach-at91/include/mach/at91_tc.h b/arch/arm/mach-at91/include/mach/at91_tc.h
deleted file mode 100644
index 5a064b4847..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_tc.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * [origin: Linux kernel arch/arm/mach-at91/include/mach/at91_tc.h]
- *
- * Copyright (C) SAN People
- *
- * Timer/Counter Unit (TC) registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_TC_H
-#define AT91_TC_H
-
-#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
-#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
-
-#define AT91_TC_BMR 0xc4 /* TC Block Mode Register */
-#define AT91_TC_TC0XC0S (3 << 0) /* External Clock Signal 0 Selection */
-#define AT91_TC_TC0XC0S_TCLK0 (0 << 0)
-#define AT91_TC_TC0XC0S_NONE (1 << 0)
-#define AT91_TC_TC0XC0S_TIOA1 (2 << 0)
-#define AT91_TC_TC0XC0S_TIOA2 (3 << 0)
-#define AT91_TC_TC1XC1S (3 << 2) /* External Clock Signal 1 Selection */
-#define AT91_TC_TC1XC1S_TCLK1 (0 << 2)
-#define AT91_TC_TC1XC1S_NONE (1 << 2)
-#define AT91_TC_TC1XC1S_TIOA0 (2 << 2)
-#define AT91_TC_TC1XC1S_TIOA2 (3 << 2)
-#define AT91_TC_TC2XC2S (3 << 4) /* External Clock Signal 2 Selection */
-#define AT91_TC_TC2XC2S_TCLK2 (0 << 4)
-#define AT91_TC_TC2XC2S_NONE (1 << 4)
-#define AT91_TC_TC2XC2S_TIOA0 (2 << 4)
-#define AT91_TC_TC2XC2S_TIOA1 (3 << 4)
-
-
-#define AT91_TC_CCR 0x00 /* Channel Control Register */
-#define AT91_TC_CLKEN (1 << 0) /* Counter Clock Enable Command */
-#define AT91_TC_CLKDIS (1 << 1) /* Counter CLock Disable Command */
-#define AT91_TC_SWTRG (1 << 2) /* Software Trigger Command */
-
-#define AT91_TC_CMR 0x04 /* Channel Mode Register */
-#define AT91_TC_TCCLKS (7 << 0) /* Capture/Waveform Mode: Clock Selection */
-#define AT91_TC_TIMER_CLOCK1 (0 << 0)
-#define AT91_TC_TIMER_CLOCK2 (1 << 0)
-#define AT91_TC_TIMER_CLOCK3 (2 << 0)
-#define AT91_TC_TIMER_CLOCK4 (3 << 0)
-#define AT91_TC_TIMER_CLOCK5 (4 << 0)
-#define AT91_TC_XC0 (5 << 0)
-#define AT91_TC_XC1 (6 << 0)
-#define AT91_TC_XC2 (7 << 0)
-#define AT91_TC_CLKI (1 << 3) /* Capture/Waveform Mode: Clock Invert */
-#define AT91_TC_BURST (3 << 4) /* Capture/Waveform Mode: Burst Signal Selection */
-#define AT91_TC_LDBSTOP (1 << 6) /* Capture Mode: Counter Clock Stopped with TB Loading */
-#define AT91_TC_LDBDIS (1 << 7) /* Capture Mode: Counter Clock Disable with RB Loading */
-#define AT91_TC_ETRGEDG (3 << 8) /* Capture Mode: External Trigger Edge Selection */
-#define AT91_TC_ABETRG (1 << 10) /* Capture Mode: TIOA or TIOB External Trigger Selection */
-#define AT91_TC_CPCTRG (1 << 14) /* Capture Mode: RC Compare Trigger Enable */
-#define AT91_TC_WAVE (1 << 15) /* Capture/Waveform mode */
-#define AT91_TC_LDRA (3 << 16) /* Capture Mode: RA Loading Selection */
-#define AT91_TC_LDRB (3 << 18) /* Capture Mode: RB Loading Selection */
-
-#define AT91_TC_CPCSTOP (1 << 6) /* Waveform Mode: Counter Clock Stopped with RC Compare */
-#define AT91_TC_CPCDIS (1 << 7) /* Waveform Mode: Counter Clock Disable with RC Compare */
-#define AT91_TC_EEVTEDG (3 << 8) /* Waveform Mode: External Event Edge Selection */
-#define AT91_TC_EEVTEDG_NONE (0 << 8)
-#define AT91_TC_EEVTEDG_RISING (1 << 8)
-#define AT91_TC_EEVTEDG_FALLING (2 << 8)
-#define AT91_TC_EEVTEDG_BOTH (3 << 8)
-#define AT91_TC_EEVT (3 << 10) /* Waveform Mode: External Event Selection */
-#define AT91_TC_EEVT_TIOB (0 << 10)
-#define AT91_TC_EEVT_XC0 (1 << 10)
-#define AT91_TC_EEVT_XC1 (2 << 10)
-#define AT91_TC_EEVT_XC2 (3 << 10)
-#define AT91_TC_ENETRG (1 << 12) /* Waveform Mode: External Event Trigger Enable */
-#define AT91_TC_WAVESEL (3 << 13) /* Waveform Mode: Waveform Selection */
-#define AT91_TC_WAVESEL_UP (0 << 13)
-#define AT91_TC_WAVESEL_UP_AUTO (2 << 13)
-#define AT91_TC_WAVESEL_UPDOWN (1 << 13)
-#define AT91_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
-#define AT91_TC_ACPA (3 << 16) /* Waveform Mode: RA Compare Effect on TIOA */
-#define AT91_TC_ACPA_NONE (0 << 16)
-#define AT91_TC_ACPA_SET (1 << 16)
-#define AT91_TC_ACPA_CLEAR (2 << 16)
-#define AT91_TC_ACPA_TOGGLE (3 << 16)
-#define AT91_TC_ACPC (3 << 18) /* Waveform Mode: RC Compre Effect on TIOA */
-#define AT91_TC_ACPC_NONE (0 << 18)
-#define AT91_TC_ACPC_SET (1 << 18)
-#define AT91_TC_ACPC_CLEAR (2 << 18)
-#define AT91_TC_ACPC_TOGGLE (3 << 18)
-#define AT91_TC_AEEVT (3 << 20) /* Waveform Mode: External Event Effect on TIOA */
-#define AT91_TC_AEEVT_NONE (0 << 20)
-#define AT91_TC_AEEVT_SET (1 << 20)
-#define AT91_TC_AEEVT_CLEAR (2 << 20)
-#define AT91_TC_AEEVT_TOGGLE (3 << 20)
-#define AT91_TC_ASWTRG (3 << 22) /* Waveform Mode: Software Trigger Effect on TIOA */
-#define AT91_TC_ASWTRG_NONE (0 << 22)
-#define AT91_TC_ASWTRG_SET (1 << 22)
-#define AT91_TC_ASWTRG_CLEAR (2 << 22)
-#define AT91_TC_ASWTRG_TOGGLE (3 << 22)
-#define AT91_TC_BCPB (3 << 24) /* Waveform Mode: RB Compare Effect on TIOB */
-#define AT91_TC_BCPB_NONE (0 << 24)
-#define AT91_TC_BCPB_SET (1 << 24)
-#define AT91_TC_BCPB_CLEAR (2 << 24)
-#define AT91_TC_BCPB_TOGGLE (3 << 24)
-#define AT91_TC_BCPC (3 << 26) /* Waveform Mode: RC Compare Effect on TIOB */
-#define AT91_TC_BCPC_NONE (0 << 26)
-#define AT91_TC_BCPC_SET (1 << 26)
-#define AT91_TC_BCPC_CLEAR (2 << 26)
-#define AT91_TC_BCPC_TOGGLE (3 << 26)
-#define AT91_TC_BEEVT (3 << 28) /* Waveform Mode: External Event Effect on TIOB */
-#define AT91_TC_BEEVT_NONE (0 << 28)
-#define AT91_TC_BEEVT_SET (1 << 28)
-#define AT91_TC_BEEVT_CLEAR (2 << 28)
-#define AT91_TC_BEEVT_TOGGLE (3 << 28)
-#define AT91_TC_BSWTRG (3 << 30) /* Waveform Mode: Software Trigger Effect on TIOB */
-#define AT91_TC_BSWTRG_NONE (0 << 30)
-#define AT91_TC_BSWTRG_SET (1 << 30)
-#define AT91_TC_BSWTRG_CLEAR (2 << 30)
-#define AT91_TC_BSWTRG_TOGGLE (3 << 30)
-
-#define AT91_TC_CV 0x10 /* Counter Value */
-#define AT91_TC_RA 0x14 /* Register A */
-#define AT91_TC_RB 0x18 /* Register B */
-#define AT91_TC_RC 0x1c /* Register C */
-
-#define AT91_TC_SR 0x20 /* Status Register */
-#define AT91_TC_COVFS (1 << 0) /* Counter Overflow Status */
-#define AT91_TC_LOVRS (1 << 1) /* Load Overrun Status */
-#define AT91_TC_CPAS (1 << 2) /* RA Compare Status */
-#define AT91_TC_CPBS (1 << 3) /* RB Compare Status */
-#define AT91_TC_CPCS (1 << 4) /* RC Compare Status */
-#define AT91_TC_LDRAS (1 << 5) /* RA Loading Status */
-#define AT91_TC_LDRBS (1 << 6) /* RB Loading Status */
-#define AT91_TC_ETRGS (1 << 7) /* External Trigger Status */
-#define AT91_TC_CLKSTA (1 << 16) /* Clock Enabling Status */
-#define AT91_TC_MTIOA (1 << 17) /* TIOA Mirror */
-#define AT91_TC_MTIOB (1 << 18) /* TIOB Mirror */
-
-#define AT91_TC_IER 0x24 /* Interrupt Enable Register */
-#define AT91_TC_IDR 0x28 /* Interrupt Disable Register */
-#define AT91_TC_IMR 0x2c /* Interrupt Mask Register */
-
-#endif
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 14/22] ARM: at91rm9200 timer: remove unused include
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (12 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 13/22] ARM: at91: remove unused header file Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 15/22] ARM: at91rm9200 timer: Make system timer defines SoC specific Sascha Hauer
` (9 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
at91rm9200_time.c doesn't need anything from at91_pmc.h, remove the
inclusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/at91rm9200_time.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index f09483a7cc..259fdd508d 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -31,7 +31,6 @@
#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_st.h>
-#include <mach/at91_pmc.h>
#include <mach/io.h>
#include <io.h>
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 15/22] ARM: at91rm9200 timer: Make system timer defines SoC specific
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (13 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 14/22] ARM: at91rm9200 timer: remove unused include Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 16/22] ARM: at91: remove mach/io.h Sascha Hauer
` (8 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
- rename at91_st.h to at91rm9200_st.h
- rename prefix from AT91_ to AT91RM9200_
- remove register offset from System timer defines
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/at91rm9200_time.c | 14 +++---
arch/arm/mach-at91/include/mach/at91_st.h | 49 -------------------
.../mach-at91/include/mach/at91rm9200_st.h | 49 +++++++++++++++++++
3 files changed, 57 insertions(+), 55 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/at91_st.h
create mode 100644 arch/arm/mach-at91/include/mach/at91rm9200_st.h
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index 259fdd508d..ef85502f5e 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -30,10 +30,12 @@
#include <clock.h>
#include <restart.h>
#include <mach/hardware.h>
-#include <mach/at91_st.h>
+#include <mach/at91rm9200_st.h>
#include <mach/io.h>
#include <io.h>
+static void __iomem *st = IOMEM(AT91RM9200_BASE_ST);
+
/*
* The ST_CRTR is updated asynchronously to the master clock ... but
* the updates as seen by the CPU don't seem to be strictly monotonic.
@@ -43,9 +45,9 @@ uint64_t at91rm9200_clocksource_read(void)
{
unsigned long x1, x2;
- x1 = at91_sys_read(AT91_ST_CRTR);
+ x1 = readl(st + AT91RM9200_ST_CRTR);
do {
- x2 = at91_sys_read(AT91_ST_CRTR);
+ x2 = readl(st + AT91RM9200_ST_CRTR);
if (x1 == x2)
break;
x1 = x2;
@@ -65,7 +67,7 @@ static int clocksource_init (void)
* directly for the clocksource and all clockevents, after adjusting
* its prescaler from the 1 Hz default.
*/
- at91_sys_write(AT91_ST_RTMR, 1);
+ writel(1, st + AT91RM9200_ST_RTMR);
cs.mult = clocksource_hz2mult(AT91_SLOW_CLOCK, cs.shift);
@@ -81,8 +83,8 @@ static void __noreturn at91rm9200_restart_soc(struct restart_handler *rst)
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
- at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
- at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
+ writel(AT91RM9200_ST_RSTEN | AT91RM9200_ST_EXTEN | 1, st + AT91RM9200_ST_WDMR);
+ writel(AT91RM9200_ST_WDRST, st + AT91RM9200_ST_CR);
/* Not reached */
hang();
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
deleted file mode 100644
index 8847173e41..0000000000
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * arch/arm/mach-at91/include/mach/at91_st.h
- *
- * Copyright (C) 2005 Ivan Kokshaysky
- * Copyright (C) SAN People
- *
- * System Timer (ST) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#ifndef AT91_ST_H
-#define AT91_ST_H
-
-#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
-#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
-
-#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
-#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
-
-#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
-#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
-#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
-#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
-
-#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
-#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
-
-#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
-#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
-#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
-#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
-#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
-
-#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
-#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
-#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
-
-#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
-#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
-
-#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
-#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
-
-#endif
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_st.h b/arch/arm/mach-at91/include/mach/at91rm9200_st.h
new file mode 100644
index 0000000000..bd676a7081
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_st.h
@@ -0,0 +1,49 @@
+/*
+ * arch/arm/mach-at91/include/mach/at91_st.h
+ *
+ * Copyright (C) 2005 Ivan Kokshaysky
+ * Copyright (C) SAN People
+ *
+ * System Timer (ST) - System peripherals registers.
+ * Based on AT91RM9200 datasheet revision E.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91RM9200_ST_H
+#define AT91RM9200_ST_H
+
+#define AT91RM9200_ST_CR (0x00) /* Control Register */
+#define AT91RM9200_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
+
+#define AT91RM9200_ST_PIMR (0x04) /* Period Interval Mode Register */
+#define AT91RM9200_ST_PIV (0xffff << 0) /* Period Interval Value */
+
+#define AT91RM9200_ST_WDMR (0x08) /* Watchdog Mode Register */
+#define AT91RM9200_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
+#define AT91RM9200_ST_RSTEN (1 << 16) /* Reset Enable */
+#define AT91RM9200_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
+
+#define AT91RM9200_ST_RTMR (0x0c) /* Real-time Mode Register */
+#define AT91RM9200_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
+
+#define AT91RM9200_ST_SR (0x10) /* Status Register */
+#define AT91RM9200_ST_PITS (1 << 0) /* Period Interval Timer Status */
+#define AT91RM9200_ST_WDOVF (1 << 1) /* Watchdog Overflow */
+#define AT91RM9200_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
+#define AT91RM9200_ST_ALMS (1 << 3) /* Alarm Status */
+
+#define AT91RM9200_ST_IER (0x14) /* Interrupt Enable Register */
+#define AT91RM9200_ST_IDR (0x18) /* Interrupt Disable Register */
+#define AT91RM9200_ST_IMR (0x1c) /* Interrupt Mask Register */
+
+#define AT91RM9200_ST_RTAR (0x20) /* Real-time Alarm Register */
+#define AT91RM9200_ST_ALMV (0xfffff << 0) /* Alarm Value */
+
+#define AT91RM9200_ST_CRTR (0x24) /* Current Real-time Register */
+#define AT91RM9200_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
+
+#endif
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 16/22] ARM: at91: remove mach/io.h
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (14 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 15/22] ARM: at91rm9200 timer: Make system timer defines SoC specific Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 17/22] ARM: at91sam926x use writel rather than pmc accessor function Sascha Hauer
` (7 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
Remove at91_sys_read() and at91_sys_write() since these are no longer
used. This makes mach/io.h empty so remove that aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/animeo_ip/init.c | 1 -
arch/arm/boards/at91rm9200ek/init.c | 1 -
arch/arm/boards/at91sam9260ek/init.c | 1 -
arch/arm/boards/at91sam9261ek/init.c | 1 -
arch/arm/boards/at91sam9263ek/init.c | 1 -
arch/arm/boards/at91sam9263ek/of_init.c | 2 +-
arch/arm/boards/at91sam9m10g45ek/init.c | 1 -
arch/arm/boards/at91sam9m10ihd/init.c | 1 -
arch/arm/boards/at91sam9n12ek/init.c | 1 -
arch/arm/boards/at91sam9x5ek/init.c | 1 -
arch/arm/boards/dss11/init.c | 1 -
arch/arm/boards/haba-knx/init.c | 1 -
arch/arm/boards/pm9261/init.c | 1 -
arch/arm/boards/pm9263/init.c | 1 -
arch/arm/boards/pm9g45/init.c | 1 -
arch/arm/boards/qil-a926x/init.c | 1 -
arch/arm/boards/sama5d3_xplained/init.c | 1 -
arch/arm/boards/sama5d3xek/init.c | 1 -
arch/arm/boards/telit-evk-pro3/init.c | 1 -
arch/arm/boards/tny-a926x/init.c | 1 -
arch/arm/boards/usb-a926x/init.c | 1 -
arch/arm/mach-at91/at91rm9200_devices.c | 1 -
arch/arm/mach-at91/at91rm9200_time.c | 1 -
arch/arm/mach-at91/at91sam9260_devices.c | 1 -
arch/arm/mach-at91/at91sam9261_devices.c | 1 -
arch/arm/mach-at91/at91sam9263_devices.c | 1 -
arch/arm/mach-at91/at91sam9g45.c | 1 -
arch/arm/mach-at91/at91sam9g45_devices.c | 1 -
arch/arm/mach-at91/at91sam9n12.c | 1 -
arch/arm/mach-at91/at91sam9n12_devices.c | 1 -
arch/arm/mach-at91/at91sam9x5_devices.c | 1 -
arch/arm/mach-at91/clock.c | 1 -
.../mach-at91/include/mach/at91rm9200_mc.h | 3 +-
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 6 ++-
.../mach-at91/include/mach/at91sam9_sdramc.h | 5 ++-
arch/arm/mach-at91/include/mach/io.h | 38 -------------------
arch/arm/mach-at91/sam9_smc.c | 1 -
arch/arm/mach-at91/sama5d3.c | 1 -
arch/arm/mach-at91/sama5d3_devices.c | 1 -
arch/arm/mach-at91/sama5d4.c | 1 -
arch/arm/mach-at91/sama5d4_devices.c | 1 -
drivers/clocksource/timer-atmel-pit.c | 1 -
drivers/spi/atmel_spi.c | 1 -
drivers/usb/gadget/at91_udc.c | 2 +-
drivers/video/atmel_hlcdfb.c | 1 -
drivers/video/atmel_lcdfb.c | 1 -
46 files changed, 13 insertions(+), 83 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/io.h
diff --git a/arch/arm/boards/animeo_ip/init.c b/arch/arm/boards/animeo_ip/init.c
index 117d834624..07daaf4ffd 100644
--- a/arch/arm/boards/animeo_ip/init.c
+++ b/arch/arm/boards/animeo_ip/init.c
@@ -24,7 +24,6 @@
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
#include <local_mac_address.h>
diff --git a/arch/arm/boards/at91rm9200ek/init.c b/arch/arm/boards/at91rm9200ek/init.c
index 7626786e07..2d9318575c 100644
--- a/arch/arm/boards/at91rm9200ek/init.c
+++ b/arch/arm/boards/at91rm9200ek/init.c
@@ -31,7 +31,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <spi/spi.h>
static struct macb_platform_data ether_pdata = {
diff --git a/arch/arm/boards/at91sam9260ek/init.c b/arch/arm/boards/at91sam9260ek/init.c
index de74835d78..037f46a78d 100644
--- a/arch/arm/boards/at91sam9260ek/init.c
+++ b/arch/arm/boards/at91sam9260ek/init.c
@@ -24,7 +24,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_rstc.h>
#include <linux/clk.h>
diff --git a/arch/arm/boards/at91sam9261ek/init.c b/arch/arm/boards/at91sam9261ek/init.c
index 58f253b1a6..a469dba92e 100644
--- a/arch/arm/boards/at91sam9261ek/init.c
+++ b/arch/arm/boards/at91sam9261ek/init.c
@@ -32,7 +32,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91sam9_smc.h>
#include <platform_data/eth-dm9000.h>
diff --git a/arch/arm/boards/at91sam9263ek/init.c b/arch/arm/boards/at91sam9263ek/init.c
index b71cc55179..f7461ce041 100644
--- a/arch/arm/boards/at91sam9263ek/init.c
+++ b/arch/arm/boards/at91sam9263ek/init.c
@@ -35,7 +35,6 @@
#include <mach/board.h>
#include <mach/iomux.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
static struct atmel_nand_data nand_pdata = {
diff --git a/arch/arm/boards/at91sam9263ek/of_init.c b/arch/arm/boards/at91sam9263ek/of_init.c
index 98af5adfc0..259287ccb5 100644
--- a/arch/arm/boards/at91sam9263ek/of_init.c
+++ b/arch/arm/boards/at91sam9263ek/of_init.c
@@ -16,13 +16,13 @@
#include <envfs.h>
#include <init.h>
#include <gpio.h>
+#include <io.h>
#include <mach/at91sam9263_matrix.h>
#include <mach/at91sam9_smc.h>
#include <mach/at91_rtt.h>
#include <mach/hardware.h>
#include <mach/iomux.h>
-#include <mach/io.h>
static int add_smc_devices(void)
{
diff --git a/arch/arm/boards/at91sam9m10g45ek/init.c b/arch/arm/boards/at91sam9m10g45ek/init.c
index ee692630bf..2660104946 100644
--- a/arch/arm/boards/at91sam9m10g45ek/init.c
+++ b/arch/arm/boards/at91sam9m10g45ek/init.c
@@ -36,7 +36,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <gpio_keys.h>
#include <readkey.h>
diff --git a/arch/arm/boards/at91sam9m10ihd/init.c b/arch/arm/boards/at91sam9m10ihd/init.c
index de601d53b3..5008e0f67e 100644
--- a/arch/arm/boards/at91sam9m10ihd/init.c
+++ b/arch/arm/boards/at91sam9m10ihd/init.c
@@ -21,7 +21,6 @@
#include <linux/mtd/nand.h>
#include <mach/board.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91sam9_smc.h>
#include <input/qt1070.h>
diff --git a/arch/arm/boards/at91sam9n12ek/init.c b/arch/arm/boards/at91sam9n12ek/init.c
index bc3fb8e089..72c6ff84ee 100644
--- a/arch/arm/boards/at91sam9n12ek/init.c
+++ b/arch/arm/boards/at91sam9n12ek/init.c
@@ -32,7 +32,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/at91sam9x5ek/init.c b/arch/arm/boards/at91sam9x5ek/init.c
index 7ed6f58595..65493ebbcd 100644
--- a/arch/arm/boards/at91sam9x5ek/init.c
+++ b/arch/arm/boards/at91sam9x5ek/init.c
@@ -32,7 +32,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/dss11/init.c b/arch/arm/boards/dss11/init.c
index 432613ff4a..0d0b5e29bf 100644
--- a/arch/arm/boards/dss11/init.c
+++ b/arch/arm/boards/dss11/init.c
@@ -29,7 +29,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_rstc.h>
#include <linux/clk.h>
diff --git a/arch/arm/boards/haba-knx/init.c b/arch/arm/boards/haba-knx/init.c
index 4a000d9aed..55441b63af 100644
--- a/arch/arm/boards/haba-knx/init.c
+++ b/arch/arm/boards/haba-knx/init.c
@@ -35,7 +35,6 @@
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <led.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/pm9261/init.c b/arch/arm/boards/pm9261/init.c
index b0377d063c..33c2a542b2 100644
--- a/arch/arm/boards/pm9261/init.c
+++ b/arch/arm/boards/pm9261/init.c
@@ -34,7 +34,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <platform_data/eth-dm9000.h>
#include <linux/w1-gpio.h>
diff --git a/arch/arm/boards/pm9263/init.c b/arch/arm/boards/pm9263/init.c
index e9f8588649..30b3d26fbf 100644
--- a/arch/arm/boards/pm9263/init.c
+++ b/arch/arm/boards/pm9263/init.c
@@ -32,7 +32,6 @@
#include <linux/mtd/nand.h>
#include <mach/at91_pmc.h>
#include <mach/board.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91sam9_smc.h>
#include <linux/w1-gpio.h>
diff --git a/arch/arm/boards/pm9g45/init.c b/arch/arm/boards/pm9g45/init.c
index efa5dc025d..0565657a8c 100644
--- a/arch/arm/boards/pm9g45/init.c
+++ b/arch/arm/boards/pm9g45/init.c
@@ -34,7 +34,6 @@
#include <mach/at91_pmc.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91sam9_smc.h>
#include <linux/w1-gpio.h>
#include <w1_mac_address.h>
diff --git a/arch/arm/boards/qil-a926x/init.c b/arch/arm/boards/qil-a926x/init.c
index 6fa0df033e..fa7575d270 100644
--- a/arch/arm/boards/qil-a926x/init.c
+++ b/arch/arm/boards/qil-a926x/init.c
@@ -25,7 +25,6 @@
#include <mach/at91sam9_smc.h>
#include <gpio.h>
#include <led.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/sama5d3_xplained/init.c b/arch/arm/boards/sama5d3_xplained/init.c
index fda4c56c6c..2433e25f16 100644
--- a/arch/arm/boards/sama5d3_xplained/init.c
+++ b/arch/arm/boards/sama5d3_xplained/init.c
@@ -30,7 +30,6 @@
#include <mach/board.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/sama5d3xek/init.c b/arch/arm/boards/sama5d3xek/init.c
index b35bdb5b05..08ccbcf4a3 100644
--- a/arch/arm/boards/sama5d3xek/init.c
+++ b/arch/arm/boards/sama5d3xek/init.c
@@ -33,7 +33,6 @@
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_smc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/telit-evk-pro3/init.c b/arch/arm/boards/telit-evk-pro3/init.c
index 4f536079cc..f6ee715bb1 100644
--- a/arch/arm/boards/telit-evk-pro3/init.c
+++ b/arch/arm/boards/telit-evk-pro3/init.c
@@ -22,7 +22,6 @@
#include <mach/at91_rstc.h>
#include <mach/at91sam9_smc.h>
#include <mach/board.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <nand.h>
diff --git a/arch/arm/boards/tny-a926x/init.c b/arch/arm/boards/tny-a926x/init.c
index 3b83c9f222..dab373009f 100644
--- a/arch/arm/boards/tny-a926x/init.c
+++ b/arch/arm/boards/tny-a926x/init.c
@@ -34,7 +34,6 @@
#include <mach/at91sam9_smc.h>
#include <mach/at91sam9_sdramc.h>
#include <gpio.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/boards/usb-a926x/init.c b/arch/arm/boards/usb-a926x/init.c
index e431cd4603..8969cbd3a8 100644
--- a/arch/arm/boards/usb-a926x/init.c
+++ b/arch/arm/boards/usb-a926x/init.c
@@ -36,7 +36,6 @@
#include <mach/at91sam9_sdramc.h>
#include <gpio.h>
#include <led.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/at91_pmc.h>
#include <mach/at91_rstc.h>
diff --git a/arch/arm/mach-at91/at91rm9200_devices.c b/arch/arm/mach-at91/at91rm9200_devices.c
index 2563b6c834..f370160580 100644
--- a/arch/arm/mach-at91/at91rm9200_devices.c
+++ b/arch/arm/mach-at91/at91rm9200_devices.c
@@ -17,7 +17,6 @@
#include <mach/at91rm9200.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/at91rm9200_mc.h>
#include <i2c/i2c-gpio.h>
#include <linux/sizes.h>
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index ef85502f5e..b4021b5038 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -31,7 +31,6 @@
#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91rm9200_st.h>
-#include <mach/io.h>
#include <io.h>
static void __iomem *st = IOMEM(AT91RM9200_BASE_ST);
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 9b8654f400..eafcfeacf7 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91sam9_sdramc.h>
#include <mach/at91_rtt.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/at91sam9261_devices.c b/arch/arm/mach-at91/at91sam9261_devices.c
index 3b869f923c..fcf719a09a 100644
--- a/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/arch/arm/mach-at91/at91sam9261_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/at91sam9263_devices.c b/arch/arm/mach-at91/at91sam9263_devices.c
index 877acc0df7..a67345f05d 100644
--- a/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/arch/arm/mach-at91/at91sam9263_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <i2c/i2c-gpio.h>
#include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index c70036b389..29294ae28f 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -1,7 +1,6 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
-#include <mach/io.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index ae4bd50c4b..43d8d5fbd6 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <i2c/i2c-gpio.h>
#include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 7ab44e4964..f764af2861 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -3,7 +3,6 @@
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include "generic.h"
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index 3c606d5a4d..43cbb79af4 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -19,7 +19,6 @@
#include <mach/at91_pmc.h>
#include <mach/at91sam9n12_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index b8035c1acf..ab506a1f42 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -18,7 +18,6 @@
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 125d16917e..1f2cfdc716 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -20,7 +20,6 @@
#include <init.h>
#include <mach/hardware.h>
-#include <mach/io.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
index 14da76b85a..03e1b87f5f 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200_mc.h
@@ -158,7 +158,8 @@
#define AT91RM9200_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#ifndef __ASSEMBLY__
-#include <mach/io.h>
+#include <io.h>
+#include <mach/at91rm9200.h>
static inline u32 at91rm9200_get_sdram_size(void)
{
u32 cr, mr;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
index 88796a6a2c..1c4d313eb4 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
@@ -136,7 +136,7 @@ Banks [not SAM9G45] */
#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
#ifndef __ASSEMBLY__
-#include <mach/io.h>
+#include <io.h>
static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
{
@@ -176,6 +176,7 @@ static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
}
#ifdef CONFIG_SOC_AT91SAM9G45
+#include <mach/at91sam9g45.h>
static inline u32 at91sam9g45_get_ddram_size(int bank)
{
switch (bank) {
@@ -195,6 +196,7 @@ static inline u32 at91sam9g45_get_ddram_size(int bank)
#endif
#ifdef CONFIG_SOC_AT91SAM9X5
+#include <mach/at91sam9x5.h>
static inline u32 at91sam9x5_get_ddram_size(void)
{
return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true);
@@ -207,6 +209,7 @@ static inline u32 at91sam9x5_get_ddram_size(void)
#endif
#ifdef CONFIG_SOC_AT91SAM9N12
+#include <mach/at91sam9n12.h>
static inline u32 at91sam9n12_get_ddram_size(void)
{
return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true);
@@ -219,6 +222,7 @@ static inline u32 at91sam9n12_get_ddram_size(void)
#endif
#ifdef CONFIG_SOC_SAMA5
+#include <mach/sama5d3.h>
static inline u32 at91sama5_get_ddram_size(void)
{
u32 cr;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
index 91efa67c8a..8595f9cd5c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
@@ -84,7 +84,7 @@
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
#ifndef __ASSEMBLY__
-#include <mach/io.h>
+#include <io.h>
static inline u32 at91_get_sdram_size(void *base)
{
u32 val;
@@ -118,6 +118,7 @@ static inline bool at91_is_low_power_sdram(void *base)
}
#ifdef CONFIG_SOC_AT91SAM9260
+#include <mach/at91sam9260.h>
static inline u32 at91sam9260_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC));
@@ -140,6 +141,7 @@ static inline bool at91sam9260_is_low_power_sdram(void)
#endif
#ifdef CONFIG_SOC_AT91SAM9261
+#include <mach/at91sam9261.h>
static inline u32 at91sam9261_get_sdram_size(void)
{
return at91_get_sdram_size(IOMEM(AT91SAM9261_BASE_SDRAMC));
@@ -162,6 +164,7 @@ static inline bool at91sam9261_is_low_power_sdram(void)
#endif
#ifdef CONFIG_SOC_AT91SAM9263
+#include <mach/at91sam9263.h>
static inline u32 at91sam9263_get_sdram_size(int bank)
{
switch (bank) {
diff --git a/arch/arm/mach-at91/include/mach/io.h b/arch/arm/mach-at91/include/mach/io.h
deleted file mode 100644
index a1d970f2a2..0000000000
--- a/arch/arm/mach-at91/include/mach/io.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * [origin: Linux kernel include/asm-arm/arch-at91/io.h]
- *
- * Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#include <io.h>
-#include <mach/hardware.h>
-
-static inline unsigned int at91_sys_read(unsigned int reg_offset)
-{
- void *addr = (void *)AT91_BASE_SYS;
-
- return __raw_readl(addr + reg_offset);
-}
-
-static inline void at91_sys_write(unsigned int reg_offset, unsigned long value)
-{
- void *addr = (void *)AT91_BASE_SYS;
-
- __raw_writel(value, addr + reg_offset);
-}
-
-#endif
diff --git a/arch/arm/mach-at91/sam9_smc.c b/arch/arm/mach-at91/sam9_smc.c
index d2b075e3e8..dc1f2edf41 100644
--- a/arch/arm/mach-at91/sam9_smc.c
+++ b/arch/arm/mach-at91/sam9_smc.c
@@ -13,7 +13,6 @@
#include <io.h>
#include <mach/hardware.h>
#include <mach/cpu.h>
-#include <mach/io.h>
#include <linux/err.h>
#include <mach/at91sam9_smc.h>
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index b52c6b49be..01c724f940 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -3,7 +3,6 @@
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <linux/clk.h>
diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c
index c6f5e3a87c..f5075b3937 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -20,7 +20,6 @@
#include <mach/at91sam9x5_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
index d6b18fca24..137800f825 100644
--- a/arch/arm/mach-at91/sama5d4.c
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -12,7 +12,6 @@
#include <init.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <linux/clk.h>
diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c
index c2f171a968..4064e4441f 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -21,7 +21,6 @@
#include <mach/at91sam9x5_matrix.h>
#include <mach/at91sam9_ddrsdr.h>
#include <mach/iomux.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/drivers/clocksource/timer-atmel-pit.c b/drivers/clocksource/timer-atmel-pit.c
index 947a1e7f49..40895847f0 100644
--- a/drivers/clocksource/timer-atmel-pit.c
+++ b/drivers/clocksource/timer-atmel-pit.c
@@ -30,7 +30,6 @@
#include <clock.h>
#include <mach/hardware.h>
#include <mach/at91_pit.h>
-#include <mach/io.h>
#include <io.h>
#include <linux/clk.h>
#include <linux/err.h>
diff --git a/drivers/spi/atmel_spi.c b/drivers/spi/atmel_spi.c
index a0243be858..55bea79a5e 100644
--- a/drivers/spi/atmel_spi.c
+++ b/drivers/spi/atmel_spi.c
@@ -32,7 +32,6 @@
#include <of_gpio.h>
#include <io.h>
#include <spi/spi.h>
-#include <mach/io.h>
#include <mach/iomux.h>
#include <mach/board.h>
#include <mach/cpu.h>
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 9d45323a53..645275a016 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -18,6 +18,7 @@
#include <errno.h>
#include <init.h>
#include <gpio.h>
+#include <io.h>
#include <clock.h>
#include <usb/ch9.h>
#include <usb/gadget.h>
@@ -33,7 +34,6 @@
#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
#include <mach/at91sam9261.h>
#endif
-#include <mach/io.h>
#include <mach/board.h>
#include <mach/cpu.h>
#include <mach/at91sam9261_matrix.h>
diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c
index 5d130f598e..aa84334b09 100644
--- a/drivers/video/atmel_hlcdfb.c
+++ b/drivers/video/atmel_hlcdfb.c
@@ -24,7 +24,6 @@
#include <linux/clk.h>
#include <mach/hardware.h>
#include <mach/atmel_hlcdc.h>
-#include <mach/io.h>
#include <mach/cpu.h>
#include <errno.h>
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index d343c5c059..322404f322 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -22,7 +22,6 @@
#include <io.h>
#include <init.h>
#include <mach/hardware.h>
-#include <mach/io.h>
#include <errno.h>
#include <linux/clk.h>
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 17/22] ARM: at91sam926x use writel rather than pmc accessor function
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (15 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 16/22] ARM: at91: remove mach/io.h Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 18/22] ARM: at91rm9200ek: use plain readl/writel for pmc accesses Sascha Hauer
` (6 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
The pmc accessor function depends on a compile time base address, so
rather use writel directly. In this case we can hardcode the base
address again since all at91sam926x SoCs have the same pmc base address.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../include/mach/at91sam926x_board_init.h | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 4141e80ddb..ee4dfa7187 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -121,6 +121,7 @@ static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg
static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg *cfg)
{
u32 r;
+ void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC);
if (!IS_ENABLED(CONFIG_AT91SAM926X_BOARD_INIT))
return;
@@ -142,28 +143,28 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
/* PMC Check if the PLL is already initialized */
- r = at91_pmc_read(AT91_PMC_MCKR);
+ r = readl(pmc + AT91_PMC_MCKR);
if ((r & AT91_PMC_CSS) && !running_in_sram())
return;
/* Enable the Main Oscillator */
- at91_pmc_write(AT91_CKGR_MOR, cfg->pmc_mor);
+ writel(cfg->pmc_mor, pmc + AT91_CKGR_MOR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/* PLLAR: x MHz for PCK */
- at91_pmc_write(AT91_CKGR_PLLAR, cfg->pmc_pllar);
+ writel(cfg->pmc_pllar, pmc + AT91_CKGR_PLLAR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/* PCK/x = MCK Master Clock from SLOW */
- at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr1);
+ writel(cfg->pmc_mckr1, pmc + AT91_PMC_MCKR);
pmc_check_mckrdy();
/* PCK/x = MCK Master Clock from PLLA */
- at91_pmc_write(AT91_PMC_MCKR, cfg->pmc_mckr2);
+ writel(cfg->pmc_mckr2, pmc + AT91_PMC_MCKR);
pmc_check_mckrdy();
/* Init SDRAM */
@@ -178,7 +179,7 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
* so enable all of them
* We will shutdown what we don't need later
*/
- at91_pmc_write(AT91_PMC_PCER, 0xffffffff);
+ writel(0xffffffff, pmc + AT91_PMC_PCER);
}
#endif /* __AT91SAM926X_BOARD_INIT_H__ */
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 18/22] ARM: at91rm9200ek: use plain readl/writel for pmc accesses
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (16 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 17/22] ARM: at91sam926x use writel rather than pmc accessor function Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 19/22] ARM: at91: drop at91_pmc_write()/at91_pmc_read() Sascha Hauer
` (5 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
at91_pmc_write() needs a compile time base address, so rather use plain
read/writel.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91rm9200ek/lowlevel.c | 17 +++++++++--------
arch/arm/mach-at91/include/mach/at91rm9200.h | 1 +
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boards/at91rm9200ek/lowlevel.c b/arch/arm/boards/at91rm9200ek/lowlevel.c
index 3fb6ca3381..a5c9058552 100644
--- a/arch/arm/boards/at91rm9200ek/lowlevel.c
+++ b/arch/arm/boards/at91rm9200ek/lowlevel.c
@@ -26,23 +26,24 @@ void __naked __bare_init barebox_arm_reset_vector(void)
u32 r;
int i;
void __iomem *mc = IOMEM(AT91RM9200_BASE_MC);
+ void __iomem *pmc = IOMEM(AT91RM9200_BASE_PMC);
arm_cpu_lowlevel_init();
/*
* PMC Check if the PLL is already initialized
*/
- r = at91_pmc_read(AT91_PMC_MCKR);
+ r = __raw_readl(pmc + AT91_PMC_MCKR);
if (r & AT91_PMC_CSS)
goto end;
/*
* Enable the Main Oscillator
*/
- at91_pmc_write(AT91_CKGR_MOR, CONFIG_SYS_MOR_VAL);
+ __raw_writel(CONFIG_SYS_MOR_VAL, pmc + AT91_CKGR_MOR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = __raw_readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MOSCS));
/*
@@ -62,24 +63,24 @@ void __naked __bare_init barebox_arm_reset_vector(void)
/*
* PLLAR: x MHz for PCK
*/
- at91_pmc_write(AT91_CKGR_PLLAR, CONFIG_SYS_PLLAR_VAL);
+ __raw_writel(CONFIG_SYS_PLLAR_VAL, pmc + AT91_CKGR_PLLAR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = __raw_readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_LOCKA));
/*
* PCK/x = MCK Master Clock from SLOW
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL1);
+ __raw_writel(CONFIG_SYS_MCKR2_VAL1, pmc + AT91_PMC_MCKR);
/*
* PCK/x = MCK Master Clock from PLLA
*/
- at91_pmc_write(AT91_PMC_MCKR, CONFIG_SYS_MCKR2_VAL2);
+ __raw_writel(CONFIG_SYS_MCKR2_VAL2, pmc + AT91_PMC_MCKR);
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = __raw_readl(pmc + AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
/*
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index d06dfa7388..e2af3585af 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -84,6 +84,7 @@
#define AT91RM9200_BASE_PIOB 0xfffff600 /* PIO Controller B */
#define AT91RM9200_BASE_PIOC 0xfffff800 /* PIO Controller C */
#define AT91RM9200_BASE_PIOD 0xfffffa00 /* PIO Controller D */
+#define AT91RM9200_BASE_PMC 0xfffffc00
#define AT91RM9200_BASE_ST 0xfffffd00 /* System Timer */
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 19/22] ARM: at91: drop at91_pmc_write()/at91_pmc_read()
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (17 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 18/22] ARM: at91rm9200ek: use plain readl/writel for pmc accesses Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 20/22] ARM: at91: make at91sam926x_board_init board specific Sascha Hauer
` (4 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
at91_pmc_write() and at91_pmc_read() need a compile time base address,
so remove them.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/clock.c | 21 +++++++++++++++++++
arch/arm/mach-at91/include/mach/at91_pmc.h | 6 ------
.../include/mach/at91sam926x_board_init.h | 4 +++-
3 files changed, 24 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-at91/clock.c b/arch/arm/mach-at91/clock.c
index 1f2cfdc716..9d2e3a3acc 100644
--- a/arch/arm/mach-at91/clock.c
+++ b/arch/arm/mach-at91/clock.c
@@ -108,6 +108,18 @@
#define cpu_has_dual_matrix() (cpu_is_sama5d4())
+static void *pmc;
+
+static inline void at91_pmc_write(unsigned int offset, u32 val)
+{
+ writel(val, pmc + offset);
+}
+
+static inline u32 at91_pmc_read(unsigned int offset)
+{
+ return readl(pmc + offset);
+}
+
static LIST_HEAD(clocks);
static u32 at91_pllb_usb_init;
@@ -648,6 +660,15 @@ int at91_clock_init(void)
int i;
unsigned long main_clock;
+ if (cpu_is_sama5d4())
+ pmc = IOMEM(0xf0018000);
+ else
+ pmc = IOMEM(0xfffffc00); /*
+ * All other supported SoCs use this
+ * base address (new ones should use of
+ * clock support)
+ */
+
main_clock = at91_main_clock;
/*
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index d74c14011c..bbbd497afa 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -16,12 +16,6 @@
#ifndef AT91_PMC_H
#define AT91_PMC_H
-#define at91_pmc_read(field) \
- __raw_readl(AT91_PMC + field)
-
-#define at91_pmc_write(field, value) \
- __raw_writel(value, AT91_PMC + field)
-
#define AT91_PMC_SCER 0x00 /* System Clock Enable Register */
#define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index ee4dfa7187..36fb84b63c 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -20,6 +20,8 @@
#include <mach/gpio.h>
#include <mach/at91sam926x.h>
+#define AT91SAM926X_BASE_PMC 0xfffffc00
+
struct at91sam926x_board_cfg {
/* SoC specific */
void __iomem *pio;
@@ -59,7 +61,7 @@ static void __always_inline pmc_check_mckrdy(void)
u32 r;
do {
- r = at91_pmc_read(AT91_PMC_SR);
+ r = readl(AT91SAM926X_BASE_PMC + AT91_PMC_SR);
} while (!(r & AT91_PMC_MCKRDY));
}
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 20/22] ARM: at91: make at91sam926x_board_init board specific
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (18 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 19/22] ARM: at91: drop at91_pmc_write()/at91_pmc_read() Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 21/22] ARM: at91: separate restart handler registration into SoC specific code Sascha Hauer
` (3 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
The base addresses used in at91sam926x_board_init() differ with each
SoC. The board knows which SoC we are running on though, so create and
use SoC specific variants of these functions which pass the appropriate
base addresses to at91sam926x_board_init().
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/at91sam9261ek/lowlevel_init.c | 2 +-
arch/arm/boards/at91sam9263ek/lowlevel_init.c | 2 +-
arch/arm/boards/pm9261/lowlevel_init.c | 2 +-
arch/arm/boards/pm9263/lowlevel_init.c | 2 +-
.../arm/boards/tny-a926x/tny_a9263_lowlevel.c | 2 +-
.../arm/boards/usb-a926x/usb_a9263_lowlevel.c | 2 +-
.../include/mach/at91sam926x_board_init.h | 35 ++++++++++++++++---
.../arm/mach-at91/include/mach/at91sam9_smc.h | 6 ----
8 files changed, 36 insertions(+), 17 deletions(-)
diff --git a/arch/arm/boards/at91sam9261ek/lowlevel_init.c b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
index 2ade3191d4..33aa9430dc 100644
--- a/arch/arm/boards/at91sam9261ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9261ek/lowlevel_init.c
@@ -111,7 +111,7 @@ static void __bare_init at91sam9261ek_init(void)
cfg.matrix_csa = IOMEM(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
at91sam9261ek_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9261_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/at91sam9263ek/lowlevel_init.c b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
index af4b62c7a4..f5d68cd7e8 100644
--- a/arch/arm/boards/at91sam9263ek/lowlevel_init.c
+++ b/arch/arm/boards/at91sam9263ek/lowlevel_init.c
@@ -109,7 +109,7 @@ static void __bare_init at91sam9263ek_init(void *fdt)
cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
at91sam9263ek_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
fdt);
diff --git a/arch/arm/boards/pm9261/lowlevel_init.c b/arch/arm/boards/pm9261/lowlevel_init.c
index 5464fda90c..0ab34b0db6 100644
--- a/arch/arm/boards/pm9261/lowlevel_init.c
+++ b/arch/arm/boards/pm9261/lowlevel_init.c
@@ -105,7 +105,7 @@ static void __bare_init pm9261_init(void)
cfg.matrix_csa = IOMEM(AT91SAM9261_BASE_MATRIX + AT91SAM9261_MATRIX_EBICSA);
pm9261_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9261_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/pm9263/lowlevel_init.c b/arch/arm/boards/pm9263/lowlevel_init.c
index bcbcf7d6ab..32850b2981 100644
--- a/arch/arm/boards/pm9263/lowlevel_init.c
+++ b/arch/arm/boards/pm9263/lowlevel_init.c
@@ -126,7 +126,7 @@ static void __bare_init pm9263_board_init(void)
cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
pm9263_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
index b7630d4d6c..8566d27a0a 100644
--- a/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
+++ b/arch/arm/boards/tny-a926x/tny_a9263_lowlevel.c
@@ -111,7 +111,7 @@ static void __bare_init tny_a9263_init(void)
tny_a9263_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1,
at91_get_sdram_size(IOMEM(AT91SAM9263_BASE_SDRAMC0)),
diff --git a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
index 6a3e7ca365..a7dd2b2ada 100644
--- a/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
+++ b/arch/arm/boards/usb-a926x/usb_a9263_lowlevel.c
@@ -116,7 +116,7 @@ static void __bare_init usb_a9263_init(void)
cfg.matrix_csa = IOMEM(AT91SAM9263_BASE_MATRIX + AT91SAM9263_MATRIX_EBI0CSA);
usb_a9263_board_config(&cfg);
- at91sam926x_board_init(&cfg);
+ at91sam9263_board_init(&cfg);
barebox_arm_entry(AT91_CHIPSELECT_1, at91_get_sdram_size(cfg.sdramc),
NULL);
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 36fb84b63c..cbb08b9c7e 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -120,7 +120,8 @@ static void __always_inline at91sam926x_sdramc_init(struct at91sam926x_board_cfg
access_sdram();
}
-static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg *cfg)
+static void __always_inline at91sam926x_board_init(void __iomem *smcbase,
+ struct at91sam926x_board_cfg *cfg)
{
u32 r;
void __iomem *pmc = IOMEM(AT91SAM926X_BASE_PMC);
@@ -139,10 +140,10 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
writel(cfg->ebi_csa, cfg->matrix_csa);
/* flash */
- at91_smc_write(cfg->smc_cs, AT91_SAM9_SMC_MODE, cfg->smc_mode);
- at91_smc_write(cfg->smc_cs, AT91_SMC_CYCLE, cfg->smc_cycle);
- at91_smc_write(cfg->smc_cs, AT91_SMC_PULSE, cfg->smc_pulse);
- at91_smc_write(cfg->smc_cs, AT91_SMC_SETUP, cfg->smc_setup);
+ writel(cfg->smc_mode, smcbase + cfg->smc_cs * 0x10 + AT91_SAM9_SMC_MODE);
+ writel(cfg->smc_cycle, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_CYCLE);
+ writel(cfg->smc_pulse, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_PULSE);
+ writel(cfg->smc_setup, smcbase + cfg->smc_cs * 0x10 + AT91_SMC_SETUP);
/* PMC Check if the PLL is already initialized */
r = readl(pmc + AT91_PMC_MCKR);
@@ -184,4 +185,28 @@ static void __always_inline at91sam926x_board_init(struct at91sam926x_board_cfg
writel(0xffffffff, pmc + AT91_PMC_PCER);
}
+#if defined CONFIG_ARCH_AT91SAM9260
+#include <mach/at91sam9260.h>
+static void __always_inline at91sam9260_board_init(struct at91sam926x_board_cfg *cfg)
+{
+ at91sam926x_board_init(IOMEM(AT91SAM9260_BASE_SMC), cfg);
+}
+#endif
+
+#if defined CONFIG_ARCH_AT91SAM9261 || defined CONFIG_ARCH_AT91SAM9G10
+#include <mach/at91sam9261.h>
+static void __always_inline at91sam9261_board_init(struct at91sam926x_board_cfg *cfg)
+{
+ at91sam926x_board_init(IOMEM(AT91SAM9261_BASE_SMC), cfg);
+}
+#endif
+
+#if defined CONFIG_ARCH_AT91SAM9263
+#include <mach/at91sam9263.h>
+static void __always_inline at91sam9263_board_init(struct at91sam926x_board_cfg *cfg)
+{
+ at91sam926x_board_init(IOMEM(AT91SAM9263_BASE_SMC0), cfg);
+}
+#endif
+
#endif /* __AT91SAM926X_BOARD_INIT_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_smc.h b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
index d19cf82eca..0908f6df25 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9_smc.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9_smc.h
@@ -16,12 +16,6 @@
#ifndef AT91SAM9_SMC_H
#define AT91SAM9_SMC_H
-#define at91_smc_read(id, field) \
- __raw_readl(AT91_BASE_SMC + ((id) * 0x10) + field)
-
-#define at91_smc_write(id, field, value) \
- __raw_writel(value, AT91_BASE_SMC + ((id) * 0x10) + field)
-
#ifndef __ASSEMBLY__
struct sam9_smc_config {
/* Setup register */
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 21/22] ARM: at91: separate restart handler registration into SoC specific code
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (19 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 20/22] ARM: at91: make at91sam926x_board_init board specific Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 15:51 ` [PATCH 22/22] ARM: at91: remove unused defines Sascha Hauer
` (2 subsequent siblings)
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/Kconfig | 14 -------------
arch/arm/mach-at91/Makefile | 6 +++---
arch/arm/mach-at91/at91sam9260.c | 11 ++++++++++
arch/arm/mach-at91/at91sam9261.c | 11 ++++++++++
arch/arm/mach-at91/at91sam9263.c | 11 ++++++++++
arch/arm/mach-at91/at91sam9_reset.S | 12 ++---------
arch/arm/mach-at91/at91sam9g45.c | 11 ++++++++++
arch/arm/mach-at91/at91sam9g45_reset.S | 12 ++---------
arch/arm/mach-at91/at91sam9n12.c | 11 ++++++++++
arch/arm/mach-at91/at91sam9x5.c | 20 +++++++++++++++++++
.../include/mach/at91sam926x_board_init.h | 2 ++
arch/arm/mach-at91/include/mach/at91sam9x5.h | 2 +-
arch/arm/mach-at91/include/mach/board.h | 3 +++
arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
arch/arm/mach-at91/include/mach/sama5d4.h | 1 +
arch/arm/mach-at91/sama5d3.c | 11 ++++++++++
arch/arm/mach-at91/sama5d4.c | 11 ++++++++++
arch/arm/mach-at91/setup.c | 8 --------
18 files changed, 112 insertions(+), 46 deletions(-)
create mode 100644 arch/arm/mach-at91/at91sam9x5.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 2c949098f0..7a895c2689 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -74,12 +74,6 @@ config HAVE_NAND_ATMEL_BUSWIDTH_16
config HAVE_AT91_DATAFLASH_CARD
bool
-config AT91SAM9_RESET
- bool
-
-config AT91SAM9G45_RESET
- bool
-
config HAVE_AT91_LOAD_BAREBOX_SRAM
bool
@@ -96,7 +90,6 @@ config SOC_AT91SAM9260
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select HAS_MACB
- select AT91SAM9_RESET
help
Select this if you are using one of Atmel's AT91SAM9260, AT91SAM9XE
or AT91SAM9G20 SoC.
@@ -105,7 +98,6 @@ config SOC_AT91SAM9261
bool
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
- select AT91SAM9_RESET
help
Select this if you are using one of Atmel's AT91SAM9261 or AT91SAM9G10 SoC.
@@ -114,7 +106,6 @@ config SOC_AT91SAM9263
select SOC_AT91SAM9
select HAVE_AT91_DBGU1
select HAS_MACB
- select AT91SAM9_RESET
select HAVE_AT91_LOAD_BAREBOX_SRAM
config SOC_AT91SAM9G45
@@ -122,7 +113,6 @@ config SOC_AT91SAM9G45
select SOC_AT91SAM9
select HAVE_AT91_DBGU1
select HAS_MACB
- select AT91SAM9G45_RESET
help
Select this if you are using one of Atmel's AT91SAM9G45 family SoC.
This support covers AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
@@ -132,7 +122,6 @@ config SOC_AT91SAM9X5
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
select HAS_MACB
- select AT91SAM9G45_RESET
select HAVE_AT91_SMD
select HAVE_AT91_USB_CLK
select HAVE_AT91_UTMI
@@ -148,7 +137,6 @@ config SOC_AT91SAM9N12
bool
select SOC_AT91SAM9
select HAVE_AT91_DBGU0
- select AT91SAM9G45_RESET
help
Select this if you are using Atmel's AT91SAM9N12 SoC.
@@ -203,7 +191,6 @@ config ARCH_SAMA5D3
select SOC_SAMA5
select HAVE_AT91_DBGU1
select HAS_MACB
- select AT91SAM9G45_RESET
select HAVE_MACH_ARM_HEAD
config ARCH_SAMA5D4
@@ -211,7 +198,6 @@ config ARCH_SAMA5D4
select SOC_SAMA5
select HAVE_AT91_DBGU2
select HAS_MACB
- select AT91SAM9G45_RESET
select HAVE_MACH_ARM_HEAD
endchoice
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index afbc896eea..d81683ac12 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -8,8 +8,8 @@ obj-$(CONFIG_CMD_AT91_BOOT_TEST) += boot_test_cmd.o
obj-$(CONFIG_AT91_BOOTSTRAP) += bootstrap.o
-obj-$(CONFIG_AT91SAM9_RESET) += at91sam9_reset.o
-obj-$(CONFIG_AT91SAM9G45_RESET) += at91sam9g45_reset.o
+obj-y += at91sam9_reset.o
+obj-y += at91sam9g45_reset.o
obj-$(CONFIG_AT91SAM9_SMC) += sam9_smc.o
@@ -24,6 +24,6 @@ obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o
endif
obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
-obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
obj-$(CONFIG_ARCH_SAMA5D4) += sama5d4.o sama5d4_devices.o
diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index 8975bf4665..56327a2c47 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -1,8 +1,11 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -221,6 +224,12 @@ static void __init at91sam9260_register_clocks(void)
clk_register(&pck1);
}
+static void at91sam9260_restart(struct restart_handler *rst)
+{
+ at91sam9_reset(IOMEM(AT91SAM9260_BASE_SDRAMC),
+ IOMEM(AT91SAM9260_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9260_initialize(void)
{
/* Register the processor-specific clocks */
@@ -233,6 +242,8 @@ static void at91sam9260_initialize(void)
at91_add_pit(AT91SAM9260_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9260_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9260_restart);
}
static int at91sam9260_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9261.c b/arch/arm/mach-at91/at91sam9261.c
index 35aaa9c96a..4abc556354 100644
--- a/arch/arm/mach-at91/at91sam9261.c
+++ b/arch/arm/mach-at91/at91sam9261.c
@@ -1,8 +1,11 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -213,6 +216,12 @@ static void at91sam9261_register_clocks(void)
clk_register(&hck1);
}
+static void at91sam9261_restart(struct restart_handler *rst)
+{
+ at91sam9_reset(IOMEM(AT91SAM9261_BASE_SDRAMC),
+ IOMEM(AT91SAM9261_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9261_initialize(void)
{
/* Register the processor-specific clocks */
@@ -225,6 +234,8 @@ static void at91sam9261_initialize(void)
at91_add_pit(AT91SAM9261_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9261_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9261_restart);
}
static int at91sam9261_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9263.c b/arch/arm/mach-at91/at91sam9263.c
index ee48115ea8..690f8e06bb 100644
--- a/arch/arm/mach-at91/at91sam9263.c
+++ b/arch/arm/mach-at91/at91sam9263.c
@@ -1,8 +1,11 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "clock.h"
#include "generic.h"
@@ -231,6 +234,12 @@ static void __init at91sam9263_register_clocks(void)
clk_register(&pck3);
}
+static void at91sam9263_restart(struct restart_handler *rst)
+{
+ at91sam9_reset(IOMEM(AT91SAM9263_BASE_SDRAMC0),
+ IOMEM(AT91SAM9263_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9263_initialize(void)
{
/* Register the processor-specific clocks */
@@ -246,6 +255,8 @@ static void at91sam9263_initialize(void)
at91_add_pit(AT91SAM9263_BASE_PIT);
at91_add_sam9_smc(0, AT91SAM9263_BASE_SMC0, 0x200);
at91_add_sam9_smc(1, AT91SAM9263_BASE_SMC1, 0x200);
+
+ restart_handler_register_fn(at91sam9263_restart);
}
static int at91sam9263_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9_reset.S b/arch/arm/mach-at91/at91sam9_reset.S
index c10674aa40..65e22f4fe7 100644
--- a/arch/arm/mach-at91/at91sam9_reset.S
+++ b/arch/arm/mach-at91/at91sam9_reset.S
@@ -20,12 +20,9 @@
.arm
- .globl restart_sam9
+ .globl at91sam9_reset
-restart_sam9: ldr r0, .at91_va_base_sdramc @ preload constants
- ldr r1, .at91_va_base_rstc_cr
-
- mov r2, #1
+at91sam9_reset: mov r2, #1
mov r3, #AT91_SDRAMC_LPCB_POWER_DOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
@@ -36,8 +33,3 @@ restart_sam9: ldr r0, .at91_va_base_sdramc @ preload constants
str r4, [r1] @ reset processor
b .
-
-.at91_va_base_sdramc:
- .word AT91_BASE_SYS + AT91_SDRAMC
-.at91_va_base_rstc_cr:
- .word AT91_BASE_SYS + AT91_RSTC + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index 29294ae28f..569aa274fc 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -1,9 +1,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -246,6 +249,12 @@ static void __init at91sam9g45_register_clocks(void)
clk_register(&pck1);
}
+static void at91sam9g45_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(AT91SAM9G45_BASE_DDRSDRC0),
+ IOMEM(AT91SAM9G45_BASE_RSTC + AT91_RSTC_CR));
+}
+
static void at91sam9g45_initialize(void)
{
/* Register the processor-specific clocks */
@@ -260,6 +269,8 @@ static void at91sam9g45_initialize(void)
at91_add_pit(AT91SAM9G45_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9G45_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9g45_restart);
}
static int at91sam9g45_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index be2ad9d396..6a58de618c 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -17,12 +17,9 @@
.arm
- .globl restart_sam9g45
+ .globl at91sam9g45_reset
-restart_sam9g45: ldr r0, .at91_va_base_sdramc @ preload constants
- ldr r1, .at91_va_base_rstc_cr
-
- mov r2, #1
+at91sam9g45_reset: mov r2, #1
mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
@@ -33,8 +30,3 @@ restart_sam9g45: ldr r0, .at91_va_base_sdramc @ preload constants
str r4, [r1] @ reset processor
b .
-
-.at91_va_base_sdramc:
- .word AT91_BASE_SYS + AT91_DDRSDRC0
-.at91_va_base_rstc_cr:
- .word AT91_BASE_SYS + AT91_RSTC + AT91_RSTC_CR
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index f764af2861..365bded56e 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -1,9 +1,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include "generic.h"
#include "clock.h"
@@ -199,6 +202,12 @@ static void __init at91sam9n12_register_clocks(void)
}
+static void at91sam9n12_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(AT91SAM9N12_BASE_DDRSDRC0),
+ IOMEM(AT91SAM9N12_BASE_RSTC + AT91_RSTC_CR));
+}
+
/* --------------------------------------------------------------------
* AT91SAM9N12 processor initialization
* -------------------------------------------------------------------- */
@@ -216,6 +225,8 @@ static void at91sam9n12_initialize(void)
at91_add_pit(AT91SAM9N12_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, AT91SAM9N12_BASE_SMC, 0x200);
+
+ restart_handler_register_fn(at91sam9n12_restart);
}
static int at91sam9n12_setup(void)
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
new file mode 100644
index 0000000000..40ba9ed56e
--- /dev/null
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -0,0 +1,20 @@
+#include <common.h>
+#include <init.h>
+#include <restart.h>
+#include <mach/at91sam9x5.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
+
+static void at91sam9x5_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(AT91SAM9X5_BASE_DDRSDRC0),
+ IOMEM(AT91SAM9X5_BASE_RSTC + AT91_RSTC_CR));
+}
+
+static int at91sam9x5_initialize(void)
+{
+ restart_handler_register_fn(at91sam9x5_restart);
+
+ return 0;
+}
+coredevice_initcall(at91sam9x5_initialize);
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index cbb08b9c7e..0a036a9db2 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -21,6 +21,8 @@
#include <mach/at91sam926x.h>
#define AT91SAM926X_BASE_PMC 0xfffffc00
+#define AT91SAM926X_BASE_RSTC 0xfffffd00
+#define AT91SAM926X_BASE_WDT 0xfffffd40
struct at91sam926x_board_cfg {
/* SoC specific */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 3ea2501b4c..54544968f5 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -90,7 +90,7 @@
* System Peripherals
*/
#define AT91SAM9X5_BASE_MATRIX 0xffffde00
-#define AT9SAM9X5_BASE1_PMECC 0xffffe000
+#define AT91SAM9X5_BASE_PMECC 0xffffe000
#define AT91SAM9X5_BASE_PMERRLOC 0xffffe600
#define AT91SAM9X5_BASE_DDRSDRC0 0xffffe800
#define AT91SAM9X5_BASE_SMC 0xffffea00
diff --git a/arch/arm/mach-at91/include/mach/board.h b/arch/arm/mach-at91/include/mach/board.h
index 56c86f0bfb..0f2c269732 100644
--- a/arch/arm/mach-at91/include/mach/board.h
+++ b/arch/arm/mach-at91/include/mach/board.h
@@ -167,4 +167,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_platform_data *data);
void at91sam_phy_reset(void __iomem *rstc_base);
+void at91sam9_reset(void __iomem *sdram, void __iomem *rstc_cr);
+void at91sam9g45_reset(void __iomem *sdram, void __iomem *rstc_cr);
+
#endif
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 2c64fdf48a..69f4f3d5df 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -98,6 +98,7 @@
#define SAMA5D3_BASE_PIOE 0xfffffa00
#define SAMA5D3_BASE_MPDDRC 0xffffea00
#define SAMA5D3_BASE_HSMC 0xffffc000
+#define SAMA5D3_BASE_RSTC 0xfffffe00
#define SAMA5D3_BASE_PIT 0xfffffe30
#define SAMA5D3_BASE_WDT 0xfffffe40
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 5ff0ffa131..022530e9f9 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -106,6 +106,7 @@
#define SAMA5D4_BASE_PMECC 0xfc05c070 /* (PMECC) Base Address */
#define SAMA5D4_BASE_PMERRLOC 0xfc05c500 /* (PMERRLOC) Base Address */
#define SAMA5D4_BASE_PIOD 0xfc068000 /* (PIOD) Base Address */
+#define SAMA5D4_BASE_RSTC 0xfc068600
#define SAMA5D4_BASE_PIT 0xfc068630 /* (PIT) Base Address */
#define SAMA5D4_BASE_DBGU 0xfc069000 /* (DBGU) Base Address */
#define SAMA5D4_BASE_PIOA 0xfc06a000 /* (PIOA) Base Address */
diff --git a/arch/arm/mach-at91/sama5d3.c b/arch/arm/mach-at91/sama5d3.c
index 01c724f940..a5d464eca0 100644
--- a/arch/arm/mach-at91/sama5d3.c
+++ b/arch/arm/mach-at91/sama5d3.c
@@ -1,9 +1,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include <linux/clk.h>
#include "generic.h"
@@ -369,6 +372,12 @@ static void __init sama5d3_register_clocks(void)
//clk_enable(&dma1_clk);
}
+static void sama5d3_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(SAMA5D3_BASE_MPDDRC),
+ IOMEM(SAMA5D3_BASE_RSTC + AT91_RSTC_CR));
+}
+
/* --------------------------------------------------------------------
* AT91SAM9x5 processor initialization
* -------------------------------------------------------------------- */
@@ -387,6 +396,8 @@ static void sama5d3_initialize(void)
at91_add_pit(SAMA5D3_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D3_BASE_HSMC + 0x600, 0xa0);
+
+ restart_handler_register_fn(sama5d3_restart);
}
static int sama5d3_setup(void)
diff --git a/arch/arm/mach-at91/sama5d4.c b/arch/arm/mach-at91/sama5d4.c
index 137800f825..ca09dfe425 100644
--- a/arch/arm/mach-at91/sama5d4.c
+++ b/arch/arm/mach-at91/sama5d4.c
@@ -10,9 +10,12 @@
#include <common.h>
#include <gpio.h>
#include <init.h>
+#include <restart.h>
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/cpu.h>
+#include <mach/board.h>
+#include <mach/at91_rstc.h>
#include <linux/clk.h>
#include "generic.h"
@@ -278,6 +281,12 @@ static void __init sama5d4_register_clocks(void)
clk_register(&pck2);
}
+static void sama5d4_restart(struct restart_handler *rst)
+{
+ at91sam9g45_reset(IOMEM(SAMA5D4_BASE_MPDDRC),
+ IOMEM(SAMA5D4_BASE_RSTC + AT91_RSTC_CR));
+}
+
/* --------------------------------------------------------------------
* Processor initialization
* -------------------------------------------------------------------- */
@@ -295,6 +304,8 @@ static void sama5d4_initialize(void)
at91_add_pit(SAMA5D4_BASE_PIT);
at91_add_sam9_smc(DEVICE_ID_SINGLE, SAMA5D4_BASE_HSMC + 0x600, 0xa0);
+
+ restart_handler_register_fn(sama5d4_restart);
}
static int sama5d4_setup(void)
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 0cc3cc3dec..adc614c42c 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -283,9 +283,6 @@ static int at91_detect(void)
}
postcore_initcall(at91_detect);
-void restart_sam9(struct restart_handler *rst);
-void restart_sam9g45(struct restart_handler *rst);
-
static int at91_soc_device(void)
{
struct device_d *dev;
@@ -294,11 +291,6 @@ static int at91_soc_device(void)
dev_add_param_fixed(dev, "name", (char*)at91_get_soc_type(&at91_soc_initdata));
dev_add_param_fixed(dev, "subname", (char*)at91_get_soc_subtype(&at91_soc_initdata));
- if (IS_ENABLED(CONFIG_AT91SAM9_RESET))
- restart_handler_register_fn(restart_sam9);
- if (IS_ENABLED(CONFIG_AT91SAM9G45_RESET))
- restart_handler_register_fn(restart_sam9g45);
-
return 0;
}
coredevice_initcall(at91_soc_device);
--
2.19.1
_______________________________________________
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barebox@lists.infradead.org
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^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH 22/22] ARM: at91: remove unused defines
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (20 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 21/22] ARM: at91: separate restart handler registration into SoC specific code Sascha Hauer
@ 2018-11-05 15:51 ` Sascha Hauer
2018-11-05 23:16 ` [PATCH 00/22] AT91 header cleanup Andrey Smirnov
2018-11-07 10:12 ` Ladislav Michl
23 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-05 15:51 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91rm9200.h | 16 ----------------
arch/arm/mach-at91/include/mach/at91sam9260.h | 15 ---------------
arch/arm/mach-at91/include/mach/at91sam9261.h | 14 --------------
arch/arm/mach-at91/include/mach/at91sam9263.h | 17 -----------------
.../include/mach/at91sam926x_board_init.h | 4 ----
arch/arm/mach-at91/include/mach/at91sam9g45.h | 16 ----------------
arch/arm/mach-at91/include/mach/at91sam9n12.h | 16 ----------------
arch/arm/mach-at91/include/mach/at91sam9x5.h | 16 ----------------
arch/arm/mach-at91/include/mach/sama5d3.h | 11 -----------
arch/arm/mach-at91/include/mach/sama5d4.h | 8 --------
10 files changed, 133 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91rm9200.h b/arch/arm/mach-at91/include/mach/at91rm9200.h
index e2af3585af..01f5d23e0c 100644
--- a/arch/arm/mach-at91/include/mach/at91rm9200.h
+++ b/arch/arm/mach-at91/include/mach/at91rm9200.h
@@ -74,7 +74,6 @@
#define AT91RM9200_BASE_SSC1 0xfffd4000
#define AT91RM9200_BASE_SSC2 0xfffd8000
#define AT91RM9200_BASE_SPI 0xfffe0000
-#define AT91_BASE_SYS 0xfffff000
/*
* System Peripherals
@@ -89,21 +88,6 @@
#define AT91RM9200_BASE_RTC 0xfffffe00 /* Real-Time Clock */
#define AT91RM9200_BASE_MC 0xffffff00 /* Memory Controllers */
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
-#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
-#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
-#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
-
-#define AT91_TC (AT91RM9200_BASE_TC0 - AT91_BASE_SYS)
-
-#define AT91_MATRIX 0 /* not supported */
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9260.h b/arch/arm/mach-at91/include/mach/at91sam9260.h
index a816c448ba..708e661b4d 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9260.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9260.h
@@ -73,7 +73,6 @@
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
-#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals
@@ -93,20 +92,6 @@
#define AT91SAM9260_BASE_WDT 0xfffffd40
#define AT91SAM9260_BASE_GPBR 0xfffffd50
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
-#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_SMC AT91SAM9260_BASE_SMC
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9261.h b/arch/arm/mach-at91/include/mach/at91sam9261.h
index acd39f28de..df948d3e72 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9261.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9261.h
@@ -60,7 +60,6 @@
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
-#define AT91_BASE_SYS 0xffffea00
/*
@@ -80,19 +79,6 @@
#define AT91SAM9261_BASE_WDT 0xfffffd40
#define AT91SAM9261_BASE_GPBR 0xfffffd50
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_SMC AT91SAM9261_BASE_SMC
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9263.h b/arch/arm/mach-at91/include/mach/at91sam9263.h
index ef3424a6c5..a357ea83fe 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9263.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9263.h
@@ -70,7 +70,6 @@
#define AT91SAM9263_BASE_EMAC 0xfffbc000
#define AT91SAM9263_BASE_ISI 0xfffc4000
#define AT91SAM9263_BASE_2DGE 0xfffc8000
-#define AT91_BASE_SYS 0xffffe000
/*
@@ -97,22 +96,6 @@
#define AT91SAM9263_BASE_RTT1 0xfffffd50
#define AT91SAM9263_BASE_GPBR 0xfffffd60
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC0 (0xffffe000 - AT91_BASE_SYS)
-#define AT91_SDRAMC0 (0xffffe200 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_SMC AT91SAM9263_BASE_SMC0
-
-#define AT91_SDRAMC AT91_SDRAMC0
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
index 0a036a9db2..9ab0eef728 100644
--- a/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
+++ b/arch/arm/mach-at91/include/mach/at91sam926x_board_init.h
@@ -20,10 +20,6 @@
#include <mach/gpio.h>
#include <mach/at91sam926x.h>
-#define AT91SAM926X_BASE_PMC 0xfffffc00
-#define AT91SAM926X_BASE_RSTC 0xfffffd00
-#define AT91SAM926X_BASE_WDT 0xfffffd40
-
struct at91sam926x_board_cfg {
/* SoC specific */
void __iomem *pio;
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 7b19d92ad3..f79df0b8c3 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -82,7 +82,6 @@
#define AT91SAM9G45_BASE_TC3 0xfffd4000
#define AT91SAM9G45_BASE_TC4 0xfffd4040
#define AT91SAM9G45_BASE_TC5 0xfffd4080
-#define AT91_BASE_SYS 0xffffe200
/*
* System Peripherals
@@ -107,21 +106,6 @@
#define AT91SAM9G45_BASE_RTC 0xfffffdb0
#define AT91SAM9G45_BASE_GPBR 0xfffffd60
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
-#define AT91_DDRSDRC1 (0xffffe400 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0 (0xffffe600 - AT91_BASE_SYS)
-#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
-#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
-
-#define AT91_BASE_SMC AT91SAM9G45_BASE_SMC
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9n12.h b/arch/arm/mach-at91/include/mach/at91sam9n12.h
index 0bb105b910..dd9c0fc4e0 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9n12.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9n12.h
@@ -77,7 +77,6 @@
#define AT91SAM9N12_BASE_UART1 0xf8044000
#define AT91SAM9N12_BASE_TRNG 0xf8048000
#define AT91SAM9N12_BASE_ADC 0xf804c000
-#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals
@@ -103,21 +102,6 @@
#define AT91SAM9N12_BASE_GPBR 0xfffffe60
#define AT91SAM9N12_BASE_RTC 0xfffffeb0
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
-#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
-#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-
-#define AT91_BASE_SMC AT91SAM9N12_BASE_SMC
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/at91sam9x5.h b/arch/arm/mach-at91/include/mach/at91sam9x5.h
index 54544968f5..f9d54df601 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9x5.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9x5.h
@@ -84,7 +84,6 @@
#define AT91SAM9X5_BASE_UART1 0xf8044000
#define AT91SAM9X5_BASE_ISI 0xf8048000
#define AT91SAM9X5_BASE_ADC 0xf804c000
-#define AT91_BASE_SYS 0xffffc000
/*
* System Peripherals
@@ -110,21 +109,6 @@
#define AT91SAM9X5_BASE_GPBR 0xfffffe60
#define AT91SAM9X5_BASE_RTC 0xfffffeb0
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_MATRIX (0xffffde00 - AT91_BASE_SYS)
-#define AT91_PMECC (0xffffe000 - AT91_BASE_SYS)
-#define AT91_PMERRLOC (0xffffe600 - AT91_BASE_SYS)
-#define AT91_DDRSDRC0 (0xffffe800 - AT91_BASE_SYS)
-#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
-#define AT91_SHDWC (0xfffffe10 - AT91_BASE_SYS)
-
-#define AT91_BASE_SMC AT91SAM9X5_BASE_SMC
-
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 69f4f3d5df..f0e53610c6 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -81,15 +81,6 @@
#define SAMA5D3_BASE_SPI1 0xf8008000
#define SAMA5D3_BASE_EMAC 0xf802c000 /* (EMAC) Base Address */
#define SAMA5D3_BASE_UDPHS 0xf8030000
-#define AT91_BASE_SYS 0xffffc000
-
-/*
- * System Peripherals (offset from AT91_BASE_SYS)
- */
-#define AT91_MATRIX (0xffffec00 - AT91_BASE_SYS)
-#define AT91_GPBR (0xfffffe60 - AT91_BASE_SYS) // KO OAR_TEMP, NO GPBR, error while building in "drivers/rtc/rtc-at91sam9.c"
-#define AT91_DDRSDRC0 (0xffffea00 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfffffe00 - AT91_BASE_SYS)
#define SAMA5D3_BASE_PIOA 0xfffff200
#define SAMA5D3_BASE_PIOB 0xfffff400
@@ -105,8 +96,6 @@
#define SAMA5D3_BASE_PMECC 0xffffc070
#define SAMA5D3_BASE_PMERRLOC 0xffffc500
-#define AT91_PMC 0xfffffc00
-
/*
* Internal Memory.
*/
diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index 022530e9f9..6d621e0111 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -123,12 +123,4 @@
#define SAMA5D4_SRAM_BASE 0x00200000 /* Internal SRAM base address */
#define SAMA5D4_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size */
-#define AT91_BASE_SYS 0xf0000000
-#define AT91_PMC SAMA5D4_BASE_PMC
-#define AT91_DDRSDRC0 (0xf0010000 - AT91_BASE_SYS)
-#define AT91_RSTC (0xfc068600 - AT91_BASE_SYS)
-#define SAMA5D3_BASE_MPDDRC SAMA5D4_BASE_MPDDRC
-#define SAMA5D3_SRAM_BASE SAMA5D4_SRAM_BASE
-#define SAMA5D3_SRAM_SIZE SAMA5D4_SRAM_SIZE
-
#endif
--
2.19.1
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/22] AT91 header cleanup
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (21 preceding siblings ...)
2018-11-05 15:51 ` [PATCH 22/22] ARM: at91: remove unused defines Sascha Hauer
@ 2018-11-05 23:16 ` Andrey Smirnov
2018-11-06 8:58 ` Sascha Hauer
2018-11-07 10:12 ` Ladislav Michl
23 siblings, 1 reply; 27+ messages in thread
From: Andrey Smirnov @ 2018-11-05 23:16 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Mon, Nov 5, 2018 at 7:51 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> The following series contains a bigger at91 header file cleanup. With
> this the SoC header files become completely SoC namespaced which means
> they can all be included as desired without conflicts. This makes the
> way free for more at91 multiboard support.
>
> I don't have that much AT91 hardware on my desk, so I am unable to test
> this properly. Testing feedback very much appreciated. Sam maybe?
>
I applied the series on 'next' and ran it on my AT91SAM9x5 devkit with
at91sam9g25 module. Didn't do anything sophisticated, just booted and
made sure that USB port can enumerate a USB stick, Ethernet pings and
I can read data off MMC. FWIW:
Tested-by: Andrey Smirnov <andrew.smrinov@gmail.com>
Thanks,
Andrey Smirnov
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/22] AT91 header cleanup
2018-11-05 23:16 ` [PATCH 00/22] AT91 header cleanup Andrey Smirnov
@ 2018-11-06 8:58 ` Sascha Hauer
0 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-06 8:58 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: Barebox List
On Mon, Nov 05, 2018 at 03:16:52PM -0800, Andrey Smirnov wrote:
> On Mon, Nov 5, 2018 at 7:51 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >
> > The following series contains a bigger at91 header file cleanup. With
> > this the SoC header files become completely SoC namespaced which means
> > they can all be included as desired without conflicts. This makes the
> > way free for more at91 multiboard support.
> >
> > I don't have that much AT91 hardware on my desk, so I am unable to test
> > this properly. Testing feedback very much appreciated. Sam maybe?
> >
>
> I applied the series on 'next' and ran it on my AT91SAM9x5 devkit with
> at91sam9g25 module. Didn't do anything sophisticated, just booted and
> made sure that USB port can enumerate a USB stick, Ethernet pings and
> I can read data off MMC. FWIW:
Thanks for testing Andrey. That sounds promising. I myself ran it on a
sama5d3 board.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/22] AT91 header cleanup
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
` (22 preceding siblings ...)
2018-11-05 23:16 ` [PATCH 00/22] AT91 header cleanup Andrey Smirnov
@ 2018-11-07 10:12 ` Ladislav Michl
2018-11-08 8:11 ` Sascha Hauer
23 siblings, 1 reply; 27+ messages in thread
From: Ladislav Michl @ 2018-11-07 10:12 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Mon, Nov 05, 2018 at 04:50:51PM +0100, Sascha Hauer wrote:
> The following series contains a bigger at91 header file cleanup. With
> this the SoC header files become completely SoC namespaced which means
> they can all be included as desired without conflicts. This makes the
> way free for more at91 multiboard support.
>
> I don't have that much AT91 hardware on my desk, so I am unable to test
> this properly. Testing feedback very much appreciated. Sam maybe?
Tested on custom AT91SAM9G20 based board. However as patch
"ARM: at91: separate restart handler registration into SoC specific code"
does exactly what its commit message says it brings some issues with
devicetree based boot. Nearly everything works except NAND and that would
work too if one uses old binding. As that is not my case, I'm using pdata
to register NAND, so I need also:
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d81683ac1..75442bd72 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -18,11 +18,12 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic
obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o
ifeq ($(CONFIG_OFDEVICE),)
obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o
+obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o
endif
-obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
Note, that with above change, once we move to device tree, there's noone
to register restart handler. I guess, that will get eventually sorted
by writing proper reset driver, right? For now I put reset handler
registration into a board file.
Above is just extraordinary long way to say, that without updating
Barebox' MTD code it is hard to move to full DT boot and someone
should start testing ;-)
Best regards,
ladis
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^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH 00/22] AT91 header cleanup
2018-11-07 10:12 ` Ladislav Michl
@ 2018-11-08 8:11 ` Sascha Hauer
0 siblings, 0 replies; 27+ messages in thread
From: Sascha Hauer @ 2018-11-08 8:11 UTC (permalink / raw)
To: Ladislav Michl; +Cc: Barebox List
On Wed, Nov 07, 2018 at 11:12:35AM +0100, Ladislav Michl wrote:
> On Mon, Nov 05, 2018 at 04:50:51PM +0100, Sascha Hauer wrote:
> > The following series contains a bigger at91 header file cleanup. With
> > this the SoC header files become completely SoC namespaced which means
> > they can all be included as desired without conflicts. This makes the
> > way free for more at91 multiboard support.
> >
> > I don't have that much AT91 hardware on my desk, so I am unable to test
> > this properly. Testing feedback very much appreciated. Sam maybe?
>
> Tested on custom AT91SAM9G20 based board. However as patch
> "ARM: at91: separate restart handler registration into SoC specific code"
> does exactly what its commit message says it brings some issues with
> devicetree based boot. Nearly everything works except NAND and that would
> work too if one uses old binding. As that is not my case, I'm using pdata
> to register NAND, so I need also:
>
> diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
> index d81683ac1..75442bd72 100644
> --- a/arch/arm/mach-at91/Makefile
> +++ b/arch/arm/mach-at91/Makefile
> @@ -18,11 +18,12 @@ obj-$(CONFIG_ARCH_AT91RM9200) += at91rm9200.o at91rm9200_time.o at91rm9200_devic
> obj-$(CONFIG_ARCH_AT91SAM9260) += at91sam9260.o at91sam9260_devices.o
> obj-$(CONFIG_ARCH_AT91SAM9261) += at91sam9261.o at91sam9261_devices.o
> obj-$(CONFIG_ARCH_AT91SAM9G10) += at91sam9261.o at91sam9261_devices.o
> +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260_devices.o
> ifeq ($(CONFIG_OFDEVICE),)
> obj-$(CONFIG_ARCH_AT91SAM9263) += at91sam9263.o at91sam9263_devices.o
> obj-$(CONFIG_ARCH_SAMA5D3) += sama5d3.o sama5d3_devices.o
> +obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o
> endif
> -obj-$(CONFIG_ARCH_AT91SAM9G20) += at91sam9260.o at91sam9260_devices.o
> obj-$(CONFIG_ARCH_AT91SAM9G45) += at91sam9g45.o at91sam9g45_devices.o
> obj-$(CONFIG_ARCH_AT91SAM9X5) += at91sam9x5.o at91sam9x5_devices.o
> obj-$(CONFIG_ARCH_AT91SAM9N12) += at91sam9n12.o at91sam9n12_devices.o
>
> Note, that with above change, once we move to device tree, there's noone
> to register restart handler. I guess, that will get eventually sorted
> by writing proper reset driver, right? For now I put reset handler
> registration into a board file.
On i.MX I have split the SoC init code into code that has always to be
executed and code that has only to be executed without devicetree
support. We can do the same on AT91 as a next step.
Writing a proper reset driver is probably a good step but not required.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 27+ messages in thread
end of thread, other threads:[~2018-11-08 8:11 UTC | newest]
Thread overview: 27+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-11-05 15:50 [PATCH 00/22] AT91 header cleanup Sascha Hauer
2018-11-05 15:50 ` [PATCH 01/22] ARM: at91: remove unused AT_DMA_ID_ defines Sascha Hauer
2018-11-05 15:50 ` [PATCH 02/22] ARM: at91: remove unused CONSISTENT_DMA_SIZE defines Sascha Hauer
2018-11-05 15:50 ` [PATCH 03/22] ARM: at91rm9200ek: Use SoC specific defines Sascha Hauer
2018-11-05 15:50 ` [PATCH 04/22] ARM: at91sam926x: Add header for at91sam926x common base addresses Sascha Hauer
2018-11-05 15:50 ` [PATCH 05/22] ARM: at91: remove unused defines Sascha Hauer
2018-11-05 15:50 ` [PATCH 06/22] ARM: at91: drop AT91_NB_USART Sascha Hauer
2018-11-05 15:50 ` [PATCH 07/22] ARM: at91: remove AT91_SDRAM_BASE Sascha Hauer
2018-11-05 15:50 ` [PATCH 08/22] ARM: at91: consolidate phy reset functions Sascha Hauer
2018-11-05 15:51 ` [PATCH 09/22] ARM: at91: remove common matrix header file Sascha Hauer
2018-11-05 15:51 ` [PATCH 10/22] ARM: at91: Add SoC namespace to matrix defines Sascha Hauer
2018-11-05 15:51 ` [PATCH 11/22] ARM: at91: Use SoC specific base addresses where appropriate Sascha Hauer
2018-11-05 15:51 ` [PATCH 12/22] ARM: at91rm9200: Add SoC namespace to memory controller defines Sascha Hauer
2018-11-05 15:51 ` [PATCH 13/22] ARM: at91: remove unused header file Sascha Hauer
2018-11-05 15:51 ` [PATCH 14/22] ARM: at91rm9200 timer: remove unused include Sascha Hauer
2018-11-05 15:51 ` [PATCH 15/22] ARM: at91rm9200 timer: Make system timer defines SoC specific Sascha Hauer
2018-11-05 15:51 ` [PATCH 16/22] ARM: at91: remove mach/io.h Sascha Hauer
2018-11-05 15:51 ` [PATCH 17/22] ARM: at91sam926x use writel rather than pmc accessor function Sascha Hauer
2018-11-05 15:51 ` [PATCH 18/22] ARM: at91rm9200ek: use plain readl/writel for pmc accesses Sascha Hauer
2018-11-05 15:51 ` [PATCH 19/22] ARM: at91: drop at91_pmc_write()/at91_pmc_read() Sascha Hauer
2018-11-05 15:51 ` [PATCH 20/22] ARM: at91: make at91sam926x_board_init board specific Sascha Hauer
2018-11-05 15:51 ` [PATCH 21/22] ARM: at91: separate restart handler registration into SoC specific code Sascha Hauer
2018-11-05 15:51 ` [PATCH 22/22] ARM: at91: remove unused defines Sascha Hauer
2018-11-05 23:16 ` [PATCH 00/22] AT91 header cleanup Andrey Smirnov
2018-11-06 8:58 ` Sascha Hauer
2018-11-07 10:12 ` Ladislav Michl
2018-11-08 8:11 ` Sascha Hauer
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