From: Michael Tretter <m.tretter@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Michael Tretter <m.tretter@pengutronix.de>
Subject: [PATCH 2/3] ARM: aarch64: compile with general-regs-only
Date: Fri, 23 Nov 2018 14:35:52 +0100 [thread overview]
Message-ID: <20181123133553.24761-3-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20181123133553.24761-1-m.tretter@pengutronix.de>
Without this flag, gcc generates code to save the Q/V registers to the
stack for handling the va_list in pr_print(). Saving the registers is
use useless, as the registers are never restored, but this hangs the
CPU.
Follow the Linux arch/arm64/Makefile and the general-regs-only flag, to
prevent usage of floating point and Advanced SIMD register.
Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
arch/arm/Makefile | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5db67b9db8..50958b787f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -27,6 +27,10 @@ else
CFLAGS += -mstrict-align
endif
+# Prevent use of floating point and Advanced SIMD registers.
+ifeq ($(CONFIG_CPU_V8),y)
+CFLAGS += -mgeneral-regs-only
+endif
# This selects which instruction set is used.
# Note that GCC does not numerically define an architecture version
--
2.19.1
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next prev parent reply other threads:[~2018-11-23 13:36 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-23 13:35 [PATCH 0/3] Xilinx Zynq Ultrascale+ MPSoC support Michael Tretter
2018-11-23 13:35 ` [PATCH 1/3] ARM: lib64: .gitignore barebox.lds Michael Tretter
2018-11-23 13:35 ` Michael Tretter [this message]
2018-11-23 13:48 ` [PATCH 2/3] ARM: aarch64: compile with general-regs-only Rouven Czerwinski
2018-11-23 13:35 ` [PATCH 3/3] ARM: zynqmp: add support for Xilinx ZCU104 board Michael Tretter
2018-11-23 13:55 ` Rouven Czerwinski
2018-11-26 10:37 ` Roland Hieber
2018-11-23 14:38 ` Michael Tretter
2018-11-23 15:08 ` Oleksij Rempel
2018-11-23 18:27 ` Michael Tretter
2018-11-23 18:41 ` Oleksij Rempel
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