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From: Michael Tretter <m.tretter@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Michael Tretter <m.tretter@pengutronix.de>
Subject: [PATCH v2 2/4] ARM: aarch64: compile with general-regs-only
Date: Wed, 28 Nov 2018 12:20:51 +0100	[thread overview]
Message-ID: <20181128112053.6027-3-m.tretter@pengutronix.de> (raw)
In-Reply-To: <20181128112053.6027-1-m.tretter@pengutronix.de>

Without this flag, gcc generates code to save the Q/V registers to the
stack for handling the va_list in pr_print(). Saving the registers is
useless, as the registers are never restored, but accessing the
registers to save them hangs the CPU.

Follow the Linux arch/arm64/Makefile and use the general-regs-only flag
to prevent usage of floating point and Advanced SIMD register.

Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
---
 arch/arm/Makefile | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5db67b9db8..50958b787f 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -27,6 +27,10 @@ else
 CFLAGS += -mstrict-align
 endif
 
+# Prevent use of floating point and Advanced SIMD registers.
+ifeq ($(CONFIG_CPU_V8),y)
+CFLAGS += -mgeneral-regs-only
+endif
 
 # This selects which instruction set is used.
 # Note that GCC does not numerically define an architecture version
-- 
2.19.1


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  parent reply	other threads:[~2018-11-28 11:21 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-11-28 11:20 [PATCH v2 0/4] Xilinx Zynq Ultrascale+ MPSoC support Michael Tretter
2018-11-28 11:20 ` [PATCH v2 1/4] ARM: lib64: .gitignore barebox.lds Michael Tretter
2018-11-28 11:20 ` Michael Tretter [this message]
2018-11-28 11:20 ` [PATCH v2 3/4] ARM: aarch64: add ENTRY_PROC macro for arm64 Michael Tretter
2018-11-28 11:20 ` [PATCH v2 4/4] ARM: zynqmp: add support for Xilinx ZCU104 board Michael Tretter
2018-11-28 13:13 ` [PATCH v2 0/4] Xilinx Zynq Ultrascale+ MPSoC support Antony Pavlov
2018-11-29  8:14   ` Sascha Hauer
2018-11-29  9:50     ` Roland Hieber
2018-11-29 10:37       ` Sascha Hauer
2018-12-07 10:11 ` [PATCH v3 " Michael Tretter
2018-12-07 10:11   ` [PATCH v3 1/4] ARM: lib64: .gitignore barebox.lds Michael Tretter
2018-12-07 10:11   ` [PATCH v3 2/4] ARM: aarch64: compile with general-regs-only Michael Tretter
2018-12-07 10:11   ` [PATCH v3 3/4] ARM: aarch64: add ENTRY_PROC macro for arm64 Michael Tretter
2018-12-07 10:11   ` [PATCH v3 4/4] ARM: zynqmp: add support for Xilinx ZCU104 board Michael Tretter
2018-12-10  9:13   ` [PATCH v3 0/4] Xilinx Zynq Ultrascale+ MPSoC support Sascha Hauer

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