* [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port
@ 2018-12-05 15:40 Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 2/3] ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1 Stefan Riedmueller
` (2 more replies)
0 siblings, 3 replies; 4+ messages in thread
From: Stefan Riedmueller @ 2018-12-05 15:40 UTC (permalink / raw)
To: barebox
The phyBOARD-Segin baseboard of the phyCORE-i.MX 6UL features a USB
type A connector on the second USB OTG port of the i.MX 6UL. So enable this
port as a host port.
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 4 ++++
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 73f7dbe9a6b3..509424347082 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -39,3 +39,7 @@
&usdhc1 {
status = "okay";
};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 2504c9729dd1..05bf18d6f1b2 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -89,6 +89,12 @@
status = "disabled";
};
+&usbotg2 {
+ dr_mode = "host";
+ disable-over-current;
+ status = "disabled";
+};
+
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
--
2.7.4
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 2/3] ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1
2018-12-05 15:40 [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Stefan Riedmueller
@ 2018-12-05 15:40 ` Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 3/3] ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL Stefan Riedmueller
2018-12-06 8:10 ` [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Stefan Riedmueller @ 2018-12-05 15:40 UTC (permalink / raw)
To: barebox; +Cc: Fabian Godehardt
From: Fabian Godehardt <fg@emlix.com>
Enable USB OTG support on USB OTG port 1 of the phyCORE-i.MX 6UL/ULL.
Signed-off-by: Fabian Godehardt <fg@emlix.com>
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/dts/imx6ul-phytec-phycore-som.dts | 4 ++++
arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 14 ++++++++++++++
arch/arm/dts/imx6ull-phytec-phycore-som.dts | 4 ++++
3 files changed, 22 insertions(+)
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
index 509424347082..6d1876702d1b 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
@@ -40,6 +40,10 @@
status = "okay";
};
+&usbotg1 {
+ status = "okay";
+};
+
&usbotg2 {
status = "okay";
};
diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index 05bf18d6f1b2..d829fdd6fb29 100644
--- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -89,6 +89,14 @@
status = "disabled";
};
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_otg1>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "disabled";
+};
+
&usbotg2 {
dr_mode = "host";
disable-over-current;
@@ -169,6 +177,12 @@
>;
};
+ pinctrl_usb_otg1: usbotg1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index de04132a02e7..ce631460caea 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -39,3 +39,7 @@
&usdhc1 {
status = "okay";
};
+
+&usbotg1 {
+ status = "okay";
+};
--
2.7.4
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^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 3/3] ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL
2018-12-05 15:40 [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 2/3] ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1 Stefan Riedmueller
@ 2018-12-05 15:40 ` Stefan Riedmueller
2018-12-06 8:10 ` [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Stefan Riedmueller @ 2018-12-05 15:40 UTC (permalink / raw)
To: barebox
The phyCORE-i.MX 6ULL now comes in a full featured (Y2 variant) and a
low cost (Y0 variant) version. The main difference for the barebox is
the missing second USB OTG port on the Y0 variant and the RAM configuration.
So to account for these differences the existing low cost version is
renamed and the full featured version added.
The results are following phyCORE-i.MX 6ULL modules:
phyCORE-i.MX 6ULL low cost:
- i.MX 6ULL Y0
- 256 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
phyCORE-i.MX 6ULL full featured:
- i.MX 6ULL Y2
- 512 MB RAM
- NAND
- Ethernet 10/100 MBits
- USB OTG
- USB Host
Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
---
arch/arm/boards/phytec-som-imx6/lowlevel.c | 3 +-
arch/arm/dts/Makefile | 1 +
arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts | 39 ++++++++++++++++++++++++++
arch/arm/dts/imx6ull-phytec-phycore-som.dts | 4 +++
images/Makefile.imx | 13 ++++++---
5 files changed, 55 insertions(+), 5 deletions(-)
create mode 100644 arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
diff --git a/arch/arm/boards/phytec-som-imx6/lowlevel.c b/arch/arm/boards/phytec-som-imx6/lowlevel.c
index 05f918f6c9c0..9d81c278ca43 100644
--- a/arch/arm/boards/phytec-som-imx6/lowlevel.c
+++ b/arch/arm/boards/phytec-som-imx6/lowlevel.c
@@ -116,4 +116,5 @@ PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_1gib, imx6q_phytec_phycore_som_
PHYTEC_ENTRY(start_phytec_phycore_imx6q_som_emmc_2gib, imx6q_phytec_phycore_som_emmc, SZ_2G, true);
PHYTEC_ENTRY(start_phytec_phycore_imx6ul_som_512mb, imx6ul_phytec_phycore_som, SZ_512M, false);
-PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_256mb, imx6ull_phytec_phycore_som, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_lc_256mb, imx6ull_phytec_phycore_som_lc, SZ_256M, false);
+PHYTEC_ENTRY(start_phytec_phycore_imx6ull_som_512mb, imx6ull_phytec_phycore_som, SZ_512M, false);
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 503d9b18f9c1..c08b35a10132 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -63,6 +63,7 @@ pbl-dtb-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += imx6q-phytec-pbaa03.dtb.o \
imx6dl-phytec-phycore-som-nand.dtb.o \
imx6dl-phytec-phycore-som-emmc.dtb.o \
imx6ul-phytec-phycore-som.dtb.o \
+ imx6ull-phytec-phycore-som-lc.dtb.o \
imx6ull-phytec-phycore-som.dtb.o
pbl-dtb-$(CONFIG_MACH_PHYTEC_PHYCORE_IMX7) += imx7d-phyboard-zeta.dtb.o
pbl-dtb-$(CONFIG_MACH_PLATHOME_OPENBLOCKS_AX3) += armada-xp-openblocks-ax3-4-bb.dtb.o
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
new file mode 100644
index 000000000000..94a783075651
--- /dev/null
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som-lc.dts
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
+/*
+ * Copyright (C) 2018 PHYTEC Messtechnik GmbH
+ * Author: Stefan Riedmueller <s.riedmueller@phytec.de>
+ */
+
+/dts-v1/;
+
+#include <arm/imx6ull.dtsi>
+#include "imx6ul-phytec-phycore-som.dtsi"
+
+/ {
+ model = "Phytec phyCORE-i.MX6 ULL SOM low-cost";
+ compatible = "phytec,imx6ul-pcl063", "fsl,imx6ull";
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&gpmi {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&usdhc1 {
+ status = "okay";
+};
+
+&usbotg1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/imx6ull-phytec-phycore-som.dts b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
index ce631460caea..4d73010131ee 100644
--- a/arch/arm/dts/imx6ull-phytec-phycore-som.dts
+++ b/arch/arm/dts/imx6ull-phytec-phycore-som.dts
@@ -43,3 +43,7 @@
&usbotg1 {
status = "okay";
};
+
+&usbotg2 {
+ status = "okay";
+};
diff --git a/images/Makefile.imx b/images/Makefile.imx
index 9b5cd577d285..507e20a7c6ce 100644
--- a/images/Makefile.imx
+++ b/images/Makefile.imx
@@ -471,10 +471,15 @@ CFG_start_phytec_phycore_imx6ul_som_512mb.pblx.imximg = $(board)/phytec-som-imx6
FILE_barebox-phytec-phycore-imx6ul-512mb.img = start_phytec_phycore_imx6ul_som_512mb.pblx.imximg
image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ul-512mb.img
-pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_256mb
-CFG_start_phytec_phycore_imx6ull_som_256mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
-FILE_barebox-phytec-phycore-imx6ull-256mb.img = start_phytec_phycore_imx6ull_som_256mb.pblx.imximg
-image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-256mb.img
+pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_lc_256mb
+CFG_start_phytec_phycore_imx6ull_som_lc_256mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-256mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-lc-256mb.img = start_phytec_phycore_imx6ull_som_lc_256mb.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-lc-256mb.img
+
+pblx-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += start_phytec_phycore_imx6ull_som_512mb
+CFG_start_phytec_phycore_imx6ull_som_512mb.pblx.imximg = $(board)/phytec-som-imx6/flash-header-phytec-pcl063-512mb.imxcfg
+FILE_barebox-phytec-phycore-imx6ull-512mb.img = start_phytec_phycore_imx6ull_som_512mb.pblx.imximg
+image-$(CONFIG_MACH_PHYTEC_SOM_IMX6) += barebox-phytec-phycore-imx6ull-512mb.img
pblx-$(CONFIG_MACH_KONTRON_SAMX6I) += start_imx6q_samx6i
CFG_start_imx6q_samx6i.pblx.imximg = $(board)/kontron-samx6i/flash-header-samx6i-quad.imxcfg
--
2.7.4
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port
2018-12-05 15:40 [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 2/3] ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1 Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 3/3] ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL Stefan Riedmueller
@ 2018-12-06 8:10 ` Sascha Hauer
2 siblings, 0 replies; 4+ messages in thread
From: Sascha Hauer @ 2018-12-06 8:10 UTC (permalink / raw)
To: Stefan Riedmueller; +Cc: barebox
On Wed, Dec 05, 2018 at 04:40:35PM +0100, Stefan Riedmueller wrote:
> The phyBOARD-Segin baseboard of the phyCORE-i.MX 6UL features a USB
> type A connector on the second USB OTG port of the i.MX 6UL. So enable this
> port as a host port.
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/dts/imx6ul-phytec-phycore-som.dts | 4 ++++
> arch/arm/dts/imx6ul-phytec-phycore-som.dtsi | 6 ++++++
> 2 files changed, 10 insertions(+)
Applied, thanks
Sascha
>
> diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dts b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
> index 73f7dbe9a6b3..509424347082 100644
> --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dts
> +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dts
> @@ -39,3 +39,7 @@
> &usdhc1 {
> status = "okay";
> };
> +
> +&usbotg2 {
> + status = "okay";
> +};
> diff --git a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
> index 2504c9729dd1..05bf18d6f1b2 100644
> --- a/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
> +++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
> @@ -89,6 +89,12 @@
> status = "disabled";
> };
>
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + status = "disabled";
> +};
> +
> &usdhc1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_usdhc1>;
> --
> 2.7.4
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
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end of thread, other threads:[~2018-12-06 8:10 UTC | newest]
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2018-12-05 15:40 [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 2/3] ARM: dts: phyCORE-i.MX 6UL/ULL: Enable USB OTG on port 1 Stefan Riedmueller
2018-12-05 15:40 ` [PATCH 3/3] ARM: phytec-som-imx6: Add full featured phyCORE-i.MX 6ULL Stefan Riedmueller
2018-12-06 8:10 ` [PATCH 1/3] ARM: dts: phyCORE-i.MX 6UL: Enable USB host port Sascha Hauer
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