[PATCH 17/58] PCI: designware: Remove incorrect RC memory base/limit configuration

[Andrey Smirnov <andrew.smirnov@gmail.com>]

Port of a Linux commit a5cb903aef8c642e6f0f6810d46dacedf666b54a

  Currently dw_pcie_setup_rc() configures memory base and memory limit in the
  type1 configuration header for the root complex.  In doing so it uses the
  CPU address (pp->mem_base) rather than the bus address (pp->mem_bus_addr).
  This is wrong and it is useless since the configuration is overwritten
  later on when pci_bus_assign_resources() is called.

  Remove this configuration from dw_pcie_setup_rc().

  Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
  Acked-by: Pratyush Anand <pratyush.anand@gmail.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/pci/pcie-designware.c | 8 --------
 1 file changed, 8 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 5e824cedc..e9058768d 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -489,8 +489,6 @@ static struct pci_ops dw_pcie_ops = {
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
 	u32 val;
-	u32 membase;
-	u32 memlimit;
 
 	/* set the number of lanes */
 	dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
@@ -537,12 +535,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	val |= 0x00010100;
 	dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
 
-	/* setup memory base, memory limit */
-	membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
-	memlimit = (pp->mem_size + (u32)pp->mem_base) & 0xfff00000;
-	val = memlimit | membase;
-	dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
-
 	/* setup command register */
 	dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
 	val &= 0xffff0000;
-- 
2.19.1


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