[PATCH 00/23] AM3517 support

[PATCH 00/23] AM3517 support

[Sascha Hauer]

This series adds support for the TI AM3517 SoC along with Wago PFC-200
board support. Also in this series some TI related driver patches. Most
notably some significant chages to the GPMC Nand driver which was not
really working anymore.

Sascha

Heinrich Toews (3):
  net: davinci-emac: fix buggy channel tear down
  net: davinci-emac: switch to device tree support
  ARM: omap: AM3517: Change default clock rate for AM3517

Oleg Karfich (1):
  ARM: omap3: Add support for reset reason detection

Sascha Hauer (19):
  net: davinci-emac: Add timeout to polling loop
  mci: omap: Improve error handling
  mci: omap: use IS_ENABLED() rather than #ifdef
  mtd: nand: omap: Use dev_dbg when a struct device * is available
  mtd: nand: omap: Fix hamming correct return values
  mtd: nand: omap: Disable subpage reads in hardware ecc mode
  mtd: nand: omap: remove unused function argument
  mtd: nand: omap: fix bch8_hw_romcode ecc layout
  mtd: nand: omap: set eccbytes correctly
  mtd: nand: omap: unbreak BCH8 support
  ARM: omap: Add missing include
  ARM: omap: dmtimer: Turn into a driver
  ARM: omap: 32ktimer: Turn into a driver
  ARM: omap: Add AM35XX support
  ARM: omap: enable am33xx_uart_soft_reset for AM35xx
  ARM: omap: Add AM3517 specific mux configuration
  ARM: omap: Add emif4 support for AM3517
  ARM: omap: Add board support for WAGO pfc200 platform
  ARM: omap: am33xx_defconfig: Enable more boards and rename

 arch/arm/boards/Makefile                      |   1 +
 arch/arm/boards/wago-pfc-am35xx/Makefile      |   6 +
 arch/arm/boards/wago-pfc-am35xx/board-mlo.c   |  73 +++
 arch/arm/boards/wago-pfc-am35xx/board.c       |  39 ++
 arch/arm/boards/wago-pfc-am35xx/lowlevel.c    | 231 +++++++++
 .../arm/configs/am35xx_pfc200_xload_defconfig |  40 ++
 .../{am335x_defconfig => omap_defconfig}      |   5 +-
 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/am35xx-pfc-750_820x.dts          | 487 ++++++++++++++++++
 arch/arm/dts/am3xxx-pfc-nandparts.dtsi        |  63 +++
 arch/arm/mach-omap/Kconfig                    |  24 +-
 arch/arm/mach-omap/Makefile                   |   5 +-
 arch/arm/mach-omap/am33xx_generic.c           |  32 +-
 arch/arm/mach-omap/am35xx_emif4.c             |  85 +++
 arch/arm/mach-omap/am3xxx.c                   |  32 ++
 .../mach-omap/include/mach/am3xxx-silicon.h   |   6 +
 arch/arm/mach-omap/include/mach/emif4.h       | 105 ++++
 arch/arm/mach-omap/include/mach/omap3-clock.h |   2 +
 arch/arm/mach-omap/include/mach/omap3-mux.h   |  49 +-
 arch/arm/mach-omap/include/mach/sys_info.h    |   2 +
 arch/arm/mach-omap/omap3_clock.c              |  16 +-
 arch/arm/mach-omap/omap3_generic.c            |  58 ++-
 arch/arm/mach-omap/omap4_generic.c            |   5 +-
 drivers/clocksource/Kconfig                   |   6 +
 drivers/clocksource/Makefile                  |   2 +
 .../clocksource/timer-ti-32k.c                |  39 +-
 .../clocksource/timer-ti-dm.c                 |  47 +-
 drivers/mci/omap_hsmmc.c                      |  37 +-
 drivers/mtd/nand/nand_omap_gpmc.c             | 141 +++--
 drivers/net/davinci_emac.c                    | 210 +++++---
 images/Makefile                               |   1 +
 images/Makefile.am35xx                        |  24 +
 include/platform_data/eth-davinci-emac.h      |  10 -
 33 files changed, 1657 insertions(+), 227 deletions(-)
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/Makefile
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/board-mlo.c
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/board.c
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/lowlevel.c
 create mode 100644 arch/arm/configs/am35xx_pfc200_xload_defconfig
 rename arch/arm/configs/{am335x_defconfig => omap_defconfig} (96%)
 create mode 100644 arch/arm/dts/am35xx-pfc-750_820x.dts
 create mode 100644 arch/arm/dts/am3xxx-pfc-nandparts.dtsi
 create mode 100644 arch/arm/mach-omap/am35xx_emif4.c
 create mode 100644 arch/arm/mach-omap/am3xxx.c
 create mode 100644 arch/arm/mach-omap/include/mach/am3xxx-silicon.h
 create mode 100644 arch/arm/mach-omap/include/mach/emif4.h
 rename arch/arm/mach-omap/s32k_clksource.c => drivers/clocksource/timer-ti-32k.c (73%)
 rename arch/arm/mach-omap/dmtimer.c => drivers/clocksource/timer-ti-dm.c (72%)
 create mode 100644 images/Makefile.am35xx
 delete mode 100644 include/platform_data/eth-davinci-emac.h

-- 
2.19.1


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[PATCH 01/23] net: davinci-emac: fix buggy channel tear down

[Sascha Hauer]

From: Heinrich Toews <heinrich.toews@wago.com>

Druing a barebox_shutdown() already probed platform devices are being halted.
While trying to halt the davinci emac a channel tear down operation is triggered
which leads due to a missing DMA pointer configuration to a memory corruption
whithin the decompressed kernel memory. In this case the devices failed to boot
and are completely freezed.

In the davinci driver DMA initialisation is only done during the opening of the
device which is done only when the device is setup for communication.

The problem was solved by adding DMA init code to emacs_init() which is called
shortly after the probing of the device. In this case the tearing down of the
channels completes successfully.

Signed-off-by: Oleg Karfich <oleg.karfich@wago.com>
---
 drivers/net/davinci_emac.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 2fccd4681e..2f6091d155 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -173,6 +173,17 @@ static int davinci_emac_set_ethaddr(struct eth_device *edev, const unsigned char
 
 static int davinci_emac_init(struct eth_device *edev)
 {
+	struct davinci_emac_priv *priv = edev->priv;
+	uint32_t cnt;
+
+	/* Set DMA head and completion pointers to 0 */
+	for(cnt = 0; cnt < 8; cnt++) {
+		writel(0, (void *)priv->adap_emac + EMAC_TX0HDP + 4 * cnt);
+		writel(0, (void *)priv->adap_emac + EMAC_RX0HDP + 4 * cnt);
+		writel(0, (void *)priv->adap_emac + EMAC_TX0CP + 4 * cnt);
+		writel(0, (void *)priv->adap_emac + EMAC_RX0CP + 4 * cnt);
+	}
+
 	dev_dbg(&edev->dev, "* emac_init\n");
 	return 0;
 }
-- 
2.19.1


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[PATCH 02/23] net: davinci-emac: Add timeout to polling loop

[Sascha Hauer]

Do not poll forever when the hardware does not behave like we want to.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/net/davinci_emac.c | 47 ++++++++++++++++++++++++++++++--------
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index 2f6091d155..bda62214ef 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -105,13 +105,40 @@ static void davinci_eth_mdio_enable(struct davinci_emac_priv *priv)
 	while (readl(priv->adap_mdio + EMAC_MDIO_CONTROL) & MDIO_CONTROL_IDLE);
 }
 
+/* wait until hardware is ready for another user access */
+static int wait_for_user_access(struct davinci_emac_priv *priv, uint32_t *val)
+{
+	u32 tmp;
+	uint64_t start = get_time_ns();
+
+	do {
+		tmp = readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0);
+
+		if (!(tmp & MDIO_USERACCESS0_GO))
+			break;
+
+		if (is_timeout(start, 100 * MSECOND)) {
+			dev_err(priv->dev, "timeout waiting for user access\n");
+			return -ETIMEDOUT;
+		}
+	} while (1);
+
+	if (val)
+		*val = tmp;
+
+	return 0;
+}
+
+
 static int davinci_miibus_read(struct mii_bus *bus, int addr, int reg)
 {
 	struct davinci_emac_priv *priv = bus->priv;
 	uint16_t value;
-	int tmp;
+	int tmp, ret;
 
-	while (readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+	ret = wait_for_user_access(priv, NULL);
+	if (ret)
+		return ret;
 
 	writel(MDIO_USERACCESS0_GO |
 		MDIO_USERACCESS0_WRITE_READ |
@@ -119,8 +146,9 @@ static int davinci_miibus_read(struct mii_bus *bus, int addr, int reg)
 		((addr & 0x1f) << 16),
 		priv->adap_mdio + EMAC_MDIO_USERACCESS0);
 
-	/* Wait for command to complete */
-	while ((tmp = readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0)) & MDIO_USERACCESS0_GO);
+	ret = wait_for_user_access(priv, &tmp);
+	if (ret)
+		return ret;
 
 	if (tmp & MDIO_USERACCESS0_ACK) {
 		value = tmp & 0xffff;
@@ -135,7 +163,11 @@ static int davinci_miibus_read(struct mii_bus *bus, int addr, int reg)
 static int davinci_miibus_write(struct mii_bus *bus, int addr, int reg, u16 value)
 {
 	struct davinci_emac_priv *priv = bus->priv;
-	while (readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
+	int ret;
+
+	ret = wait_for_user_access(priv, NULL);
+	if (ret)
+		return ret;
 
 	dev_dbg(priv->dev, "davinci_miibus_write: addr=0x%02x reg=0x%02x value=0x%04x\n",
 		   addr, reg, value);
@@ -146,10 +178,7 @@ static int davinci_miibus_write(struct mii_bus *bus, int addr, int reg, u16 valu
 				(value & 0xffff),
 		priv->adap_mdio + EMAC_MDIO_USERACCESS0);
 
-	/* Wait for command to complete */
-	while (readl(priv->adap_mdio + EMAC_MDIO_USERACCESS0) & MDIO_USERACCESS0_GO);
-
-	return 0;
+	return wait_for_user_access(priv, NULL);
 }
 
 static int davinci_emac_get_ethaddr(struct eth_device *edev, unsigned char *adr)
-- 
2.19.1


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[PATCH 03/23] net: davinci-emac: switch to device tree support

[Sascha Hauer]

From: Heinrich Toews <heinrich.toews@wago.com>

This adds device tree support to the davinci-emac driver.

This needs some changes to the driver as the device has four different
resources. Three of them are merged into a single resource in the
dts files with the node providing offsets for the different resources
to base address. The mdio node is found separately in the dts, so we
have to split this out to a different driver. Since this driver has been
unused previously, we do not bother maintaining two different probe
methods and remove platform probe support at the same time.

Signed-off-by: Heinrich Toews <heinrich.toews@wago.com>
Signed-off-by: Sascha Hauer, <s.hauer@pengutronix.de>
---
 drivers/net/davinci_emac.c               | 154 +++++++++++++----------
 include/platform_data/eth-davinci-emac.h |  10 --
 2 files changed, 85 insertions(+), 79 deletions(-)
 delete mode 100644 include/platform_data/eth-davinci-emac.h

diff --git a/drivers/net/davinci_emac.c b/drivers/net/davinci_emac.c
index bda62214ef..ff35b746e2 100644
--- a/drivers/net/davinci_emac.c
+++ b/drivers/net/davinci_emac.c
@@ -32,18 +32,16 @@
 #include <asm/system.h>
 #include <linux/phy.h>
 #include <mach/emac_defs.h>
-#include <platform_data/eth-davinci-emac.h>
+#include <of_net.h>
 #include "davinci_emac.h"
 
 struct davinci_emac_priv {
 	struct device_d *dev;
 	struct eth_device edev;
-	struct mii_bus miibus;
 
 	/* EMAC Addresses */
 	void __iomem *adap_emac; /* = EMAC_BASE_ADDR */
 	void __iomem *adap_ewrap; /* = EMAC_WRAPPER_BASE_ADDR */
-	void __iomem *adap_mdio; /* = EMAC_MDIO_BASE_ADDR */
 
 	/* EMAC descriptors */
 	void __iomem *emac_desc_base; /* = EMAC_WRAPPER_RAM_ADDR */
@@ -58,8 +56,6 @@ struct davinci_emac_priv {
 
 	/* PHY-specific information */
 	phy_interface_t interface;
-	uint8_t phy_addr;
-	uint32_t phy_flags;
 
 	/* mac_addr[0] goes out on the wire first */
 	uint8_t mac_addr[6];
@@ -86,7 +82,13 @@ static inline void __iomem *HW_TO_BD(uint32_t x)
 #define HW_TO_BD(x)     (x)
 #endif
 
-static void davinci_eth_mdio_enable(struct davinci_emac_priv *priv)
+struct davinci_mdio_priv {
+	struct device_d *dev;
+	struct mii_bus miibus;
+	void __iomem *adap_mdio; /* = EMAC_MDIO_BASE_ADDR */
+};
+
+static void davinci_eth_mdio_enable(struct davinci_mdio_priv *priv)
 {
 	uint32_t	clkdiv;
 
@@ -106,7 +108,7 @@ static void davinci_eth_mdio_enable(struct davinci_emac_priv *priv)
 }
 
 /* wait until hardware is ready for another user access */
-static int wait_for_user_access(struct davinci_emac_priv *priv, uint32_t *val)
+static int wait_for_user_access(struct davinci_mdio_priv *priv, uint32_t *val)
 {
 	u32 tmp;
 	uint64_t start = get_time_ns();
@@ -132,7 +134,7 @@ static int wait_for_user_access(struct davinci_emac_priv *priv, uint32_t *val)
 
 static int davinci_miibus_read(struct mii_bus *bus, int addr, int reg)
 {
-	struct davinci_emac_priv *priv = bus->priv;
+	struct davinci_mdio_priv *priv = bus->priv;
 	uint16_t value;
 	int tmp, ret;
 
@@ -162,7 +164,7 @@ static int davinci_miibus_read(struct mii_bus *bus, int addr, int reg)
 
 static int davinci_miibus_write(struct mii_bus *bus, int addr, int reg, u16 value)
 {
-	struct davinci_emac_priv *priv = bus->priv;
+	struct davinci_mdio_priv *priv = bus->priv;
 	int ret;
 
 	ret = wait_for_user_access(priv, NULL);
@@ -220,7 +222,7 @@ static int davinci_emac_init(struct eth_device *edev)
 static int davinci_emac_open(struct eth_device *edev)
 {
 	struct davinci_emac_priv *priv = edev->priv;
-	uint32_t clkdiv, cnt;
+	uint32_t cnt;
 	void __iomem *rx_desc;
 	unsigned long mac_hi, mac_lo;
 	int ret;
@@ -322,16 +324,10 @@ static int davinci_emac_open(struct eth_device *edev)
 		EMAC_MACCONTROL_RMIISPEED_100),
 	       priv->adap_emac + EMAC_MACCONTROL);
 
-	/* Init MDIO & get link state */
-	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
-	writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
-		priv->adap_mdio + EMAC_MDIO_CONTROL);
-
 	/* Start receive process */
 	writel(BD_TO_HW(priv->emac_rx_desc), priv->adap_emac + EMAC_RX0HDP);
 
-	ret = phy_device_connect(edev, &priv->miibus, priv->phy_addr, NULL,
-	                         priv->phy_flags, priv->interface);
+	ret = phy_device_connect(edev, NULL, -1, NULL, 0, priv->interface);
 	if (ret)
 		return ret;
 
@@ -540,19 +536,13 @@ out:
 static int davinci_emac_probe(struct device_d *dev)
 {
 	struct resource *iores;
-	struct davinci_emac_platform_data *pdata;
 	struct davinci_emac_priv *priv;
-	uint64_t start;
-	uint32_t phy_mask;
+	uint32_t ctrl_reg_offset;
+	uint32_t ctrl_ram_offset;
+	struct device_node *np = dev->device_node;
 
 	dev_dbg(dev, "+ emac_probe\n");
 
-	if (!dev->platform_data) {
-		dev_err(dev, "no platform_data\n");
-		return -ENODEV;
-	}
-	pdata = dev->platform_data;
-
 	priv = xzalloc(sizeof(*priv));
 	dev->priv = priv;
 
@@ -561,22 +551,14 @@ static int davinci_emac_probe(struct device_d *dev)
 	iores = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(iores))
 		return PTR_ERR(iores);
-	priv->adap_emac = IOMEM(iores->start);
 
-	iores = dev_request_mem_resource(dev, 1);
-	if (IS_ERR(iores))
-		return PTR_ERR(iores);
 	priv->adap_ewrap = IOMEM(iores->start);
 
-	iores = dev_request_mem_resource(dev, 2);
-	if (IS_ERR(iores))
-		return PTR_ERR(iores);
-	priv->adap_mdio = IOMEM(iores->start);
+	of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", &ctrl_reg_offset);
+	priv->adap_emac = IOMEM(iores->start) + ctrl_reg_offset;
 
-	iores = dev_request_mem_resource(dev, 3);
-	if (IS_ERR(iores))
-		return PTR_ERR(iores);
-	priv->emac_desc_base = IOMEM(iores->start);
+	of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", &ctrl_ram_offset);
+	priv->emac_desc_base = IOMEM(iores->start) + ctrl_ram_offset;
 
 	/* EMAC descriptors */
 	priv->emac_rx_desc = priv->emac_desc_base + EMAC_RX_DESC_BASE;
@@ -598,37 +580,7 @@ static int davinci_emac_probe(struct device_d *dev)
 	priv->edev.set_ethaddr = davinci_emac_set_ethaddr;
 	priv->edev.parent = dev;
 
-	davinci_eth_mdio_enable(priv);
-
-	start = get_time_ns();
-	while (1) {
-		phy_mask = readl(priv->adap_mdio + EMAC_MDIO_ALIVE);
-		if (phy_mask) {
-			dev_info(dev, "detected phy mask 0x%x\n", phy_mask);
-			phy_mask = ~phy_mask;
-			break;
-		}
-		if (is_timeout(start, 256 * MSECOND)) {
-			dev_err(dev, "no live phy, scanning all\n");
-			phy_mask = 0;
-			break;
-		}
-	}
-
-	if (pdata->interface_rmii)
-		priv->interface = PHY_INTERFACE_MODE_RMII;
-	else
-		priv->interface = PHY_INTERFACE_MODE_MII;
-	priv->phy_addr = pdata->phy_addr;
-	priv->phy_flags = pdata->force_link ? PHYLIB_FORCE_LINK : 0;
-
-	priv->miibus.read = davinci_miibus_read;
-	priv->miibus.write = davinci_miibus_write;
-	priv->miibus.priv = priv;
-	priv->miibus.parent = dev;
-	priv->miibus.phy_mask = phy_mask;
-
-	mdiobus_register(&priv->miibus);
+	priv->interface = of_get_phy_mode(np);
 
 	eth_register(&priv->edev);
 
@@ -643,9 +595,73 @@ static void davinci_emac_remove(struct device_d *dev)
 	davinci_emac_halt(&priv->edev);
 }
 
+static __maybe_unused struct of_device_id davinci_emac_dt_ids[] = {
+	{
+		.compatible = "ti,am3517-emac",
+	}, {
+		/* sentinel */
+	}
+};
+
 static struct driver_d davinci_emac_driver = {
 	.name   = "davinci_emac",
 	.probe  = davinci_emac_probe,
 	.remove = davinci_emac_remove,
+	.of_compatible = DRV_OF_COMPAT(davinci_emac_dt_ids),
 };
 device_platform_driver(davinci_emac_driver);
+
+static int davinci_mdio_probe(struct device_d *dev)
+{
+	struct resource *iores;
+	struct davinci_mdio_priv *priv;
+	int ret;
+	uint32_t clkdiv;
+
+	priv = xzalloc(sizeof(*priv));
+
+	priv->dev = dev;
+	priv->miibus.read = davinci_miibus_read;
+	priv->miibus.write = davinci_miibus_write;
+	priv->miibus.priv = priv;
+	priv->miibus.parent = dev;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+
+	priv->adap_mdio = IOMEM(iores->start);
+
+	davinci_eth_mdio_enable(priv);
+
+	/* Init MDIO & get link state */
+	clkdiv = (EMAC_MDIO_BUS_FREQ / EMAC_MDIO_CLOCK_FREQ) - 1;
+	writel((clkdiv & 0xff) | MDIO_CONTROL_ENABLE | MDIO_CONTROL_FAULT,
+		priv->adap_mdio + EMAC_MDIO_CONTROL);
+
+	ret = mdiobus_register(&priv->miibus);
+	if (ret)
+		goto err;
+
+	return 0;
+
+err:
+	free(priv);
+
+	return ret;
+}
+
+static __maybe_unused struct of_device_id davinci_mdio_dt_ids[] = {
+	{
+		.compatible = "ti,davinci_mdio",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d davinci_mdio_driver = {
+	.name   = "davinci_mdio",
+	.probe  = davinci_mdio_probe,
+	.of_compatible = DRV_OF_COMPAT(davinci_mdio_dt_ids),
+};
+device_platform_driver(davinci_mdio_driver);
diff --git a/include/platform_data/eth-davinci-emac.h b/include/platform_data/eth-davinci-emac.h
deleted file mode 100644
index caead1fecf..0000000000
--- a/include/platform_data/eth-davinci-emac.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __NET_DAVINCI_EMAC_H__
-#define __NET_DAVINCI_EMAC_H__
-
-struct davinci_emac_platform_data {
-	int phy_addr;
-	bool force_link;
-	bool interface_rmii;
-};
-
-#endif /* __NET_DAVINCI_EMAC_H__ */
-- 
2.19.1


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[PATCH 04/23] mci: omap: Improve error handling

[Sascha Hauer]

Return proper error code from read/write functions rather than '1'. Also
add messages printing the status register to give a glue what went
wrong.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/omap_hsmmc.c | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c
index cbc69e4083..9e7ecabf85 100644
--- a/drivers/mci/omap_hsmmc.c
+++ b/drivers/mci/omap_hsmmc.c
@@ -316,13 +316,16 @@ static int mmc_read_data(struct omap_hsmmc *hsmmc, char *buf, unsigned int size)
 		do {
 			mmc_stat = readl(&mmc_base->stat);
 			if (is_timeout(start, SECOND)) {
-				dev_dbg(hsmmc->dev, "timedout waiting for status!\n");
+				dev_err(hsmmc->dev, "timedout waiting for status!\n");
 				return -ETIMEDOUT;
 			}
 		} while (mmc_stat == 0);
 
-		if ((mmc_stat & ERRI_MASK) != 0)
-			return 1;
+		if ((mmc_stat & ERRI_MASK) != 0) {
+			dev_err(hsmmc->dev, "Error while reading data. status: 0x%08x\n",
+				mmc_stat);
+			return -EIO;
+		}
 
 		if (mmc_stat & BRR_MASK) {
 			unsigned int k;
@@ -373,8 +376,11 @@ static int mmc_write_data(struct omap_hsmmc *hsmmc, const char *buf, unsigned in
 			}
 		} while (mmc_stat == 0);
 
-		if ((mmc_stat & ERRI_MASK) != 0)
-			return 1;
+		if ((mmc_stat & ERRI_MASK) != 0) {
+			dev_err(hsmmc->dev, "Error while reading data. status: 0x%08x\n",
+				mmc_stat);
+			return -EIO;
+		}
 
 		if (mmc_stat & BWR_MASK) {
 			unsigned int k;
-- 
2.19.1


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[PATCH 05/23] mci: omap: use IS_ENABLED() rather than #ifdef

[Sascha Hauer]

While touching it propagate the errors from read/write functions instead
of silently ignoring them.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/omap_hsmmc.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/mci/omap_hsmmc.c b/drivers/mci/omap_hsmmc.c
index 9e7ecabf85..d8e40aba20 100644
--- a/drivers/mci/omap_hsmmc.c
+++ b/drivers/mci/omap_hsmmc.c
@@ -352,7 +352,6 @@ static int mmc_read_data(struct omap_hsmmc *hsmmc, char *buf, unsigned int size)
 	return 0;
 }
 
-#ifdef CONFIG_MCI_WRITE
 static int mmc_write_data(struct omap_hsmmc *hsmmc, const char *buf, unsigned int size)
 {
 	struct hsmmc *mmc_base = hsmmc->base;
@@ -406,7 +405,6 @@ static int mmc_write_data(struct omap_hsmmc *hsmmc, const char *buf, unsigned in
 	}
 	return 0;
 }
-#endif
 
 static int mmc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
 		struct mci_data *data)
@@ -517,13 +515,18 @@ static int mmc_send_cmd(struct mci_host *mci, struct mci_cmd *cmd,
 		}
 	}
 
-	if (data && (data->flags & MMC_DATA_READ))
-		mmc_read_data(hsmmc, data->dest, data->blocksize * data->blocks);
-#ifdef CONFIG_MCI_WRITE
-	else if (data && (data->flags & MMC_DATA_WRITE))
-		mmc_write_data(hsmmc, data->src, data->blocksize * data->blocks);
-#endif
-	return 0;
+	if (!data)
+		return 0;
+
+	if (data->flags & MMC_DATA_READ)
+		return mmc_read_data(hsmmc, data->dest,
+				     data->blocksize * data->blocks);
+
+	if (IS_ENABLED(CONFIG_MCI_WRITE))
+		return mmc_write_data(hsmmc, data->src,
+				      data->blocksize * data->blocks);
+
+	return -ENOSYS;
 }
 
 static void mmc_set_ios(struct mci_host *mci, struct mci_ios *ios)
-- 
2.19.1


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[PATCH 06/23] mtd: nand: omap: Use dev_dbg when a struct device * is available

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 323a9c7532..8e29bae831 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -162,7 +162,7 @@ static void gpmc_nand_wp(struct gpmc_nand_info *oinfo, int mode)
 {
 	unsigned long config = readl(oinfo->gpmc_base + GPMC_CFG);
 
-	debug("%s: mode=%x\n", __func__, mode);
+	dev_dbg(oinfo->pdev, "%s: mode=%x\n", __func__, mode);
 
 	if (mode)
 		config &= ~(NAND_WP_BIT);	/* WP is ON */
@@ -425,7 +425,7 @@ static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	struct nand_chip *nand = (struct nand_chip *)(mtd->priv);
 	struct gpmc_nand_info *oinfo = (struct gpmc_nand_info *)(nand->priv);
 
-	debug("%s\n", __func__);
+	dev_dbg(oinfo->pdev, "%s\n", __func__);
 
 	switch (oinfo->ecc_mode) {
 	case OMAP_ECC_HAMMING_CODE_HW_ROMCODE:
-- 
2.19.1


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[PATCH 07/23] mtd: nand: omap: Fix hamming correct return values

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 8e29bae831..4ec4b93595 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -391,14 +391,13 @@ static int omap_correct_hamming(struct mtd_info *mtd, uint8_t *dat,
 			byte = (parity_bits >> 3) & 0x1FF;
 			/* Flip the bit to correct */
 			dat[byte] ^= (0x1 << bit);
+			return 1;
 		} else if (hm == 1) {
-			printf("Ecc is wrong\n");
 			/* ECC itself is corrupted */
-			return 2;
+			return -EBADMSG;
 		} else {
-			printf("bad compare! failed\n");
 			/* detected 2 bit error */
-			return -1;
+			return -EBADMSG;
 		}
 	}
 
-- 
2.19.1


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[PATCH 08/23] mtd: nand: omap: Disable subpage reads in hardware ecc mode

[Sascha Hauer]

Once the driver has started in software ECC mode the NAND core will set
the NAND_SUBPAGE_READ flag. We have to clear it explicitly when we
change to another mode afterwards.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 4ec4b93595..9b92f179b1 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -736,6 +736,7 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
 		nand->ecc.read_oob = NULL;
 		nand->ecc.write_oob = NULL;
 		nand->ecc.mode = NAND_ECC_HW;
+		nand->options &= ~NAND_SUBPAGE_READ;
 	}
 
 	switch (mode) {
-- 
2.19.1


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[PATCH 09/23] mtd: nand: omap: remove unused function argument

[Sascha Hauer]

__omap_calculate_ecc doesn't use the provided buffer argument, so remove
it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 9b92f179b1..91f5682e9e 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -228,8 +228,8 @@ static unsigned int gen_true_ecc(u8 *ecc_buf)
 	    ((ecc_buf[2] & 0x0F) << 8);
 }
 
-static int __omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
-			      uint8_t *ecc_code, int sblock)
+static int __omap_calculate_ecc(struct mtd_info *mtd, uint8_t *ecc_code,
+				int sblock)
 {
 	struct nand_chip *nand = (struct nand_chip *)(mtd->priv);
 	struct gpmc_nand_info *oinfo = (struct gpmc_nand_info *)(nand->priv);
@@ -288,7 +288,7 @@ static int __omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 static int omap_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat,
 			      uint8_t *ecc_code)
 {
-	return __omap_calculate_ecc(mtd, dat, ecc_code, 0);
+	return __omap_calculate_ecc(mtd, ecc_code, 0);
 }
 
 static int omap_correct_bch(struct mtd_info *mtd, uint8_t *dat,
@@ -436,7 +436,7 @@ static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 		 * but before it has read the oob data. Do it again,
 		 * this time with oob data.
 		 */
-		__omap_calculate_ecc(mtd, dat, calc_ecc, 0);
+		__omap_calculate_ecc(mtd, calc_ecc, 0);
 		return omap_correct_bch(mtd, dat, read_ecc, calc_ecc);
 	default:
 		return -EINVAL;
@@ -691,7 +691,7 @@ static int omap_gpmc_read_page_bch_rom_mode(struct mtd_info *mtd,
 	for (i = 0; i < chip->ecc.total; i++)
 		ecc_code[i] = chip->oob_poi[eccpos[i]];
 
-	__omap_calculate_ecc(mtd, buf, ecc_calc, 1);
+	__omap_calculate_ecc(mtd, ecc_calc, 1);
 
 	p = buf;
 
-- 
2.19.1


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[PATCH 10/23] mtd: nand: omap: fix bch8_hw_romcode ecc layout

[Sascha Hauer]

The ecc layout we provide to the nand core is broken since
00f119a293. Before this commit ecc bytes/size were per page
and now they are per subpage. The offset for the first ecc
byte was calculated as oob_end - num_ecc_bytes which must
now become oob_end - num_ecc_bytes * ecc_steps.

Fixes: 00f119a293 ("mtd: omap gpmc: fix ecc bytes/size")

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 91f5682e9e..d64ae41e7a 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -763,10 +763,14 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
 		oinfo->nand.ecc.size     = 512;
 		oinfo->nand.ecc.strength = BCH8_MAX_ERROR;
 		omap_oobinfo.oobfree->offset = offset;
+		oinfo->nand.ecc.steps = minfo->writesize / oinfo->nand.ecc.size;
+		oinfo->nand.ecc.total = oinfo->nand.ecc.steps * oinfo->nand.ecc.bytes;
+
 		omap_oobinfo.oobfree->length = minfo->oobsize -
 					offset - omap_oobinfo.eccbytes;
-		offset = minfo->oobsize - oinfo->nand.ecc.bytes;
-		for (i = 0; i < oinfo->nand.ecc.bytes; i++)
+		offset = minfo->oobsize - oinfo->nand.ecc.total;
+
+		for (i = 0; i < oinfo->nand.ecc.total; i++)
 			omap_oobinfo.eccpos[i] = i + offset;
 		break;
 	case OMAP_ECC_BCH8_CODE_HW_ROMCODE:
-- 
2.19.1


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[PATCH 11/23] mtd: nand: omap: set eccbytes correctly

[Sascha Hauer]

The total number of ecc bytes per page must be provided to the
nand core. This patch fixes this for bch8_hw and bch8_hw_romcode.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index d64ae41e7a..58ba95cb48 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -765,6 +765,7 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
 		omap_oobinfo.oobfree->offset = offset;
 		oinfo->nand.ecc.steps = minfo->writesize / oinfo->nand.ecc.size;
 		oinfo->nand.ecc.total = oinfo->nand.ecc.steps * oinfo->nand.ecc.bytes;
+		omap_oobinfo.eccbytes = oinfo->nand.ecc.total;
 
 		omap_oobinfo.oobfree->length = minfo->oobsize -
 					offset - omap_oobinfo.eccbytes;
@@ -779,6 +780,9 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
 		oinfo->nand.ecc.strength = BCH8_MAX_ERROR;
 		nand->ecc.read_page = omap_gpmc_read_page_bch_rom_mode;
 		omap_oobinfo.oobfree->length = 0;
+		oinfo->nand.ecc.steps = minfo->writesize / oinfo->nand.ecc.size;
+		oinfo->nand.ecc.total = oinfo->nand.ecc.steps * oinfo->nand.ecc.bytes;
+		omap_oobinfo.eccbytes = oinfo->nand.ecc.total;
 		j = 0;
 		for (i = 2; i < 58; i++)
 			omap_oobinfo.eccpos[j++] = i;
-- 
2.19.1


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[PATCH 12/23] mtd: nand: omap: unbreak BCH8 support

[Sascha Hauer]

We now tell the NAND layer that we have subpages with 512 bytes each.
This means the calculate_ecc / correct hooks are also called for each
subpage which means we cannot iterate over subpages in the calculate_ecc
callback.

Implement this correctly by removing the loop over subpages in the
calculate_ecc callback and by implementing a read_page callback.

With this the bch8_hw and bch8_hw_romcode were tested on AM335x, OMAP4
and AM3517. Number of bitflips is correctly reported as tested with the
nand_bitflip tool.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mtd/nand/nand_omap_gpmc.c | 113 ++++++++++++++++++------------
 1 file changed, 67 insertions(+), 46 deletions(-)

diff --git a/drivers/mtd/nand/nand_omap_gpmc.c b/drivers/mtd/nand/nand_omap_gpmc.c
index 58ba95cb48..8d82f637c0 100644
--- a/drivers/mtd/nand/nand_omap_gpmc.c
+++ b/drivers/mtd/nand/nand_omap_gpmc.c
@@ -236,39 +236,36 @@ static int __omap_calculate_ecc(struct mtd_info *mtd, uint8_t *ecc_code,
 	unsigned int reg;
 	unsigned int val1 = 0x0, val2 = 0x0;
 	unsigned int val3 = 0x0, val4 = 0x0;
-	int i;
 	int ecc_size = 8;
 
 	switch (oinfo->ecc_mode) {
 	case OMAP_ECC_BCH8_CODE_HW:
 	case OMAP_ECC_BCH8_CODE_HW_ROMCODE:
-		for (i = 0; i < 4; i++) {
-			/*
-			 * Reading HW ECC_BCH_Results
-			 * 0x240-0x24C, 0x250-0x25C, 0x260-0x26C, 0x270-0x27C
-			 */
-			reg =  GPMC_ECC_BCH_RESULT_0 + (0x10 * (i + sblock));
-			val1 = readl(oinfo->gpmc_base + reg);
-			val2 = readl(oinfo->gpmc_base + reg + 4);
-			if (ecc_size == 8) {
-				val3 = readl(oinfo->gpmc_base  +reg + 8);
-				val4 = readl(oinfo->gpmc_base + reg + 12);
-
-				*ecc_code++ = (val4 & 0xFF);
-				*ecc_code++ = ((val3 >> 24) & 0xFF);
-				*ecc_code++ = ((val3 >> 16) & 0xFF);
-				*ecc_code++ = ((val3 >> 8) & 0xFF);
-				*ecc_code++ = (val3 & 0xFF);
-				*ecc_code++ = ((val2 >> 24) & 0xFF);
-			}
-			*ecc_code++ = ((val2 >> 16) & 0xFF);
-			*ecc_code++ = ((val2 >> 8) & 0xFF);
-			*ecc_code++ = (val2 & 0xFF);
-			*ecc_code++ = ((val1 >> 24) & 0xFF);
-			*ecc_code++ = ((val1 >> 16) & 0xFF);
-			*ecc_code++ = ((val1 >> 8) & 0xFF);
-			*ecc_code++ = (val1 & 0xFF);
+		/*
+		 * Reading HW ECC_BCH_Results
+		 * 0x240-0x24C, 0x250-0x25C, 0x260-0x26C, 0x270-0x27C
+		 */
+		reg =  GPMC_ECC_BCH_RESULT_0 + (0x10 * sblock);
+		val1 = readl(oinfo->gpmc_base + reg);
+		val2 = readl(oinfo->gpmc_base + reg + 4);
+		if (ecc_size == 8) {
+			val3 = readl(oinfo->gpmc_base  +reg + 8);
+			val4 = readl(oinfo->gpmc_base + reg + 12);
+
+			*ecc_code++ = (val4 & 0xFF);
+			*ecc_code++ = ((val3 >> 24) & 0xFF);
+			*ecc_code++ = ((val3 >> 16) & 0xFF);
+			*ecc_code++ = ((val3 >> 8) & 0xFF);
+			*ecc_code++ = (val3 & 0xFF);
+			*ecc_code++ = ((val2 >> 24) & 0xFF);
 		}
+		*ecc_code++ = ((val2 >> 16) & 0xFF);
+		*ecc_code++ = ((val2 >> 8) & 0xFF);
+		*ecc_code++ = (val2 & 0xFF);
+		*ecc_code++ = ((val1 >> 24) & 0xFF);
+		*ecc_code++ = ((val1 >> 16) & 0xFF);
+		*ecc_code++ = ((val1 >> 8) & 0xFF);
+		*ecc_code++ = (val1 & 0xFF);
 		break;
 	case OMAP_ECC_HAMMING_CODE_HW_ROMCODE:
 		/* read ecc result */
@@ -302,7 +299,6 @@ static int omap_correct_bch(struct mtd_info *mtd, uint8_t *dat,
 	int bch_max_err;
 	int bitflip_count = 0;
 	bool eccflag = 0;
-
 	int eccsize = oinfo->nand.ecc.bytes;
 
 	switch (oinfo->ecc_mode) {
@@ -424,23 +420,10 @@ static int omap_correct_data(struct mtd_info *mtd, uint8_t *dat,
 	struct nand_chip *nand = (struct nand_chip *)(mtd->priv);
 	struct gpmc_nand_info *oinfo = (struct gpmc_nand_info *)(nand->priv);
 
-	dev_dbg(oinfo->pdev, "%s\n", __func__);
-
-	switch (oinfo->ecc_mode) {
-	case OMAP_ECC_HAMMING_CODE_HW_ROMCODE:
-		return omap_correct_hamming(mtd, dat, read_ecc, calc_ecc);
-	case OMAP_ECC_BCH8_CODE_HW:
-	case OMAP_ECC_BCH8_CODE_HW_ROMCODE:
-		/*
-		 * The nand layer already called omap_calculate_ecc,
-		 * but before it has read the oob data. Do it again,
-		 * this time with oob data.
-		 */
-		__omap_calculate_ecc(mtd, calc_ecc, 0);
-		return omap_correct_bch(mtd, dat, read_ecc, calc_ecc);
-	default:
+	if (oinfo->ecc_mode != OMAP_ECC_HAMMING_CODE_HW_ROMCODE)
 		return -EINVAL;
-	}
+
+	return omap_correct_hamming(mtd, dat, read_ecc, calc_ecc);
 
 	return 0;
 }
@@ -691,11 +674,10 @@ static int omap_gpmc_read_page_bch_rom_mode(struct mtd_info *mtd,
 	for (i = 0; i < chip->ecc.total; i++)
 		ecc_code[i] = chip->oob_poi[eccpos[i]];
 
-	__omap_calculate_ecc(mtd, ecc_calc, 1);
-
 	p = buf;
 
 	for (i = 0, j = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize, j++) {
+		__omap_calculate_ecc(mtd, &ecc_calc[i - j], j);
 		stat = omap_correct_bch(mtd, p, &ecc_code[i], &ecc_calc[i - j]);
 		if (stat < 0) {
 			mtd->ecc_stats.failed++;
@@ -708,6 +690,44 @@ static int omap_gpmc_read_page_bch_rom_mode(struct mtd_info *mtd,
 	return max_bitflips;
 }
 
+static int gpmc_read_page_hwecc(struct mtd_info *mtd,
+				struct nand_chip *chip, uint8_t *buf,
+				int oob_required, int page)
+{
+	int i, eccsize = chip->ecc.size;
+	int eccbytes = chip->ecc.bytes;
+	int eccsteps = chip->ecc.steps;
+	uint8_t *p = buf;
+	uint8_t *ecc_calc = chip->buffers->ecccalc;
+	uint8_t *ecc_code = chip->buffers->ecccode;
+	uint32_t *eccpos = chip->ecc.layout->eccpos;
+	unsigned int max_bitflips = 0;
+
+	chip->ecc.hwctl(mtd, NAND_ECC_READ);
+	chip->read_buf(mtd, p, mtd->writesize);
+	chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+	for (i = 0; i < chip->ecc.total; i++)
+		ecc_code[i] = chip->oob_poi[eccpos[i]];
+
+	eccsteps = chip->ecc.steps;
+	p = buf;
+
+	for (i = 0 ; eccsteps; eccsteps--, i++, p += eccsize) {
+		int stat;
+
+		__omap_calculate_ecc(mtd, &ecc_calc[i * eccbytes], i);
+		stat = omap_correct_bch(mtd, p, &ecc_code[i * eccbytes], &ecc_calc[i * eccbytes]);
+		if (stat < 0) {
+			mtd->ecc_stats.failed++;
+		} else {
+			mtd->ecc_stats.corrected += stat;
+			max_bitflips = max_t(unsigned int, max_bitflips, stat);
+		}
+	}
+	return max_bitflips;
+}
+
 static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
 		enum gpmc_ecc_mode mode)
 {
@@ -762,6 +782,7 @@ static int omap_gpmc_eccmode(struct gpmc_nand_info *oinfo,
 		oinfo->nand.ecc.bytes    = 13;
 		oinfo->nand.ecc.size     = 512;
 		oinfo->nand.ecc.strength = BCH8_MAX_ERROR;
+		nand->ecc.read_page = gpmc_read_page_hwecc;
 		omap_oobinfo.oobfree->offset = offset;
 		oinfo->nand.ecc.steps = minfo->writesize / oinfo->nand.ecc.size;
 		oinfo->nand.ecc.total = oinfo->nand.ecc.steps * oinfo->nand.ecc.bytes;
-- 
2.19.1


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[PATCH 13/23] ARM: omap: Add missing include

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/omap3_generic.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 5327bad1aa..02aa65d08b 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -43,6 +43,7 @@
 #include <mach/wdt.h>
 #include <mach/sys_info.h>
 #include <mach/syslib.h>
+#include <mach/omap3-generic.h>
 
 /**
  * @brief Reset the CPU
-- 
2.19.1


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[PATCH 14/23] ARM: omap: dmtimer: Turn into a driver

[Sascha Hauer]

Turn OMAP dmtimer into a driver and move to drivers/clocksource.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/Kconfig                    |  5 +-
 arch/arm/mach-omap/Makefile                   |  1 -
 arch/arm/mach-omap/am33xx_generic.c           |  5 +-
 drivers/clocksource/Kconfig                   |  3 ++
 drivers/clocksource/Makefile                  |  1 +
 .../clocksource/timer-ti-dm.c                 | 47 ++++++++++++++-----
 6 files changed, 44 insertions(+), 18 deletions(-)
 rename arch/arm/mach-omap/dmtimer.c => drivers/clocksource/timer-ti-dm.c (72%)

diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index c451cf0d47..5ab01439f0 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -43,7 +43,7 @@ config ARCH_AM33XX
 	select CPU_V7
 	select GENERIC_GPIO
 	select OFTREE
-	select OMAP_CLOCK_SOURCE_DMTIMER
+	select CLOCKSOURCE_TI_DM
 	select ARM_USE_COMPRESSED_DTB
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform
@@ -52,9 +52,6 @@ config ARCH_AM33XX
 config OMAP_CLOCK_SOURCE_S32K
 	bool
 
-config OMAP_CLOCK_SOURCE_DMTIMER
-	bool
-
 config OMAP_GPMC
 	prompt "Support for GPMC configuration"
 	bool
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index a84e94ed7d..4ce8e10587 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -18,7 +18,6 @@
 obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
 pbl-$(CONFIG_ARCH_OMAP) += syslib.o
 obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
-obj-$(CONFIG_OMAP_CLOCK_SOURCE_DMTIMER) += dmtimer.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index 513746248e..c446431537 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -256,7 +256,10 @@ int am33xx_init(void)
 
 int am33xx_devices_init(void)
 {
-	return am33xx_gpio_init();
+	am33xx_gpio_init();
+	add_generic_device("omap-dmtimer", 0, NULL, AM33XX_DMTIMER2_BASE, 0x400,
+			   IORESOURCE_MEM, NULL);
+	return 0;
 }
 
 /* UART Defines */
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 337a7a2e13..2228d44bde 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -88,4 +88,7 @@ config CLOCKSOURCE_DW_APB_TIMER
 	help
 	  Enables the support for the dw_apb timer.
 
+config CLOCKSOURCE_TI_DM
+	bool
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index ab78f0700d..3b154cbc2a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_CLOCKSOURCE_ARMV8_TIMER) += armv8-timer.o
 obj-$(CONFIG_CLOCKSOURCE_ARM_GLOBAL_TIMER) += arm_global_timer.o
 obj-$(CONFIG_CLOCKSOURCE_IMX_GPT) += timer-imx-gpt.o
 obj-$(CONFIG_CLOCKSOURCE_DW_APB_TIMER) += dw_apb_timer.o
+obj-$(CONFIG_CLOCKSOURCE_TI_DM) += timer-ti-dm.o
\ No newline at end of file
diff --git a/arch/arm/mach-omap/dmtimer.c b/drivers/clocksource/timer-ti-dm.c
similarity index 72%
rename from arch/arm/mach-omap/dmtimer.c
rename to drivers/clocksource/timer-ti-dm.c
index e223b8cc8f..635b860cf9 100644
--- a/arch/arm/mach-omap/dmtimer.c
+++ b/drivers/clocksource/timer-ti-dm.c
@@ -27,6 +27,7 @@
  *
  */
 
+#include <common.h>
 #include <clock.h>
 #include <init.h>
 #include <io.h>
@@ -55,7 +56,7 @@
 #define TSICR			0x54
 #define TCAR2			0x58
 
-static void *base = (void *)AM33XX_DMTIMER2_BASE;
+static void *base;
 
 /**
  * @brief Provide a simple counter read
@@ -73,17 +74,20 @@ static struct clocksource dmtimer_cs = {
 	.shift	= 10,
 };
 
-/**
- * @brief Initialize the Clock
- *
- * Enable dmtimer.
- *
- * @return result of @ref init_clock
- */
-static int dmtimer_init(void)
+static int omap_dmtimer_probe(struct device_d *dev)
 {
+	struct resource *iores;
 	u64 clk_speed;
 
+	/* one timer is enough */
+	if (base)
+		return 0;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+	base = IOMEM(iores->start);
+
 	clk_speed = am33xx_get_osc_clock();
 	clk_speed *= 1000;
 	dmtimer_cs.mult = clocksource_hz2mult(clk_speed, dmtimer_cs.shift);
@@ -91,8 +95,27 @@ static int dmtimer_init(void)
 	/* Enable counter */
 	writel(0x3, base + TCLR);
 
-	return init_clock(&dmtimer_cs);
+	init_clock(&dmtimer_cs);
+
+	return 0;
 }
 
-/* Run me at boot time */
-core_initcall(dmtimer_init);
+static __maybe_unused struct of_device_id omap_dmtimer_dt_ids[] = {
+	{
+		.compatible = "ti,am335x-timer",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d omap_dmtimer_driver = {
+	.name = "omap-dmtimer",
+	.probe = omap_dmtimer_probe,
+	.of_compatible = DRV_OF_COMPAT(omap_dmtimer_dt_ids),
+};
+
+static int omap_dmtimer_init(void)
+{
+	return platform_driver_register(&omap_dmtimer_driver);
+}
+postcore_initcall(omap_dmtimer_init);
-- 
2.19.1


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[PATCH 15/23] ARM: omap: 32ktimer: Turn into a driver

[Sascha Hauer]

Turn OMAP 32KHz timer into a driver and move to drivers/clocksource.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/Kconfig                    |  8 +---
 arch/arm/mach-omap/Makefile                   |  1 -
 arch/arm/mach-omap/omap3_generic.c            |  5 ++-
 arch/arm/mach-omap/omap4_generic.c            |  5 ++-
 drivers/clocksource/Kconfig                   |  3 ++
 drivers/clocksource/Makefile                  |  3 +-
 .../clocksource/timer-ti-32k.c                | 39 ++++++++++++++-----
 7 files changed, 45 insertions(+), 19 deletions(-)
 rename arch/arm/mach-omap/s32k_clksource.c => drivers/clocksource/timer-ti-32k.c (73%)

diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 5ab01439f0..34d37dcd7e 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -26,7 +26,7 @@ config ARCH_OMAP3
 	bool
 	select CPU_V7
 	select GENERIC_GPIO
-	select OMAP_CLOCK_SOURCE_S32K
+	select CLOCKSOURCE_TI_32K
 	help
 	  Say Y here if you are using Texas Instrument's OMAP343x based platform
 
@@ -34,7 +34,7 @@ config ARCH_OMAP4
 	bool
 	select CPU_V7
 	select GENERIC_GPIO
-	select OMAP_CLOCK_SOURCE_S32K
+	select CLOCKSOURCE_TI_32K
 	help
 	  Say Y here if you are using Texas Instrument's OMAP4 based platform
 
@@ -48,10 +48,6 @@ config ARCH_AM33XX
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform
 
-# Blind enable all possible clocks.. think twice before you do this.
-config OMAP_CLOCK_SOURCE_S32K
-	bool
-
 config OMAP_GPMC
 	prompt "Support for GPMC configuration"
 	bool
diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 4ce8e10587..e6132342e1 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -17,7 +17,6 @@
 #
 obj-$(CONFIG_ARCH_OMAP) += syslib.o omap_devices.o omap_generic.o omap_fb.o
 pbl-$(CONFIG_ARCH_OMAP) += syslib.o
-obj-$(CONFIG_OMAP_CLOCK_SOURCE_S32K) += s32k_clksource.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 02aa65d08b..3f91441d2e 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -533,6 +533,9 @@ static int omap3_gpio_init(void)
 
 int omap3_devices_init(void)
 {
-	return omap3_gpio_init();
+	omap3_gpio_init();
+	add_generic_device("omap-32ktimer", 0, NULL, OMAP3_32KTIMER_BASE, 0x400,
+			   IORESOURCE_MEM, NULL);
+	return 0;
 }
 #endif
diff --git a/arch/arm/mach-omap/omap4_generic.c b/arch/arm/mach-omap/omap4_generic.c
index a3f370df8f..c7b6e513a2 100644
--- a/arch/arm/mach-omap/omap4_generic.c
+++ b/arch/arm/mach-omap/omap4_generic.c
@@ -684,5 +684,8 @@ static int omap4_gpio_init(void)
 
 int omap4_devices_init(void)
 {
-	return omap4_gpio_init();
+	omap4_gpio_init();
+	add_generic_device("omap-32ktimer", 0, NULL, OMAP44XX_32KTIMER_BASE, 0x400,
+			   IORESOURCE_MEM, NULL);
+	return 0;
 }
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 2228d44bde..7b04663d2e 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -91,4 +91,7 @@ config CLOCKSOURCE_DW_APB_TIMER
 config CLOCKSOURCE_TI_DM
 	bool
 
+config CLOCKSOURCE_TI_32K
+	bool
+
 endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 3b154cbc2a..f8ff83d60a 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_CLOCKSOURCE_ARMV8_TIMER) += armv8-timer.o
 obj-$(CONFIG_CLOCKSOURCE_ARM_GLOBAL_TIMER) += arm_global_timer.o
 obj-$(CONFIG_CLOCKSOURCE_IMX_GPT) += timer-imx-gpt.o
 obj-$(CONFIG_CLOCKSOURCE_DW_APB_TIMER) += dw_apb_timer.o
-obj-$(CONFIG_CLOCKSOURCE_TI_DM) += timer-ti-dm.o
\ No newline at end of file
+obj-$(CONFIG_CLOCKSOURCE_TI_DM) += timer-ti-dm.o
+obj-$(CONFIG_CLOCKSOURCE_TI_32K) += timer-ti-32k.o
\ No newline at end of file
diff --git a/arch/arm/mach-omap/s32k_clksource.c b/drivers/clocksource/timer-ti-32k.c
similarity index 73%
rename from arch/arm/mach-omap/s32k_clksource.c
rename to drivers/clocksource/timer-ti-32k.c
index 7def8b1807..f93ab5bcff 100644
--- a/arch/arm/mach-omap/s32k_clksource.c
+++ b/drivers/clocksource/timer-ti-32k.c
@@ -67,19 +67,40 @@ static struct clocksource s32k_cs = {
  *
  * @return result of @ref init_clock
  */
-static int s32k_clocksource_init(void)
+static int omap_32ktimer_probe(struct device_d *dev)
 {
-	if (IS_ENABLED(CONFIG_ARCH_OMAP3))
-		timerbase = (void *)OMAP3_32KTIMER_BASE;
-	else if (IS_ENABLED(CONFIG_ARCH_OMAP4))
-		timerbase = (void *)OMAP44XX_32KTIMER_BASE;
-	else
-		BUG();
+	struct resource *iores;
+
+	/* one timer is enough */
+	if (timerbase)
+		return 0;
+
+	iores = dev_request_mem_resource(dev, 0);
+	if (IS_ERR(iores))
+		return PTR_ERR(iores);
+	timerbase = IOMEM(iores->start);
 
 	s32k_cs.mult = clocksource_hz2mult(S32K_FREQUENCY, s32k_cs.shift);
 
 	return init_clock(&s32k_cs);
 }
 
-/* Run me at boot time */
-core_initcall(s32k_clocksource_init);
+static __maybe_unused struct of_device_id omap_32ktimer_dt_ids[] = {
+	{
+		.compatible = "ti,omap-counter32k",
+	}, {
+		/* sentinel */
+	}
+};
+
+static struct driver_d omap_32ktimer_driver = {
+	.name = "omap-32ktimer",
+	.probe = omap_32ktimer_probe,
+	.of_compatible = DRV_OF_COMPAT(omap_32ktimer_dt_ids),
+};
+
+static int omap_32ktimer_init(void)
+{
+	return platform_driver_register(&omap_32ktimer_driver);
+}
+postcore_initcall(omap_32ktimer_init);
-- 
2.19.1


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[PATCH 16/23] ARM: omap: Add AM35XX support

[Sascha Hauer]

Not much to be done here. The AM35xx is very similar to OMAP3.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/Kconfig                    |  6 ++++++
 arch/arm/mach-omap/include/mach/omap3-clock.h |  2 ++
 arch/arm/mach-omap/include/mach/sys_info.h    |  2 ++
 arch/arm/mach-omap/omap3_clock.c              | 14 +++++++++-----
 arch/arm/mach-omap/omap3_generic.c            |  3 +++
 5 files changed, 22 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 34d37dcd7e..5537f5101a 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -48,6 +48,12 @@ config ARCH_AM33XX
 	help
 	  Say Y here if you are using Texas Instrument's AM33xx based platform
 
+config ARCH_AM35XX
+	bool
+	select ARCH_OMAP3
+	help
+	  Say Y here if you are using Texas Instrument's AM35XX based platform
+
 config OMAP_GPMC
 	prompt "Support for GPMC configuration"
 	bool
diff --git a/arch/arm/mach-omap/include/mach/omap3-clock.h b/arch/arm/mach-omap/include/mach/omap3-clock.h
index 7c52da754f..849964ab3e 100644
--- a/arch/arm/mach-omap/include/mach/omap3-clock.h
+++ b/arch/arm/mach-omap/include/mach/omap3-clock.h
@@ -64,6 +64,8 @@
 #define CM_CLKSEL_CAM		0X0f40
 #define CM_FCLKEN_PER		0X1000
 #define CM_ICLKEN_PER		0X1010
+#define CM_IDLEST_PER		0X1020
+#define CM_AUTOIDLE_PER		0X1030
 #define CM_CLKSEL_PER		0X1040
 #define CM_CLKSEL1_EMU		0X1140
 #define CM_FCLKEN_USBH		0x1400
diff --git a/arch/arm/mach-omap/include/mach/sys_info.h b/arch/arm/mach-omap/include/mach/sys_info.h
index e36f49df8a..57bfb3c680 100644
--- a/arch/arm/mach-omap/include/mach/sys_info.h
+++ b/arch/arm/mach-omap/include/mach/sys_info.h
@@ -43,6 +43,7 @@
 #define CPU_3350	0x3350
 #define CPU_3430	0x3430
 #define CPU_3630	0x3630
+#define CPU_AM35XX	0x3500
 
 /**
  * Define CPU revisions
@@ -84,6 +85,7 @@
 #define OMAP_HAWKEYE_34XX	0xB7AE /* OMAP34xx */
 #define OMAP_HAWKEYE_36XX	0xB891 /* OMAP36xx */
 #define OMAP_HAWKEYE_335X	0xB944 /* AM335x */
+#define OMAP_HAWKEYE_AM35XX	0xb868 /* AM35xx */
 
 /** These are implemented by the System specific code in omapX-generic.c */
 u32 get_cpu_type(void);
diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 6700f56f39..0159574f30 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -617,11 +617,12 @@ void prcm_init(void)
 	sr32(OMAP3_CM_REG(CLKEN_PLL_MPU), 0, 3, PLL_LOW_POWER_BYPASS);
 	wait_on_value((0x1 << 0), 0, OMAP3_CM_REG(IDLEST_PLL_MPU), LDELAY);
 
-	if (cpu_type == CPU_3430) {
+	if (cpu_type == CPU_3430 || cpu_type == CPU_AM35XX) {
 		init_core_dpll_34x(cpu_rev, clk_index);
 		init_per_dpll_34x(cpu_rev, clk_index);
 		init_mpu_dpll_34x(cpu_rev, clk_index);
-		init_iva_dpll_34x(cpu_rev, clk_index);
+		if (cpu_type != CPU_AM35XX)
+			init_iva_dpll_34x(cpu_rev, clk_index);
 	}
 	else if (cpu_type == CPU_3630) {
 		init_core_dpll_36x(cpu_rev, clk_index);
@@ -676,7 +677,12 @@ static void per_clocks_enable(void)
 #define ICK_CAM_ON	0x00000001
 #define FCK_PER_ON	0x0003ffff
 #define ICK_PER_ON	0x0003ffff
-	sr32(OMAP3_CM_REG(FCLKEN_IVA2), 0, 32, FCK_IVA2_ON);
+
+	if (get_cpu_type() != CPU_AM35XX) {
+		sr32(OMAP3_CM_REG(FCLKEN_IVA2), 0, 32, FCK_IVA2_ON);
+		sr32(OMAP3_CM_REG(FCLKEN_CAM), 0, 32, FCK_CAM_ON);
+		sr32(OMAP3_CM_REG(ICLKEN_CAM), 0, 32, ICK_CAM_ON);
+	}
 	sr32(OMAP3_CM_REG(FCLKEN1_CORE), 0, 32, FCK_CORE1_ON);
 	sr32(OMAP3_CM_REG(ICLKEN1_CORE), 0, 32, ICK_CORE1_ON);
 	sr32(OMAP3_CM_REG(ICLKEN2_CORE), 0, 32, ICK_CORE2_ON);
@@ -684,8 +690,6 @@ static void per_clocks_enable(void)
 	sr32(OMAP3_CM_REG(ICLKEN_WKUP), 0, 32, ICK_WKUP_ON);
 	sr32(OMAP3_CM_REG(FCLKEN_DSS), 0, 32, FCK_DSS_ON);
 	sr32(OMAP3_CM_REG(ICLKEN_DSS), 0, 32, ICK_DSS_ON);
-	sr32(OMAP3_CM_REG(FCLKEN_CAM), 0, 32, FCK_CAM_ON);
-	sr32(OMAP3_CM_REG(ICLKEN_CAM), 0, 32, ICK_CAM_ON);
 	sr32(OMAP3_CM_REG(FCLKEN_PER), 0, 32, FCK_PER_ON);
 	sr32(OMAP3_CM_REG(ICLKEN_PER), 0, 32, ICK_PER_ON);
 
diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 3f91441d2e..348a00cdff 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -78,6 +78,9 @@ u32 get_cpu_type(void)
 	if (hawkeye == OMAP_HAWKEYE_34XX)
 		return CPU_3430;
 
+	if (hawkeye == OMAP_HAWKEYE_AM35XX)
+		return CPU_AM35XX;
+
 	if (hawkeye == OMAP_HAWKEYE_36XX)
 		return CPU_3630;
 
-- 
2.19.1


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[PATCH 17/23] ARM: omap: enable am33xx_uart_soft_reset for AM35xx

[Sascha Hauer]

am33xx_uart_soft_reset() can be used on AM35xx aswell, so move it
to a more generic place where it can be added to am35xx compilation.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/Makefile                   |  3 +-
 arch/arm/mach-omap/am33xx_generic.c           | 27 ----------------
 arch/arm/mach-omap/am3xxx.c                   | 32 +++++++++++++++++++
 .../mach-omap/include/mach/am3xxx-silicon.h   |  6 ++++
 4 files changed, 40 insertions(+), 28 deletions(-)
 create mode 100644 arch/arm/mach-omap/am3xxx.c
 create mode 100644 arch/arm/mach-omap/include/mach/am3xxx-silicon.h

diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index e6132342e1..901cc90373 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -21,7 +21,8 @@ obj-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
-obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o
+obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o
+obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o
 obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
diff --git a/arch/arm/mach-omap/am33xx_generic.c b/arch/arm/mach-omap/am33xx_generic.c
index c446431537..fe3c4a8b17 100644
--- a/arch/arm/mach-omap/am33xx_generic.c
+++ b/arch/arm/mach-omap/am33xx_generic.c
@@ -262,33 +262,6 @@ int am33xx_devices_init(void)
 	return 0;
 }
 
-/* UART Defines */
-#define UART_SYSCFG_OFFSET	0x54
-#define UART_SYSSTS_OFFSET	0x58
-
-#define UART_CLK_RUNNING_MASK	0x1
-#define UART_RESET		(0x1 << 1)
-#define UART_SMART_IDLE_EN	(0x1 << 0x3)
-
-void am33xx_uart_soft_reset(void __iomem *uart_base)
-{
-	int reg;
-
-	reg = readl(uart_base + UART_SYSCFG_OFFSET);
-	reg |= UART_RESET;
-	writel(reg, (uart_base + UART_SYSCFG_OFFSET));
-
-	while ((readl(uart_base + UART_SYSSTS_OFFSET) &
-		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
-		;
-
-	/* Disable smart idle */
-	reg = readl((uart_base + UART_SYSCFG_OFFSET));
-	reg |= UART_SMART_IDLE_EN;
-	writel(reg, (uart_base + UART_SYSCFG_OFFSET));
-}
-
-
 #define VTP_CTRL_READY		(0x1 << 5)
 #define VTP_CTRL_ENABLE		(0x1 << 6)
 #define VTP_CTRL_START_EN	(0x1)
diff --git a/arch/arm/mach-omap/am3xxx.c b/arch/arm/mach-omap/am3xxx.c
new file mode 100644
index 0000000000..75965a8e0e
--- /dev/null
+++ b/arch/arm/mach-omap/am3xxx.c
@@ -0,0 +1,32 @@
+#include <common.h>
+#include <io.h>
+#include <mach/am3xxx-silicon.h>
+
+/* UART Defines */
+#define UART_SYSCFG_OFFSET	0x54
+#define UART_SYSSTS_OFFSET	0x58
+
+#define UART_CLK_RUNNING_MASK	0x1
+#define UART_RESET		(0x1 << 1)
+#define UART_SMART_IDLE_EN	(0x1 << 0x3)
+
+void am3xxx_uart_soft_reset(void __iomem *uart_base)
+{
+	int reg;
+
+	reg = readl(uart_base + UART_SYSCFG_OFFSET);
+	reg |= UART_RESET;
+	writel(reg, (uart_base + UART_SYSCFG_OFFSET));
+
+	while ((readl(uart_base + UART_SYSSTS_OFFSET) &
+		UART_CLK_RUNNING_MASK) != UART_CLK_RUNNING_MASK)
+		;
+
+	/* Disable smart idle */
+	reg = readl((uart_base + UART_SYSCFG_OFFSET));
+	reg |= UART_SMART_IDLE_EN;
+	writel(reg, (uart_base + UART_SYSCFG_OFFSET));
+}
+
+void am33xx_uart_soft_reset(void __iomem *uart_base)
+	__alias(am3xxx_uart_soft_reset);
\ No newline at end of file
diff --git a/arch/arm/mach-omap/include/mach/am3xxx-silicon.h b/arch/arm/mach-omap/include/mach/am3xxx-silicon.h
new file mode 100644
index 0000000000..c5f73ad457
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/am3xxx-silicon.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_AM33XX_H
+#define __ASM_ARCH_AM33XX_H
+
+void am3xxx_uart_soft_reset(void __iomem *uart_base);
+
+#endif /* __ASM_ARCH_AM33XX_H */
\ No newline at end of file
-- 
2.19.1


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[PATCH 18/23] ARM: omap3: Add support for reset reason detection

[Sascha Hauer]

From: Oleg Karfich <oleg.karfich@wago.com>

Due to the Errata i520, the reset code in the linux kernel aswell in barebox
triggers a cpu reset by setting the bit RST_DPLL3 in the PRM_RSTCTRL register.
This induces a global cold reset on the chip. So we will always detect a POR as
reset source when a reboot of the chip is triggerd. Other states like WDG, JTAG
were tested successfully.

Signed-off-by: Oleg Karfich <oleg.karfich@wago.com>
---
 arch/arm/mach-omap/omap3_generic.c | 49 ++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm/mach-omap/omap3_generic.c b/arch/arm/mach-omap/omap3_generic.c
index 348a00cdff..cff4a4fb11 100644
--- a/arch/arm/mach-omap/omap3_generic.c
+++ b/arch/arm/mach-omap/omap3_generic.c
@@ -44,6 +44,7 @@
 #include <mach/sys_info.h>
 #include <mach/syslib.h>
 #include <mach/omap3-generic.h>
+#include <reset_source.h>
 
 /**
  * @brief Reset the CPU
@@ -490,12 +491,60 @@ static int omap3_bootsource(void)
 	return 0;
 }
 
+#define OMAP3_PRM_RSTST_OFF 0x8
+#define OMAP3_REG_PRM_RSTST (OMAP3_PRM_REG(RSTCTRL) + OMAP3_PRM_RSTST_OFF)
+
+#define OMAP3_ICECRUSHER_RST	BIT(10)
+#define OMAP3_ICEPICK_RST	BIT(9)
+#define OMAP3_EXTERNAL_WARM_RST	BIT(6)
+#define OMAP3_SECURE_WD_RST	BIT(5)
+#define OMAP3_MPU_WD_RST	BIT(4)
+#define OMAP3_SECURITY_VIOL_RST	BIT(3)
+#define OMAP3_GLOBAL_SW_RST	BIT(1)
+#define OMAP3_GLOBAL_COLD_RST	BIT(0)
+
+static void omap3_detect_reset_reason(void)
+{
+	uint32_t val = 0;
+
+	val = readl(OMAP3_REG_PRM_RSTST);
+	/* clear OMAP3_PRM_RSTST - must be cleared by software */
+	writel(val, OMAP3_REG_PRM_RSTST);
+
+	switch (val) {
+	case OMAP3_ICECRUSHER_RST:
+	case OMAP3_ICEPICK_RST:
+		reset_source_set(RESET_JTAG);
+		break;
+	case OMAP3_EXTERNAL_WARM_RST:
+		reset_source_set(RESET_EXT);
+		break;
+	case OMAP3_SECURE_WD_RST:
+	case OMAP3_MPU_WD_RST:
+	case OMAP3_SECURITY_VIOL_RST:
+		reset_source_set(RESET_WDG);
+		break;
+	case OMAP3_GLOBAL_SW_RST:
+		reset_source_set(RESET_RST);
+		break;
+	case OMAP3_GLOBAL_COLD_RST:
+		reset_source_set(RESET_POR);
+		break;
+	default:
+		reset_source_set(RESET_UKWN);
+		break;
+	}
+}
+
 int omap3_init(void)
 {
 	omap_gpmc_base = (void *)OMAP3_GPMC_BASE;
 
 	restart_handler_register_fn(omap3_restart_soc);
 
+	if (IS_ENABLED(CONFIG_RESET_SOURCE))
+		omap3_detect_reset_reason();
+
 	return omap3_bootsource();
 }
 
-- 
2.19.1


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[PATCH 19/23] ARM: omap: Add AM3517 specific mux configuration

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/include/mach/omap3-mux.h | 49 ++++++++++++++++++++-
 1 file changed, 48 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap/include/mach/omap3-mux.h b/arch/arm/mach-omap/include/mach/omap3-mux.h
index d6fb9c393c..a679e25567 100644
--- a/arch/arm/mach-omap/include/mach/omap3-mux.h
+++ b/arch/arm/mach-omap/include/mach/omap3-mux.h
@@ -413,4 +413,51 @@
 #define CONTROL_PADCONF_SDRC_CKE0	0x0262
 #define CONTROL_PADCONF_SDRC_CKE1	0x0264
 
-#endif /* _ASM_ARCH_OMAP3_MUX_H_ */
+/* AM3517 specific mux configuration */
+#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
+/* CCDC */
+#define CONTROL_PADCONF_CCDC_PCLK	0x01E4
+#define CONTROL_PADCONF_CCDC_FIELD	0x01E6
+#define CONTROL_PADCONF_CCDC_HD		0x01E8
+#define CONTROL_PADCONF_CCDC_VD		0x01EA
+#define CONTROL_PADCONF_CCDC_WEN	0x01EC
+#define CONTROL_PADCONF_CCDC_DATA0	0x01EE
+#define CONTROL_PADCONF_CCDC_DATA1	0x01F0
+#define CONTROL_PADCONF_CCDC_DATA2	0x01F2
+#define CONTROL_PADCONF_CCDC_DATA3	0x01F4
+#define CONTROL_PADCONF_CCDC_DATA4	0x01F6
+#define CONTROL_PADCONF_CCDC_DATA5	0x01F8
+#define CONTROL_PADCONF_CCDC_DATA6	0x01FA
+#define CONTROL_PADCONF_CCDC_DATA7	0x01FC
+/* RMII */
+#define CONTROL_PADCONF_RMII_MDIO_DATA	0x01FE
+#define CONTROL_PADCONF_RMII_MDIO_CLK	0x0200
+#define CONTROL_PADCONF_RMII_RXD0	0x0202
+#define CONTROL_PADCONF_RMII_RXD1	0x0204
+#define CONTROL_PADCONF_RMII_CRS_DV	0x0206
+#define CONTROL_PADCONF_RMII_RXER	0x0208
+#define CONTROL_PADCONF_RMII_TXD0	0x020A
+#define CONTROL_PADCONF_RMII_TXD1	0x020C
+#define CONTROL_PADCONF_RMII_TXEN	0x020E
+#define CONTROL_PADCONF_RMII_50MHZ_CLK	0x0210
+#define CONTROL_PADCONF_USB0_DRVBUS	0x0212
+/* CAN */
+#define CONTROL_PADCONF_HECC1_TXD	0x0214
+#define CONTROL_PADCONF_HECC1_RXD	0x0216
+
+#define CONTROL_PADCONF_SYS_BOOT7	0x0218
+#define CONTROL_PADCONF_SDRC_DQS0N	0x021A
+#define CONTROL_PADCONF_SDRC_DQS1N	0x021C
+#define CONTROL_PADCONF_SDRC_DQS2N	0x021E
+#define CONTROL_PADCONF_SDRC_DQS3N	0x0220
+#define CONTROL_PADCONF_STRBEN_DLY0	0x0222
+#define CONTROL_PADCONF_STRBEN_DLY1	0x0224
+#define CONTROL_PADCONF_SYS_BOOT8	0x0226
+
+/* AM/DM37xx specific */
+#define CONTROL_PADCONF_GPIO127		0x0A54
+#define CONTROL_PADCONF_GPIO126		0x0A56
+#define CONTROL_PADCONF_GPIO128		0x0A58
+#define CONTROL_PADCONF_GPIO129		0x0A5A
+
+#endif
-- 
2.19.1


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[PATCH 20/23] ARM: omap: Add emif4 support for AM3517

[Sascha Hauer]

This adds support for the SDRAM controller found on AM3517.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-omap/Makefile             |   2 +-
 arch/arm/mach-omap/am35xx_emif4.c       |  85 +++++++++++++++++++
 arch/arm/mach-omap/include/mach/emif4.h | 105 ++++++++++++++++++++++++
 3 files changed, 191 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-omap/am35xx_emif4.c
 create mode 100644 arch/arm/mach-omap/include/mach/emif4.h

diff --git a/arch/arm/mach-omap/Makefile b/arch/arm/mach-omap/Makefile
index 901cc90373..36b2aa090e 100644
--- a/arch/arm/mach-omap/Makefile
+++ b/arch/arm/mach-omap/Makefile
@@ -22,7 +22,7 @@ pbl-$(CONFIG_ARCH_OMAP3) += omap3_generic.o auxcr.o
 obj-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 pbl-$(CONFIG_ARCH_OMAP4) += omap4_generic.o omap4_clock.o
 obj-pbl-$(CONFIG_ARCH_AM33XX) += am33xx_generic.o am33xx_clock.o am33xx_mux.o am3xxx.o
-obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o
+obj-pbl-$(CONFIG_ARCH_AM35XX) += am3xxx.o am35xx_emif4.o
 obj-$(CONFIG_ARCH_AM33XX) += am33xx_scrm.o
 obj-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
 pbl-$(CONFIG_ARCH_OMAP3) += omap3_clock.o
diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c
new file mode 100644
index 0000000000..38fc0f02d2
--- /dev/null
+++ b/arch/arm/mach-omap/am35xx_emif4.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Author :
+ *     Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Based on mem.c and sdrc.c
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ */
+
+#include <common.h>
+#include <io.h>
+#include <mach/emif4.h>
+#include <mach/omap3-silicon.h>
+
+/*
+ * do_pac200_emif4_init -
+ *  - Init the emif4 module for DDR access
+ *  - Early init routines, called from flash or SRAM.
+ */
+void am35xx_emif4_init(void)
+{
+	unsigned int regval;
+	struct emif4 *emif4_base = IOMEM(OMAP3_SDRC_BASE);
+
+	/* Set the DDR PHY parameters in PHY ctrl registers */
+	regval = (EMIF4_DDR1_READ_LAT | EMIF4_DDR1_PWRDN_DIS |
+		EMIF4_DDR1_EXT_STRB_DIS);
+	writel(regval, &emif4_base->ddr_phyctrl1);
+	writel(regval, &emif4_base->ddr_phyctrl1_shdw);
+	writel(0, &emif4_base->ddr_phyctrl2);
+
+	/* Reset the DDR PHY and wait till completed */
+	regval = readl(&emif4_base->sdram_iodft_tlgc);
+	regval |= (1 << 10);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+
+	/* Wait till that bit clears*/
+	while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1);
+
+	/* Re-verify the DDR PHY status*/
+	while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0);
+
+	regval |= (1 << 0);
+	writel(regval, &emif4_base->sdram_iodft_tlgc);
+
+	/* Set SDR timing registers */
+	regval = (EMIF4_TIM1_T_WTR | EMIF4_TIM1_T_RRD |
+		EMIF4_TIM1_T_RC | EMIF4_TIM1_T_RAS |
+		EMIF4_TIM1_T_WR | EMIF4_TIM1_T_RCD |
+		EMIF4_TIM1_T_RP);
+	writel(regval, &emif4_base->sdram_time1);
+	writel(regval, &emif4_base->sdram_time1_shdw);
+
+	regval = (EMIF4_TIM2_T_CKE | EMIF4_TIM2_T_RTP |
+		EMIF4_TIM2_T_XSRD | EMIF4_TIM2_T_XSNR |
+		EMIF4_TIM2_T_ODT | EMIF4_TIM2_T_XP);
+	writel(regval, &emif4_base->sdram_time2);
+	writel(regval, &emif4_base->sdram_time2_shdw);
+
+	regval = (EMIF4_TIM3_T_RAS_MAX | EMIF4_TIM3_T_RFC);
+	writel(regval, &emif4_base->sdram_time3);
+	writel(regval, &emif4_base->sdram_time3_shdw);
+
+	/* Set the PWR control register */
+	regval = (EMIF4_PWR_PM_TIM | EMIF4_PWR_LP_MODE |
+		EMIF4_PWR_DPD_DIS | EMIF4_PWR_IDLE_MODE);
+	writel(regval, &emif4_base->sdram_pwr_mgmt);
+	writel(regval, &emif4_base->sdram_pwr_mgmt_shdw);
+
+	/* Set the DDR refresh rate control register */
+	regval = (EMIF4_REFRESH_RATE | EMIF4_INITREF_DIS);
+	writel(regval, &emif4_base->sdram_refresh_ctrl);
+	writel(regval, &emif4_base->sdram_refresh_ctrl_shdw);
+
+	/* set the SDRAM configuration register */
+	regval = (EMIF4_CFG_PGSIZE | EMIF4_CFG_EBANK |
+		EMIF4_CFG_IBANK | EMIF4_CFG_ROWSIZE |
+		EMIF4_CFG_CL | EMIF4_CFG_NARROW_MD |
+		EMIF4_CFG_SDR_DRV | EMIF4_CFG_DDR_DIS_DLL |
+		EMIF4_CFG_DDR2_DDQS | EMIF4_CFG_DDR_TERM |
+		EMIF4_CFG_IBANK_POS | EMIF4_CFG_SDRAM_TYP);
+	writel(regval, &emif4_base->sdram_config);
+}
diff --git a/arch/arm/mach-omap/include/mach/emif4.h b/arch/arm/mach-omap/include/mach/emif4.h
new file mode 100644
index 0000000000..1f9c2938a1
--- /dev/null
+++ b/arch/arm/mach-omap/include/mach/emif4.h
@@ -0,0 +1,105 @@
+/*
+ * Auther:
+ *       Vaibhav Hiremath <hvaibhav@ti.com>
+ *
+ * Copyright (C) 2010
+ * Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _EMIF_H_
+#define _EMIF_H_
+
+/*
+ * Configuration values
+ */
+#define EMIF4_TIM1_T_RP		(0x3 << 25)
+#define EMIF4_TIM1_T_RCD	(0x3 << 21)
+#define EMIF4_TIM1_T_WR		(0x3 << 17)
+#define EMIF4_TIM1_T_RAS	(0x7 << 12) /* 8->7 */
+#define EMIF4_TIM1_T_RC		(0xA << 6)
+#define EMIF4_TIM1_T_RRD	(0x2 << 3)
+#define EMIF4_TIM1_T_WTR	(0x2)
+
+#define EMIF4_TIM2_T_XP		(0x2 << 28)
+#define EMIF4_TIM2_T_ODT	(0x0 << 25) /* 2? */
+#define EMIF4_TIM2_T_XSNR	(0x1C << 16)
+#define EMIF4_TIM2_T_XSRD	(0xC8 << 6)
+#define EMIF4_TIM2_T_RTP	(0x1 << 3)
+#define EMIF4_TIM2_T_CKE	(0x2)
+
+#define EMIF4_TIM3_T_RFC	(0x15 << 4) /* 25->15 */
+#define EMIF4_TIM3_T_RAS_MAX	(0xf)	    /* 7->f */
+
+#define EMIF4_PWR_IDLE_MODE	(0x2 << 30)
+#define EMIF4_PWR_DPD_DIS	(0x0 << 10)
+#define EMIF4_PWR_DPD_EN	(0x1 << 10)
+#define EMIF4_PWR_LP_MODE	(0x0 << 8)
+#define EMIF4_PWR_PM_TIM	(0x0)
+
+#define EMIF4_INITREF_DIS	(0x0 << 31)
+#define EMIF4_REFRESH_RATE	(0x257) /* 50f->257 */
+
+#define EMIF4_CFG_SDRAM_TYP	(0x2 << 29)
+#define EMIF4_CFG_IBANK_POS	(0x0 << 27)
+#define EMIF4_CFG_DDR_TERM	(0x3 << 24) /* --> 0x3 */
+#define EMIF4_CFG_DDR2_DDQS	(0x1 << 23)
+#define EMIF4_CFG_DDR_DIS_DLL	(0x0 << 20)
+#define EMIF4_CFG_SDR_DRV	(0x0 << 18)
+#define EMIF4_CFG_NARROW_MD	(0x0 << 14)
+#define EMIF4_CFG_CL		(0x5 << 10)
+#define EMIF4_CFG_ROWSIZE	(0x0 << 7) /* --> 0x4: a0..a12 */
+#define EMIF4_CFG_IBANK		(0x3 << 4)
+#define EMIF4_CFG_EBANK		(0x0 << 3)
+#define EMIF4_CFG_PGSIZE	(0x2)      /* 10 columns */
+
+/*
+ * EMIF4 PHY Control 1 register configuration
+ */
+#define EMIF4_DDR1_EXT_STRB_EN	(0x1 << 7)
+#define EMIF4_DDR1_EXT_STRB_DIS	(0x0 << 7)
+#define EMIF4_DDR1_PWRDN_DIS	(0x0 << 6)
+#define EMIF4_DDR1_PWRDN_EN	(0x1 << 6)
+#define EMIF4_DDR1_READ_LAT	(0x6 << 0)
+
+struct emif4 {
+	unsigned int emif_mod_id_rev;
+	unsigned int sdram_sts;
+	unsigned int sdram_config;
+	unsigned int res1;
+	unsigned int sdram_refresh_ctrl;
+	unsigned int sdram_refresh_ctrl_shdw;
+	unsigned int sdram_time1;
+	unsigned int sdram_time1_shdw;
+	unsigned int sdram_time2;
+	unsigned int sdram_time2_shdw;
+	unsigned int sdram_time3;
+	unsigned int sdram_time3_shdw;
+	unsigned char res2[8];
+	unsigned int sdram_pwr_mgmt;
+	unsigned int sdram_pwr_mgmt_shdw;
+	unsigned char res3[32];
+	unsigned int sdram_iodft_tlgc;
+	unsigned char res4[128];
+	unsigned int ddr_phyctrl1;
+	unsigned int ddr_phyctrl1_shdw;
+	unsigned int ddr_phyctrl2;
+};
+
+void am35xx_emif4_init(void);
+
+#endif /* endif _EMIF_H_ */
-- 
2.19.1


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[PATCH 21/23] ARM: omap: AM3517: Change default clock rate for AM3517

[Sascha Hauer]

From: Heinrich Toews <heinrich.toews@wago.com>

This is an adoption of U-Boot commit:

| commit c8e5ba8034ad2a961782a092498f6ea71237c63f
| Author: Schuyler Patton <spatton@ti.com>
| Date:   Wed Feb 1 07:31:44 2012 +0000
|
|    AM3517: Changed default clock rate for AM3517
|
|    Changed #define MPU_M_13_ES2 from 0x1F4 to 0x258, this allows
|    the AM3517 to boot up at 600MHz instead of 500 MHz
|
|    Signed-off-by: Schuyler Patton <spatton@ti.com>
|    CC: Tom Rini <tom.rini@gmail.com>
|    CC: Simon Schwarz <simonschwarzcor@gmail.com>
|    CC: Stefano Babic <sbabic@denx.de>

Signed-off-by: Heinrich Toews <heinrich.toews@wago.com>
---
 arch/arm/mach-omap/omap3_clock.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap/omap3_clock.c b/arch/arm/mach-omap/omap3_clock.c
index 0159574f30..03b866c28e 100644
--- a/arch/arm/mach-omap/omap3_clock.c
+++ b/arch/arm/mach-omap/omap3_clock.c
@@ -290,7 +290,7 @@ static struct dpll_param mpu_dpll_param_34x_es1[] = {
 
 static struct dpll_param mpu_dpll_param_34x_es2[] = {
 	{.m = 0x0FA, .n = 0x05, .fsel = 0x07, .m2 = 0x01, }, /* 12   MHz */
-	{.m = 0x1F4, .n = 0x0C, .fsel = 0x03, .m2 = 0x01, }, /* 13   MHz */
+	{.m = 0x258, .n = 0x0C, .fsel = 0x03, .m2 = 0x01, }, /* 13   MHz */
 	{.m = 0x271, .n = 0x17, .fsel = 0x03, .m2 = 0x01, }, /* 19.2 MHz */
 	{.m = 0x0FA, .n = 0x0C, .fsel = 0x07, .m2 = 0x01, }, /* 26   MHz */
 	{.m = 0x271, .n = 0x2F, .fsel = 0x03, .m2 = 0x01, }, /* 38.4 MHz */
-- 
2.19.1


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[PATCH 22/23] ARM: omap: Add board support for WAGO pfc200 platform

[Sascha Hauer]

This adds support for the AM3517 based WAGO pfc100/200 SPS.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/Makefile                      |   1 +
 arch/arm/boards/wago-pfc-am35xx/Makefile      |   6 +
 arch/arm/boards/wago-pfc-am35xx/board-mlo.c   |  73 +++
 arch/arm/boards/wago-pfc-am35xx/board.c       |  39 ++
 arch/arm/boards/wago-pfc-am35xx/lowlevel.c    | 231 +++++++++
 .../arm/configs/am35xx_pfc200_xload_defconfig |  40 ++
 arch/arm/dts/Makefile                         |   1 +
 arch/arm/dts/am35xx-pfc-750_820x.dts          | 487 ++++++++++++++++++
 arch/arm/dts/am3xxx-pfc-nandparts.dtsi        |  63 +++
 arch/arm/mach-omap/Kconfig                    |   9 +
 images/Makefile                               |   1 +
 images/Makefile.am35xx                        |  24 +
 12 files changed, 975 insertions(+)
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/Makefile
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/board-mlo.c
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/board.c
 create mode 100644 arch/arm/boards/wago-pfc-am35xx/lowlevel.c
 create mode 100644 arch/arm/configs/am35xx_pfc200_xload_defconfig
 create mode 100644 arch/arm/dts/am35xx-pfc-750_820x.dts
 create mode 100644 arch/arm/dts/am3xxx-pfc-nandparts.dtsi
 create mode 100644 images/Makefile.am35xx

diff --git a/arch/arm/boards/Makefile b/arch/arm/boards/Makefile
index 3bf176b14d..b546274244 100644
--- a/arch/arm/boards/Makefile
+++ b/arch/arm/boards/Makefile
@@ -157,3 +157,4 @@ obj-$(CONFIG_MACH_ZII_RDU1)			+= zii-imx51-rdu1/
 obj-$(CONFIG_MACH_ZII_RDU2)			+= zii-imx6q-rdu2/
 obj-$(CONFIG_MACH_ZII_VF610_DEV)		+= zii-vf610-dev/
 obj-$(CONFIG_MACH_ZII_IMX7D_RPU2)		+= zii-imx7d-rpu2/
+obj-$(CONFIG_MACH_WAGO_PFC_AM35XX)		+= wago-pfc-am35xx/
diff --git a/arch/arm/boards/wago-pfc-am35xx/Makefile b/arch/arm/boards/wago-pfc-am35xx/Makefile
new file mode 100644
index 0000000000..7bd3009f31
--- /dev/null
+++ b/arch/arm/boards/wago-pfc-am35xx/Makefile
@@ -0,0 +1,6 @@
+lwl-y += lowlevel.o
+ifdef CONFIG_OMAP_BUILD_IFT
+obj-y += board-mlo.o
+else
+obj-y += board.o
+endif
diff --git a/arch/arm/boards/wago-pfc-am35xx/board-mlo.c b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c
new file mode 100644
index 0000000000..49fcd0b30b
--- /dev/null
+++ b/arch/arm/boards/wago-pfc-am35xx/board-mlo.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2015 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com>
+ * Author: Heinrich Toews <heinrich.toews@wago.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <io.h>
+#include <linux/sizes.h>
+#include <mach/omap3-silicon.h>
+#include <mach/gpmc.h>
+#include <mach/gpmc_nand.h>
+#include <errno.h>
+#include <mach/omap3-devices.h>
+#include <mach/generic.h>
+
+/* map first four erase blocks */
+static struct omap_barebox_part pfc200_mlo_part = {
+	/* start of boot0..boot3 (stage2 bootcode),
+	 * we have 4x partitions
+	 */
+	.nand_offset = 4 * SZ_128K,
+	.nand_size = 4 * SZ_128K,
+};
+
+/**
+ * @brief Initialize the serial port to be used as console.
+ *
+ * @return result of device registration
+ */
+static int pfc200_init_console(void)
+{
+	barebox_set_model("Wago PFC200 MLO Stage #1");
+	barebox_set_hostname("pfc200-mlo");
+
+	omap3_add_uart3();
+
+	return 0;
+}
+console_initcall(pfc200_init_console);
+
+static int pfc200_mem_init(void)
+{
+	omap_add_ram0(SZ_256M);
+
+	return 0;
+}
+mem_initcall(pfc200_mem_init);
+
+static struct gpmc_nand_platform_data nand_plat = {
+	.cs = 0,
+	.device_width = 8,
+	.ecc_mode = OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
+	.nand_cfg = &omap3_nand_cfg,
+};
+
+static int pfc200_init_devices(void)
+{
+#ifdef CONFIG_OMAP_GPMC
+	/*
+	 * WP is made high and WAIT1 active Low
+	 */
+	gpmc_generic_init(0x10);
+#endif
+	omap_add_gpmc_nand_device(&nand_plat);
+	omap_set_barebox_part(&pfc200_mlo_part);
+
+	omap3_add_mmc1(NULL);
+
+	return 0;
+}
+device_initcall(pfc200_init_devices);
diff --git a/arch/arm/boards/wago-pfc-am35xx/board.c b/arch/arm/boards/wago-pfc-am35xx/board.c
new file mode 100644
index 0000000000..2bad40912d
--- /dev/null
+++ b/arch/arm/boards/wago-pfc-am35xx/board.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2014 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com>
+ * Author: Heinrich Toews <heinrich.toews@wago.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <driver.h>
+#include <gpio.h>
+#include <linux/sizes.h>
+#include <linux/err.h>
+#include <asm/memory.h>
+#include <mach/generic.h>
+
+static int pfc200_mem_init(void)
+{
+	if (!of_machine_is_compatible("ti,pfc200"))
+		return 0;
+
+	arm_add_mem_device("ram0", 0x80000000, SZ_256M);
+	return 0;
+}
+mem_initcall(pfc200_mem_init);
+
+#define GPIO_KSZ886x_RESET	136
+
+static int pfc200_devices_init(void)
+{
+	if (!of_machine_is_compatible("ti,pfc200"))
+		return 0;
+
+	gpio_direction_output(GPIO_KSZ886x_RESET, 1);
+
+	omap_set_bootmmc_devname("mmc0");
+
+	return 0;
+}
+coredevice_initcall(pfc200_devices_init);
diff --git a/arch/arm/boards/wago-pfc-am35xx/lowlevel.c b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
new file mode 100644
index 0000000000..7da8fd0331
--- /dev/null
+++ b/arch/arm/boards/wago-pfc-am35xx/lowlevel.c
@@ -0,0 +1,231 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2014 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com>
+ * Author: Heinrich Toews <heinrich.toews@wago.com>
+ */
+
+#include <common.h>
+#include <init.h>
+#include <linux/sizes.h>
+#include <io.h>
+#include <linux/string.h>
+#include <debug_ll.h>
+#include <asm/barebox-arm-head.h>
+#include <asm/barebox-arm.h>
+#include <mach/generic.h>
+#include <mach/sdrc.h>
+#include <mach/sys_info.h>
+#include <mach/syslib.h>
+#include <mach/wdt.h>
+#include <mach/omap3-mux.h>
+#include <mach/omap3-silicon.h>
+#include <mach/omap3-generic.h>
+#include <mach/omap3-clock.h>
+#include <mach/control.h>
+#include <asm/common.h>
+#include <asm-generic/memory_layout.h>
+
+#include <mach/emif4.h>
+
+static void mux_config(void)
+{
+	/* SDRC */
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0));
+	MUX_VAL(CP(SDRC_CKE0),		(M0));
+	MUX_VAL(CP(SDRC_CKE1),		(M0));
+	/* sdrc_strben_dly0 */
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0));
+	 /*sdrc_strben_dly1*/
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0));
+
+	/* GPMC */
+	MUX_VAL(CP(GPMC_A1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A3),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A4),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A5),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A6),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A7),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A8),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A9),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS1),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS2),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS3),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS4),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS5),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NCS6),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NCS7),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_CLK),		(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_NWP),		(IEN  | PTD | DIS | M0));
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4)); /*GPIO_64*/
+							 /* - ETH_nRESET*/
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN  | PTU | EN  | M0));
+
+	/* MMC */
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0));
+
+	/* MMC GPIOs */
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTD | DIS | M4)); /* McBSP2_FSX    -> SD-MMC1-CD (GPIO_116) */
+	MUX_VAL(CP(MCBSP2_CLKX),	(IDIS | PTU | DIS | M4)); /* McBSP2_CLKX   -> SD-MMC1-EN (GPIO_117) */
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTD | DIS | M4)); /* McBSP2_DR     -> SD-MMC1-WP (GPIO_118) */
+	MUX_VAL(CP(MMC2_DAT7),		(IDIS | PTU | DIS | M4)); /* MMC2_DAT7     -> SD-MMC1-RW (GPIO_139) */
+
+	/* UART1 */
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)); /* M4, GPIO_149 */
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0));
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0));
+
+	MUX_VAL(CP(MCSPI1_CS2),		(IDIS | PTU | DIS | M4)); /* MCSPI1_CS2    -> SEL_RS232/485_GPIO176 (GPIO_176) */
+
+	/* UART2 */
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0));
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0));
+
+	/* WATCHDOG */
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M4)); /* Trigger Event <1,6s */
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IDIS | PTD | DIS | M4)); /* Enable */
+
+	/* I2C1: PMIC */
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0));
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTU | EN  | M4)); /* SYS_nIRQ      -> PMIC_nINT1      (GPIO_0) */
+
+	/* I2C2: RTC, EEPROM */
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)); /* RTC_EEPROM_SCL2 */
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)); /* RTC_EEPROM_SDA2 */
+	MUX_VAL(CP(HDQ_SIO),		(IDIS | PTD | DIS  | M4)); /* HDQ_SIO       -> WD_nWP   GPIO_170 */
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M4));  /* SYS_CLKREQ    -> RTC_nINT (GPIO_1) */
+
+	/* GPIO_BANK3: operating mode switch and reset all pushbutton */
+	MUX_VAL(CP(DSS_DATA20),  (IEN  | PTU | EN  | M4));  //    DSS_DATA20    -> BAS_RUN      /* GPIO 90 */ (sync, changed)
+	MUX_VAL(CP(DSS_DATA21),  (IEN  | PTU | EN  | M4));  //    DSS_DATA21    -> BAS_STOP     /* GPIO 91 */ (sync, changed)
+	MUX_VAL(CP(DSS_DATA22),  (IEN  | PTU | EN  | M4));  //    DSS_DATA22    -> BAS_RESET    /* GPIO 92 */ (sync, changed)
+	MUX_VAL(CP(DSS_DATA23),  (IEN  | PTU | EN  | M4));  //    DSS_DATA23    -> RESET_ALL    /* GPIO 93 */ (sync, changed)
+	MUX_VAL(CP(CCDC_PCLK) , (IEN  | PTU | EN  | M4));   //    CCDC_PCLK     -> System Reset /* GPIO 94 */ (sync, changed) Reserved for later use!
+
+	/* *********** ADDED FOR JTAG DEBUGGING ************* */
+	MUX_VAL(CP(SYS_NRESWARM),     	(IDIS | PTU | DIS | M4));
+}
+
+static noinline void pfc200_board_init(void)
+{
+	int in_sdram = omap3_running_in_sdram();
+	u32 r0;
+
+	if (IS_ENABLED(CONFIG_DEBUG_LL)) {
+		am33xx_uart_soft_reset(IOMEM(OMAP3_UART3_BASE));
+		omap_uart_lowlevel_init(IOMEM(OMAP3_UART3_BASE));
+		putc_ll('>');
+	}
+
+	omap3_core_init();
+
+	mux_config();
+
+#define CONTROL_DEVCONF3   0x48002584
+	/* activate DDR2 CPU Termination */
+	r0 = readl(CONTROL_DEVCONF3);
+	writel(r0 | 0x2, CONTROL_DEVCONF3);
+
+	/* Dont reconfigure SDRAM while running in SDRAM */
+	if (!in_sdram)
+		am35xx_emif4_init();
+
+	barebox_arm_entry(0x80000000, SZ_256M, NULL);
+}
+
+ENTRY_FUNCTION(start_am35xx_pfc_750_820x_sram, bootinfo, r1, r2)
+{
+	omap3_save_bootinfo((void *)bootinfo);
+
+	arm_cpu_lowlevel_init();
+
+	omap3_gp_romcode_call(OMAP3_GP_ROMCODE_API_L2_INVAL, 0);
+
+	relocate_to_current_adr();
+	setup_c();
+
+	pfc200_board_init();
+}
+
+extern char __dtb_am35xx_pfc_750_820x_start[];
+
+ENTRY_FUNCTION(start_am35xx_pfc_750_820x_sdram, r0, r1, r2)
+{
+	void *fdt = __dtb_am35xx_pfc_750_820x_start;
+
+	fdt += get_runtime_offset();
+
+	barebox_arm_entry(0x80000000, SZ_256M, fdt);
+}
diff --git a/arch/arm/configs/am35xx_pfc200_xload_defconfig b/arch/arm/configs/am35xx_pfc200_xload_defconfig
new file mode 100644
index 0000000000..da55382f05
--- /dev/null
+++ b/arch/arm/configs/am35xx_pfc200_xload_defconfig
@@ -0,0 +1,40 @@
+CONFIG_ARCH_OMAP=y
+CONFIG_OMAP_BUILD_IFT=y
+CONFIG_OMAP_MULTI_BOARDS=y
+CONFIG_MACH_WAGO_PFC_AM35XX=y
+CONFIG_THUMB2_BAREBOX=y
+# CONFIG_ARM_EXCEPTIONS is not set
+# CONFIG_MEMINFO is not set
+CONFIG_MMU=y
+# CONFIG_MMU_EARLY is not set
+CONFIG_STACK_SIZE=0xc00
+CONFIG_MALLOC_SIZE=0x0
+CONFIG_MALLOC_DUMMY=y
+CONFIG_RELOCATABLE=y
+CONFIG_PROMPT="X-load pfc200>"
+CONFIG_SHELL_NONE=y
+# CONFIG_ERRNO_MESSAGES is not set
+# CONFIG_TIMESTAMP is not set
+CONFIG_CONSOLE_SIMPLE=y
+CONFIG_DRIVER_SERIAL_NS16550=y
+CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
+# CONFIG_SPI is not set
+CONFIG_MTD=y
+# CONFIG_MTD_WRITE is not set
+# CONFIG_MTD_OOB_DEVICE is not set
+CONFIG_NAND=y
+# CONFIG_NAND_ECC_SOFT is not set
+# CONFIG_NAND_ECC_HW_SYNDROME is not set
+# CONFIG_NAND_ECC_HW_NONE is not set
+# CONFIG_NAND_INFO is not set
+# CONFIG_NAND_BBT is not set
+CONFIG_NAND_OMAP_GPMC=y
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_MMC_BOOT_PARTITIONS=y
+CONFIG_MCI_OMAP_HSMMC=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c08b35a101..cdbaf8189f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -122,5 +122,6 @@ pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
 pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
 
 pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
+pbl-dtb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += am35xx-pfc-750_820x.dtb.o
 
 clean-files := *.dtb *.dtb.S .*.dtc .*.pre .*.dts *.dtb.lzo
diff --git a/arch/arm/dts/am35xx-pfc-750_820x.dts b/arch/arm/dts/am35xx-pfc-750_820x.dts
new file mode 100644
index 0000000000..707778dfac
--- /dev/null
+++ b/arch/arm/dts/am35xx-pfc-750_820x.dts
@@ -0,0 +1,487 @@
+/*
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Copyright (C) 2014 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com>
+ * Author: Heinrich Toews <heinrich.toews@wago.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include <arm/am3517.dtsi>
+
+/ {
+	model = "Wago PFC200 (AM3505)";
+	compatible = "ti,pfc200", "ti,am3517", "ti,omap3";
+
+	chosen {
+		stdout-path = &uart3;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+
+	vmmc_fixed: vmmc {
+		compatible = "regulator-fixed";
+		regulator-name = "vmmc_fixed";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+	};
+
+	aliases {
+		serial3 = &uart3;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		gpio3 = &gpio4;
+		gpio4 = &gpio5;
+		gpio5 = &gpio6;
+		mmc0 = &mmc1;
+		mmc1 = &mmc2;
+		mmc2 = &mmc3;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&led_pins>;
+
+		u1-green@0 {
+			label = "u1-green";
+			gpios = <&gpio3 22 0>;
+			linux,default-trigger = "none";
+		};
+
+		u1-red@1 {
+			label = "u1-red";
+			gpios = <&gpio3 23 0>;
+			linux,default-trigger = "none";
+		};
+
+		u2-green@2 {
+			label = "u2-green";
+			gpios = <&gpio3 18 0>;
+			linux,default-trigger = "none";
+		};
+
+		u2-red@3 {
+			label = "u2-red";
+			gpios = <&gpio3 19 0>;
+			linux,default-trigger = "none";
+		};
+
+		u3-green@4 {
+			label = "u3-green";
+			gpios = <&gpio3 14 0>;
+			linux,default-trigger = "none";
+		};
+
+		u3-red@5 {
+			label = "u3-red";
+			gpios = <&gpio3 15 0>;
+			linux,default-trigger = "none";
+		};
+
+		u4-green@6 {
+			label = "u4-green";
+			gpios = <&gpio3 10 0>;
+			linux,default-trigger = "none";
+		};
+
+		u4-red@7 {
+			label = "u4-red";
+			gpios = <&gpio3 11 0>;
+			linux,default-trigger = "none";
+		};
+
+		dia-green@8 {
+			label = "dia-green";
+			gpios = <&gpio3 6 0>;
+			linux,default-trigger = "none";
+		};
+
+		dia-red@9 {
+			label = "dia-red";
+			gpios = <&gpio3 7 0>;
+			linux,default-trigger = "none";
+		};
+
+		bf-green@10 {
+			label = "bf-green";
+			gpios = <&gpio3 2 0>;
+			linux,default-trigger = "none";
+		};
+
+		bf-red@11 {
+			label = "bf-red";
+			gpios = <&gpio3 3 0>;
+			linux,default-trigger = "none";
+		};
+
+		sys-green@12 {
+			label = "sys-green";
+			gpios = <&gpio3 4 0>;
+			linux,default-trigger = "none";
+		};
+
+		sys-red@13 {
+			label = "sys-red";
+			gpios = <&gpio3 5 0>;
+			linux,default-trigger = "none";
+		};
+
+
+		run-green@14 {
+			label = "run-green";
+			gpios = <&gpio3 8 0>;
+			linux,default-trigger = "none";
+		};
+
+		run-red@15 {
+			label = "run-red";
+			gpios = <&gpio3 9 0>;
+			linux,default-trigger = "none";
+		};
+
+
+		io-green@16 {
+			label = "io-green";
+			gpios = <&gpio3 12 0>;
+			linux,default-trigger = "none";
+		};
+
+		io-red@17 {
+			label = "io-red";
+			gpios = <&gpio3 13 0>;
+			linux,default-trigger = "none";
+		};
+
+
+		ms-green@18 {
+			label = "ms-green";
+			gpios = <&gpio3 16 0>;
+			linux,default-trigger = "none";
+		};
+
+		ms-red@19 {
+			label = "ms-red";
+			gpios = <&gpio3 17 0>;
+			linux,default-trigger = "none";
+		};
+
+
+		ns-green@20 {
+			label = "ns-green";
+			gpios = <&gpio3 20 0>;
+			linux,default-trigger = "none";
+		};
+
+		ns-red@21 {
+			label = "ns-red";
+			gpios = <&gpio3 21 0>;
+			linux,default-trigger = "none";
+		};
+
+
+		can-green@22 {
+			label = "can-green";
+			gpios = <&gpio3 24 0>;
+			linux,default-trigger = "none";
+		};
+
+		can-red@23 {
+			label = "can-red";
+			gpios = <&gpio3 25 0>;
+			linux,default-trigger = "none";
+		};
+
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "disabled";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "disabled";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3_pins>;
+        status = "okay";
+};
+
+&davinci_emac {
+	pinctrl-names = "default";
+	pinctrl-0 = <&emac_pins>;
+        status = "okay";
+        phy-mode = "rmii";
+
+	fixed-link {
+		speed = <100>;
+		full-duplex;
+	};
+};
+
+&davinci_mdio {
+	status = "okay";
+	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+};
+
+&i2c1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	clock-frequency = <100000>;
+};
+
+&i2c2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c2_pins>;
+	clock-frequency = <400000>;
+};
+
+&i2c3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c3_pins>;
+	clock-frequency = <100000>;
+};
+
+&mmc1 {
+        status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	vmmc-supply = <&vmmc_fixed>;
+	bus-width = <4>;
+	cd-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; /* GPIO 116 */
+	cd-inverted;
+};
+
+&mmc2 {
+      status = "disabled";
+};
+
+&mmc3 {
+      status = "disabled";
+};
+
+&omap3_pmx_core {
+	pinctrl-names = "default";
+	pinctrl-0 = <&bas_pins>;
+
+	uart1_pins: pinmux_uart1_pins {
+		pinctrl-single,pins = <
+                        0x150 (PIN_INPUT | MUX_MODE0)		  /* uart1_cts.uart1_cts */
+                        0x14e (PIN_OUTPUT | MUX_MODE0)		  /* uart1_rts.uart1_rts */
+                        0x152 (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx   */
+                        0x14c (PIN_OUTPUT | MUX_MODE0)		  /* uart1_tx.uart1_tx   */
+		        0x1a2 (PIN_OUTPUT | MUX_MODE4)            /* mcspi1_cs2.gpio_176: sel_rs232/485_gpio176 */
+		>;
+	};
+
+	uart2_pins: pinmux_uart2_pins {
+		pinctrl-single,pins = <
+                        0x14a (WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
+                        0x148 (PIN_OUTPUT | MUX_MODE0)		/* uart2_tx.uart2_tx */
+		>;
+	};
+
+	uart3_pins: pinmux_uart3_pins {
+		pinctrl-single,pins = <
+			0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
+			0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
+		>;
+	};
+
+	i2c1_pins: pinmux_i2c1_pins {
+		pinctrl-single,pins = <
+			0x18a (PIN_INPUT_PULLUP | MUX_MODE0)   /* i2c1_scl.i2c1_scl */
+			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)   /* i2c1_sda.i2c1_sda */
+		>;
+	};
+
+	i2c2_pins: pinmux_i2c2_pins {
+		pinctrl-single,pins = <
+			0x18e (PIN_INPUT_PULLUP | MUX_MODE0)   /* i2c2_scl.i2c2_scl */
+			0x190 (PIN_INPUT_PULLUP | MUX_MODE0)   /* i2c2_sda.i2c2_sda */
+		        0x196 (PIN_OUTPUT | MUX_MODE4)  /* hdq_sio.gpio_170: wd_nwp */
+		>;
+	};
+
+	i2c3_pins: pinmux_i2c3_pins {
+		pinctrl-single,pins = <
+			0x192 (PIN_INPUT | MUX_MODE0)   /* i2c3_scl.i2c3_scl */
+			0x194 (PIN_INPUT | MUX_MODE0)   /* i2c3_sda.i2c3_sda */
+		>;
+	};
+
+	mmc1_pins: pinmux_mmc1_pins {
+		pinctrl-single,pins = <
+			0x114 (PIN_INPUT_PULLUP | MUX_MODE0)	/* sdmmc1_clk.sdmmc1_clk */
+			0x116 (PIN_INPUT | MUX_MODE0)	/* sdmmc1_cmd.sdmmc1_cmd */
+			0x118 (PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat0.sdmmc1_dat0 */
+			0x11a (PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat1.sdmmc1_dat1 */
+			0x11c (PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat2.sdmmc1_dat2 */
+			0x11e (PIN_INPUT | MUX_MODE0)	/* sdmmc1_dat3.sdmmc1_dat3 */
+		>;
+	};
+
+	emac_pins: pinmux_emac_pins {
+		pinctrl-single,pins = <
+		        0x1ce (PIN_INPUT | MUX_MODE0)           /* rmii_mdio_data.rmii_mdio_data */
+		        0x1d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* rmii_mdio_clk.rmii_mdio_clk   */
+		        0x1d2 (PIN_INPUT | MUX_MODE0)           /* rmii_rxd0.rmii_rxd0           */
+		        0x1d4 (PIN_INPUT | MUX_MODE0)           /* rmii_rxd1.rmii_rxd1           */
+		        0x1d6 (PIN_INPUT | MUX_MODE0)           /* rmii_crs_dv.rmii_crs_dv       */
+		        0x1d8 (PIN_INPUT | MUX_MODE0)           /* rmii_rxer.rmii_rxer           */
+		        0x1da (PIN_OUTPUT_PULLUP | MUX_MODE0)   /* rmii_txd0.rmii_txd0           */
+		        0x1dc (PIN_INPUT | MUX_MODE0)           /* rmii_txd1.rmii_txd1           */
+		        0x1de (PIN_INPUT | MUX_MODE0)           /* rmii_txen.rmii_txen           */
+		        0x1e0 (PIN_INPUT | MUX_MODE0)           /* rmii_50mhz_clk.rmii_50mhz_clk */
+		        0x134 (PIN_OUTPUT | MUX_MODE4)          /* mmc2_dat4.gpio_136: nrst_switch */
+		>;
+	};
+
+	led_pins: pinmux_led_pins {
+		pinctrl-single,pins = <
+		        0x0a4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_pclk.gpio_66: led_1_1_green */
+		        0x0a6 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_hsync.gpio_67: led_1_1_red */
+		        0x0a8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_vsync.gpio_68: led_1_2_green */
+		        0x0aa (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_acbias.gpio_69: led_1_2_red */
+
+		        0x0ac (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data0.gpio_70: led_2_1_green */
+		        0x0ae (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data1.gpio_71: led_2_1_red */
+		        0x0b0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data2.gpio_72: led_2_2_green */
+		        0x0b2 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data3.gpio_73: led_2_2_red */
+
+		        0x0b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data4.gpio_74: led_3_1_green */
+		        0x0b6 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data5.gpio_75: led_3_1_red */
+		        0x0b8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data6.gpio_76: led_3_2_green */
+		        0x0ba (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data7.gpio_77: led_3_2_red */
+
+		        0x0bc (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data8.gpio_78: led_4_1_green */
+		        0x0be (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data9.gpio_79: led_4_1_red */
+		        0x0c0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data10.gpio_80: led_4_2_green */
+		        0x0c2 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data11.gpio_81: led_4_2_red */
+
+		        0x0c4 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data12.gpio_82: led_5_1_green */
+		        0x0c6 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data13.gpio_83: led_5_1_red */
+		        0x0c8 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data14.gpio_84: led_5_2_green */
+		        0x0ca (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data15.gpio_85: led_5_2_red */
+
+		        0x0cc (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data16.gpio_86: led_6_1_green */
+		        0x0ce (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data17.gpio_87: led_6_1_red */
+		        0x0d0 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data18.gpio_88: led_6_2_green */
+		        0x0d2 (PIN_OUTPUT_PULLDOWN | MUX_MODE4)  /* dss_data19.gpio_89: led_6_2_red */
+		>;
+	};
+
+	bas_pins: pinmux_bas_pins {
+		pinctrl-single,pins = <
+			0x0d4 (PIN_INPUT_PULLUP | MUX_MODE4)	/* dss_data20.gpio_90: bas_run */
+			0x0d6 (PIN_INPUT_PULLUP | MUX_MODE4)	/* dss_data21.gpio_91: bas_stop */
+			0x0d8 (PIN_INPUT_PULLUP | MUX_MODE4)	/* dss_data22.gpio_92: bas_reset */
+			0x0da (PIN_INPUT_PULLUP | MUX_MODE4)	/* dss_data23.gpio_93: reset_all */
+		>;
+	};
+
+	gpmc_pins: pinmux_gpmc_pins {
+		pinctrl-single,pins = <
+			0x04a (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a1.gpmc_a1 */
+			0x04c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a2.gpmc_a2 */
+			0x04e (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a3.gpmc_a3 */
+			0x050 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a4.gpmc_a4 */
+			0x052 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a5.gpmc_a5 */
+			0x054 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a6.gpmc_a6 */
+			0x056 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a7.gpmc_a7 */
+			0x058 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a8.gpmc_a8 */
+			0x05a (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a9.gpmc_a9 */
+			0x05c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_a10.gpmc_a10 */
+
+			0x06c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d8.gpmc_d8 */
+			0x06e (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d9.gpmc_d9 */
+			0x070 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d10.gpmc_d10 */
+			0x072 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d11.gpmc_d11 */
+			0x074 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d12.gpmc_d12 */
+			0x076 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d13.gpmc_d13 */
+			0x078 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d14.gpmc_d14 */
+			0x07a (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_d15.gpmc_d15 */
+
+			0x07e (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_ncs0.gpmc_ncs0 */
+			0x080 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_ncs1.gpmc_ncs1 */
+			0x082 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_ncs2.gpmc_ncs2 */
+			0x08c (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_clk.gpmc_clk */
+
+			0x090 (PIN_OUTPUT | MUX_MODE0)	/* gpmc_nadv_ale.gpmc_nadv_ale */
+			0x092 (PIN_OUTPUT | MUX_MODE0)	/* gpmc_noe.gpmc_noe */
+			0x094 (PIN_OUTPUT | MUX_MODE0)	/* gpmc_nwe */
+
+			0x096 (PIN_OUTPUT_PULLUP | MUX_MODE0)	/* gpmc_nbe0_cle.gpmc_nbe0_cle */
+
+			0x098 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_nbe1.gpmc_nbe1 */
+			0x09a (PIN_INPUT | MUX_MODE0)	/* gpmc_nwp.gpmc_nwp */
+
+			0x09c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
+			0x09e (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait1.gpmc_wait1 */
+			0x0a0 (PIN_INPUT_PULLUP | MUX_MODE4)	/* gpmc_wait2.gpio_64 */
+			0x0a2 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait3.gpmc_wait3 */
+		>;
+	};
+};
+
+&gpmc {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&gpmc_pins>;
+	num-cs = <2>;
+	num-waitpins = <1>;
+	ranges = <
+		0 0 0x08000000 0x01000000	/* CS0: NAND */
+	>;
+
+	nand: nand@0,0 {
+		reg = <0 0 0>; /* CS0, offset 0 */
+		nand-bus-width = <8>;
+		ti,nand-ecc-opt = "bch8";
+		gpmc,device-nand = "true";
+		gpmc,device-width = <1>;
+
+		gpmc,sync-clk-ps = <0>;
+		gpmc,cs-on-ns = <0>;
+		gpmc,cs-rd-off-ns = <36>;
+		gpmc,cs-wr-off-ns = <36>;
+		gpmc,adv-on-ns = <6>;
+		gpmc,adv-rd-off-ns = <24>;
+		gpmc,adv-wr-off-ns = <36>;
+		gpmc,we-on-ns = <0>;
+		gpmc,we-off-ns = <30>;
+		gpmc,oe-on-ns = <0>;
+		gpmc,oe-off-ns = <48>;
+		gpmc,access-ns = <54>;
+		gpmc,rd-cycle-ns = <72>;
+		gpmc,wr-cycle-ns = <72>;
+
+		gpmc,wait-on-read = "true";
+		gpmc,wait-on-write = "true";
+		gpmc,bus-turnaround-ns = <0>;
+		gpmc,cycle2cycle-delay-ns = <0>;
+		gpmc,clk-activation-ns = <0>;
+		gpmc,wait-monitoring-ns = <0>;
+
+		gpmc,wr-access-ns = <30>;
+		gpmc,wr-data-mux-bus-ns = <0>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
+
+/include/ "am3xxx-pfc-nandparts.dtsi"
diff --git a/arch/arm/dts/am3xxx-pfc-nandparts.dtsi b/arch/arm/dts/am3xxx-pfc-nandparts.dtsi
new file mode 100644
index 0000000000..65dd56b815
--- /dev/null
+++ b/arch/arm/dts/am3xxx-pfc-nandparts.dtsi
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Copyright (C) 2015 WAGO Kontakttechnik GmbH & Co. KG <http://global.wago.com>
+ * Author: Oleg Karfich <oleg.karfich@wago.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+&nand {
+	        /* 4 x 128k MLOs */
+		partition@0 {
+			label = "mlo0";
+			reg = <0x0 0x20000>;
+		};
+
+		partition@20000 {
+			label = "mlo1";
+			reg = <0x20000 0x20000>;
+		};
+
+		partition@40000 {
+			label = "mlo2";
+			reg = <0x40000 0x20000>;
+		};
+
+		partition@60000 {
+			label = "mlo3";
+			reg = <0x60000 0x20000>;
+		};
+
+	        /* 16 x 128k: 4 x stage2 (4x128k) */
+		partition@80000 {
+			label = "boot0";
+			reg = <0x80000 0x80000>;
+		};
+
+		partition@100000 {
+			label = "boot1";
+			reg = <0x100000 0x80000>;
+		};
+
+		partition@180000 {
+			label = "boot2";
+			reg = <0x180000 0x80000>;
+		};
+
+		partition@200000 {
+			label = "boot3";
+			reg = <0x200000 0x80000>;
+		};
+
+		partition@280000 {
+			label = "ubidata";
+			/*
+			 * Size 0x0 extends partition to
+			 * end of nand flash.
+			 */
+			reg = <0x280000 0x0>;
+		};
+};
diff --git a/arch/arm/mach-omap/Kconfig b/arch/arm/mach-omap/Kconfig
index 5537f5101a..e793175f38 100644
--- a/arch/arm/mach-omap/Kconfig
+++ b/arch/arm/mach-omap/Kconfig
@@ -183,6 +183,15 @@ config MACH_VSCOM_BALTOS
 	help
 	  Say Y here if you are using a am335x based VScom Baltos devices
 
+config MACH_WAGO_PFC_AM35XX
+        bool "Wago PFC200 Fieldbus Controller"
+        select ARCH_AM35XX
+        select HAVE_DEFAULT_ENVIRONMENT_NEW
+        select HAVE_PBL_MULTI_IMAGES
+        select HAVE_CONFIGURABLE_MEMORY_LAYOUT
+        help
+          Say Y here if you are using a the AM3505 based PFC200 controller
+
 endif
 
 source arch/arm/boards/phytec-som-am335x/Kconfig
diff --git a/images/Makefile b/images/Makefile
index 4c6d486f08..90cb2ba29e 100644
--- a/images/Makefile
+++ b/images/Makefile
@@ -94,6 +94,7 @@ board = $(srctree)/arch/$(ARCH)/boards
 objboard = $(objtree)/arch/$(ARCH)/boards
 
 include $(srctree)/images/Makefile.am33xx
+include $(srctree)/images/Makefile.am35xx
 include $(srctree)/images/Makefile.bcm283x
 include $(srctree)/images/Makefile.imx
 include $(srctree)/images/Makefile.mvebu
diff --git a/images/Makefile.am35xx b/images/Makefile.am35xx
new file mode 100644
index 0000000000..6d30baee64
--- /dev/null
+++ b/images/Makefile.am35xx
@@ -0,0 +1,24 @@
+
+# %.mlo - convert into mlo image
+# ----------------------------------------------------------------
+quiet_cmd_mlo_image_am35xx = MLO     $@
+      cmd_mlo_image_am35xx = scripts/omap_signGP -o $@ -l 0x40200000 -c $<
+
+$(obj)/%.mlo-am35xx: $(obj)/% FORCE
+	$(call if_changed,mlo_image_am35xx)
+
+ifdef CONFIG_OMAP_BUILD_IFT
+pblb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += start_am35xx_pfc_750_820x_sram
+FILE_barebox-am35xx-pfc-750-820x-mlo.img = start_am35xx_pfc_750_820x_sram.pblb.mlo-am35xx
+am35xx-mlo-$(CONFIG_MACH_WAGO_PFC_AM35XX) += barebox-am35xx-pfc-750-820x-mlo.img
+endif
+
+pblb-$(CONFIG_MACH_WAGO_PFC_AM35XX) += start_am35xx_pfc_750_820x_sdram
+FILE_barebox-am35xx-pfc-750-820x.img = start_am35xx_pfc_750_820x_sdram.pblb
+am35xx-barebox-$(CONFIG_MACH_WAGO_PFC_AM35XX) += barebox-am35xx-pfc-750-820x.img
+
+ifdef CONFIG_OMAP_BUILD_IFT
+image-y += $(am35xx-mlo-y)
+else
+image-y += $(am35xx-barebox-y)
+endif
-- 
2.19.1


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[PATCH 23/23] ARM: omap: am33xx_defconfig: Enable more boards and rename

[Sascha Hauer]

Enable more boards in am33xx_defconfig. Since this now also supports
omap3 and am35xx boards rename it to omap_defconfig.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/configs/{am335x_defconfig => omap_defconfig} | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)
 rename arch/arm/configs/{am335x_defconfig => omap_defconfig} (96%)

diff --git a/arch/arm/configs/am335x_defconfig b/arch/arm/configs/omap_defconfig
similarity index 96%
rename from arch/arm/configs/am335x_defconfig
rename to arch/arm/configs/omap_defconfig
index 09dde908a3..e41757b919 100644
--- a/arch/arm/configs/am335x_defconfig
+++ b/arch/arm/configs/omap_defconfig
@@ -4,14 +4,16 @@ CONFIG_BAREBOX_UPDATE_AM33XX_NAND=y
 CONFIG_BAREBOX_UPDATE_AM33XX_EMMC=y
 CONFIG_OMAP_MULTI_BOARDS=y
 CONFIG_MACH_AFI_GF=y
+CONFIG_MACH_BEAGLE=y
 CONFIG_MACH_BEAGLEBONE=y
 CONFIG_MACH_PHYTEC_SOM_AM335X=y
+CONFIG_MACH_VSCOM_BALTOS=y
+CONFIG_MACH_WAGO_PFC_AM35XX=y
 CONFIG_THUMB2_BAREBOX=y
 CONFIG_ARM_BOARD_APPEND_ATAG=y
 CONFIG_ARM_OPTIMZED_STRING_FUNCTIONS=y
 CONFIG_ARM_UNWIND=y
 CONFIG_MMU=y
-CONFIG_TEXT_BASE=0x0
 CONFIG_MALLOC_SIZE=0x0
 CONFIG_MALLOC_TLSF=y
 CONFIG_KALLSYMS=y
@@ -98,6 +100,7 @@ CONFIG_OF_BAREBOX_DRIVERS=y
 CONFIG_DRIVER_SERIAL_NS16550=y
 CONFIG_DRIVER_SERIAL_NS16550_OMAP_EXTENSIONS=y
 CONFIG_DRIVER_NET_CPSW=y
+CONFIG_DRIVER_NET_DAVINCI_EMAC=y
 CONFIG_MICREL_PHY=y
 CONFIG_SMSC_PHY=y
 CONFIG_NET_USB=y
-- 
2.19.1


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Re: [PATCH 00/23] AM3517 support

[Ladislav Michl]

Hello Sascha,

On Fri, Dec 14, 2018 at 03:17:07PM +0100, Sascha Hauer wrote:
> This series adds support for the TI AM3517 SoC along with Wago PFC-200
> board support. Also in this series some TI related driver patches. Most
> notably some significant chages to the GPMC Nand driver which was not
> really working anymore.
> 
> Sascha
> 
> Heinrich Toews (3):
>   net: davinci-emac: fix buggy channel tear down
>   net: davinci-emac: switch to device tree support
>   ARM: omap: AM3517: Change default clock rate for AM3517
> 
> Oleg Karfich (1):
>   ARM: omap3: Add support for reset reason detection
> 
> Sascha Hauer (19):
>   net: davinci-emac: Add timeout to polling loop
>   mci: omap: Improve error handling
>   mci: omap: use IS_ENABLED() rather than #ifdef

>   mtd: nand: omap: Use dev_dbg when a struct device * is available
>   mtd: nand: omap: Fix hamming correct return values
>   mtd: nand: omap: Disable subpage reads in hardware ecc mode
>   mtd: nand: omap: remove unused function argument
>   mtd: nand: omap: fix bch8_hw_romcode ecc layout
>   mtd: nand: omap: set eccbytes correctly
>   mtd: nand: omap: unbreak BCH8 support

may I point there is a MTD update pending on mailing list which,
once applied, would make merging with upstream drivers easier?
Yes, that upstream, which already fixed those bugs...

>   ARM: omap: Add missing include
>   ARM: omap: dmtimer: Turn into a driver
>   ARM: omap: 32ktimer: Turn into a driver
>   ARM: omap: Add AM35XX support
>   ARM: omap: enable am33xx_uart_soft_reset for AM35xx
>   ARM: omap: Add AM3517 specific mux configuration
>   ARM: omap: Add emif4 support for AM3517
>   ARM: omap: Add board support for WAGO pfc200 platform
>   ARM: omap: am33xx_defconfig: Enable more boards and rename
> 
>  arch/arm/boards/Makefile                      |   1 +
>  arch/arm/boards/wago-pfc-am35xx/Makefile      |   6 +
>  arch/arm/boards/wago-pfc-am35xx/board-mlo.c   |  73 +++
>  arch/arm/boards/wago-pfc-am35xx/board.c       |  39 ++
>  arch/arm/boards/wago-pfc-am35xx/lowlevel.c    | 231 +++++++++
>  .../arm/configs/am35xx_pfc200_xload_defconfig |  40 ++
>  .../{am335x_defconfig => omap_defconfig}      |   5 +-
>  arch/arm/dts/Makefile                         |   1 +
>  arch/arm/dts/am35xx-pfc-750_820x.dts          | 487 ++++++++++++++++++
>  arch/arm/dts/am3xxx-pfc-nandparts.dtsi        |  63 +++
>  arch/arm/mach-omap/Kconfig                    |  24 +-
>  arch/arm/mach-omap/Makefile                   |   5 +-
>  arch/arm/mach-omap/am33xx_generic.c           |  32 +-
>  arch/arm/mach-omap/am35xx_emif4.c             |  85 +++
>  arch/arm/mach-omap/am3xxx.c                   |  32 ++
>  .../mach-omap/include/mach/am3xxx-silicon.h   |   6 +
>  arch/arm/mach-omap/include/mach/emif4.h       | 105 ++++
>  arch/arm/mach-omap/include/mach/omap3-clock.h |   2 +
>  arch/arm/mach-omap/include/mach/omap3-mux.h   |  49 +-
>  arch/arm/mach-omap/include/mach/sys_info.h    |   2 +
>  arch/arm/mach-omap/omap3_clock.c              |  16 +-
>  arch/arm/mach-omap/omap3_generic.c            |  58 ++-
>  arch/arm/mach-omap/omap4_generic.c            |   5 +-
>  drivers/clocksource/Kconfig                   |   6 +
>  drivers/clocksource/Makefile                  |   2 +
>  .../clocksource/timer-ti-32k.c                |  39 +-
>  .../clocksource/timer-ti-dm.c                 |  47 +-
>  drivers/mci/omap_hsmmc.c                      |  37 +-
>  drivers/mtd/nand/nand_omap_gpmc.c             | 141 +++--
>  drivers/net/davinci_emac.c                    | 210 +++++---
>  images/Makefile                               |   1 +
>  images/Makefile.am35xx                        |  24 +
>  include/platform_data/eth-davinci-emac.h      |  10 -
>  33 files changed, 1657 insertions(+), 227 deletions(-)
>  create mode 100644 arch/arm/boards/wago-pfc-am35xx/Makefile
>  create mode 100644 arch/arm/boards/wago-pfc-am35xx/board-mlo.c
>  create mode 100644 arch/arm/boards/wago-pfc-am35xx/board.c
>  create mode 100644 arch/arm/boards/wago-pfc-am35xx/lowlevel.c
>  create mode 100644 arch/arm/configs/am35xx_pfc200_xload_defconfig
>  rename arch/arm/configs/{am335x_defconfig => omap_defconfig} (96%)
>  create mode 100644 arch/arm/dts/am35xx-pfc-750_820x.dts
>  create mode 100644 arch/arm/dts/am3xxx-pfc-nandparts.dtsi
>  create mode 100644 arch/arm/mach-omap/am35xx_emif4.c
>  create mode 100644 arch/arm/mach-omap/am3xxx.c
>  create mode 100644 arch/arm/mach-omap/include/mach/am3xxx-silicon.h
>  create mode 100644 arch/arm/mach-omap/include/mach/emif4.h
>  rename arch/arm/mach-omap/s32k_clksource.c => drivers/clocksource/timer-ti-32k.c (73%)
>  rename arch/arm/mach-omap/dmtimer.c => drivers/clocksource/timer-ti-dm.c (72%)
>  create mode 100644 images/Makefile.am35xx
>  delete mode 100644 include/platform_data/eth-davinci-emac.h
> 
> -- 
> 2.19.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox

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Re: [PATCH 00/23] AM3517 support

[Sascha Hauer]

On Fri, Dec 14, 2018 at 05:22:49PM +0100, Ladislav Michl wrote:
> Hello Sascha,
> 
> On Fri, Dec 14, 2018 at 03:17:07PM +0100, Sascha Hauer wrote:
> > This series adds support for the TI AM3517 SoC along with Wago PFC-200
> > board support. Also in this series some TI related driver patches. Most
> > notably some significant chages to the GPMC Nand driver which was not
> > really working anymore.
> > 
> > Sascha
> > 
> > Heinrich Toews (3):
> >   net: davinci-emac: fix buggy channel tear down
> >   net: davinci-emac: switch to device tree support
> >   ARM: omap: AM3517: Change default clock rate for AM3517
> > 
> > Oleg Karfich (1):
> >   ARM: omap3: Add support for reset reason detection
> > 
> > Sascha Hauer (19):
> >   net: davinci-emac: Add timeout to polling loop
> >   mci: omap: Improve error handling
> >   mci: omap: use IS_ENABLED() rather than #ifdef
> 
> >   mtd: nand: omap: Use dev_dbg when a struct device * is available
> >   mtd: nand: omap: Fix hamming correct return values
> >   mtd: nand: omap: Disable subpage reads in hardware ecc mode
> >   mtd: nand: omap: remove unused function argument
> >   mtd: nand: omap: fix bch8_hw_romcode ecc layout
> >   mtd: nand: omap: set eccbytes correctly
> >   mtd: nand: omap: unbreak BCH8 support
> 
> may I point there is a MTD update pending on mailing list which,
> once applied, would make merging with upstream drivers easier?
> Yes, that upstream, which already fixed those bugs...

Hm, somehow I assumed you would send a v2. I applied the series now
along with the fixup you sent.

However, the barebox OMAP nand driver has the special feature that we
can switch the ECC mode during runtime, so even with a uptodate NAND
stack we would still have to make adjustments to the Linux driver.

You are right, a nand stack better in sync with Linux would make things
easier, your series is a start.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 14/23] ARM: omap: dmtimer: Turn into a driver

[Teresa Remmet]

Hello Sascha,

...

> diff --git a/arch/arm/mach-omap/dmtimer.c
> b/drivers/clocksource/timer-ti-dm.c
> similarity index 72%
> rename from arch/arm/mach-omap/dmtimer.c
> rename to drivers/clocksource/timer-ti-dm.c
> index e223b8cc8f..635b860cf9 100644
> --- a/arch/arm/mach-omap/dmtimer.c
> +++ b/drivers/clocksource/timer-ti-dm.c
> @@ -27,6 +27,7 @@
>   *
>   */
>  
> +#include <common.h>
>  #include <clock.h>
>  #include <init.h>
>  #include <io.h>
> @@ -55,7 +56,7 @@
>  #define TSICR			0x54
>  #define TCAR2			0x58
>  
> -static void *base = (void *)AM33XX_DMTIMER2_BASE;
> +static void *base;
>  
>  /**
>   * @brief Provide a simple counter read
> @@ -73,17 +74,20 @@ static struct clocksource dmtimer_cs = {
>  	.shift	= 10,
>  };
>  
> -/**
> - * @brief Initialize the Clock
> - *
> - * Enable dmtimer.
> - *
> - * @return result of @ref init_clock
> - */
> -static int dmtimer_init(void)
> +static int omap_dmtimer_probe(struct device_d *dev)
>  {
> +	struct resource *iores;
>  	u64 clk_speed;
>  
> +	/* one timer is enough */
> +	if (base)
> +		return 0;
> +
> +	iores = dev_request_mem_resource(dev, 0);
> +	if (IS_ERR(iores))
> +		return PTR_ERR(iores);
> +	base = IOMEM(iores->start);
> +
>  	clk_speed = am33xx_get_osc_clock();
>  	clk_speed *= 1000;
>  	dmtimer_cs.mult = clocksource_hz2mult(clk_speed,
> dmtimer_cs.shift);
> @@ -91,8 +95,27 @@ static int dmtimer_init(void)
>  	/* Enable counter */
>  	writel(0x3, base + TCLR);
>  
> -	return init_clock(&dmtimer_cs);
> +	init_clock(&dmtimer_cs);
> +
> +	return 0;

is there any reason why you always return 0 now?

Teresa

>  }
>  
> -/* Run me at boot time */
> -core_initcall(dmtimer_init);
> +static __maybe_unused struct of_device_id omap_dmtimer_dt_ids[] = {
> +	{
> +		.compatible = "ti,am335x-timer",
> +	}, {
> +		/* sentinel */
> +	}
> +};
> +
> +static struct driver_d omap_dmtimer_driver = {
> +	.name = "omap-dmtimer",
> +	.probe = omap_dmtimer_probe,
> +	.of_compatible = DRV_OF_COMPAT(omap_dmtimer_dt_ids),
> +};
> +
> +static int omap_dmtimer_init(void)
> +{
> +	return platform_driver_register(&omap_dmtimer_driver);
> +}
> +postcore_initcall(omap_dmtimer_init);

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Re: [PATCH 14/23] ARM: omap: dmtimer: Turn into a driver

[Sascha Hauer]

On Mon, Dec 17, 2018 at 02:37:57PM +0100, Teresa Remmet wrote:
> Hello Sascha,
> 
> >  	/* Enable counter */
> >  	writel(0x3, base + TCLR);
> >  
> > -	return init_clock(&dmtimer_cs);
> > +	init_clock(&dmtimer_cs);
> > +
> > +	return 0;
> 
> is there any reason why you always return 0 now?

No particular reason. Fixed it.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
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Re: [PATCH 22/23] ARM: omap: Add board support for WAGO pfc200 platform

[Heinrich.Toews]

Hi Sascha,

Am 14.12.18 um 15:17 schrieb Sascha Hauer:
> This adds support for the AM3517 based WAGO pfc100/200 SPS.
                                                   ^
CAUTION: The PFC100 SPS is based on AM335x and NOT AM35xx. Would be nice 
to fix the commit message in order to prevent a misunderstanding.

> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---

---

Thanks,
Heinrich
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Re: [PATCH 22/23] ARM: omap: Add board support for WAGO pfc200 platform

[Sascha Hauer]

Hi Heinrich,

On Mon, Jan 07, 2019 at 11:40:13AM +0000, Heinrich.Toews@wago.com wrote:
> Hi Sascha,
> 
> Am 14.12.18 um 15:17 schrieb Sascha Hauer:
> > This adds support for the AM3517 based WAGO pfc100/200 SPS.
>                                                    ^
> CAUTION: The PFC100 SPS is based on AM335x and NOT AM35xx. Would be nice 
> to fix the commit message in order to prevent a misunderstanding.

Thanks for noting. Just did that.

Sascha

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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