From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mail-pg1-x541.google.com ([2607:f8b0:4864:20::541]) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1gYlKF-0001MU-95 for barebox@lists.infradead.org; Mon, 17 Dec 2018 05:20:32 +0000 Received: by mail-pg1-x541.google.com with SMTP id d72so5521146pga.9 for ; Sun, 16 Dec 2018 21:20:08 -0800 (PST) From: Andrey Smirnov Date: Sun, 16 Dec 2018 21:18:42 -0800 Message-Id: <20181217051925.17582-23-andrew.smirnov@gmail.com> In-Reply-To: <20181217051925.17582-1-andrew.smirnov@gmail.com> References: <20181217051925.17582-1-andrew.smirnov@gmail.com> MIME-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH v2 22/65] PCI: designware: Check LTSSM training bit before deciding link is up To: barebox@lists.infradead.org Cc: Andrey Smirnov Port of a Linux commit 01c076732e8288485c22ef50f20949455a783ca9 The link may be up but still in link training. In this case, we can't think the link is up and operating correctly. Teach dw_pcie_link_up() to be aware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit. Also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that it's consistent with other macros. Signed-off-by: Jisheng Zhang Signed-off-by: Bjorn Helgaas Acked-by: Joao Pinto Signed-off-by: Andrey Smirnov --- drivers/pci/pcie-designware.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c index 5d0f782f4..a6006201e 100644 --- a/drivers/pci/pcie-designware.c +++ b/drivers/pci/pcie-designware.c @@ -98,7 +98,8 @@ /* PCIe Port Logic registers */ #define PLR_OFFSET 0x700 #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c) -#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010 +#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4) +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29) static unsigned long global_io_offset; @@ -279,7 +280,8 @@ int dw_pcie_link_up(struct pcie_port *pp) return pp->ops->link_up(pp); val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1); - return val & PCIE_PHY_DEBUG_R1_LINK_UP; + return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) && + !(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)); } static inline struct pcie_port *host_to_pcie(struct pci_controller *host) -- 2.19.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox