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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v2 38/65] PCI: imx6: Pass struct imx6_pcie to PHY accessors
Date: Sun, 16 Dec 2018 21:18:58 -0800	[thread overview]
Message-ID: <20181217051925.17582-39-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20181217051925.17582-1-andrew.smirnov@gmail.com>

Port of a Linux commit 8bad7f2fc3006d1752c426343ca77f1fbe61cf00

  Pass the struct imx6_pcie pointer, not dbi_base address, to PHY accessors.
  This enables future simplifications.  No functional change intended.

  Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/pci/pci-imx6.c | 41 +++++++++++++++++++++++------------------
 1 file changed, 23 insertions(+), 18 deletions(-)

diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index a3658844c..8b78f3ec1 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -94,8 +94,9 @@ struct imx6_pcie {
 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
 
-static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
+static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
 {
+	void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
 	u32 val;
 	u32 max_iterations = 10;
 	u32 wait_counter = 0;
@@ -114,8 +115,9 @@ static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val)
 	return -ETIMEDOUT;
 }
 
-static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
+static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
 {
+	void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
 	u32 val;
 	int ret;
 
@@ -125,23 +127,24 @@ static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr)
 	val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
 	writel(val, dbi_base + PCIE_PHY_CTRL);
 
-	ret = pcie_phy_poll_ack(dbi_base, 1);
+	ret = pcie_phy_poll_ack(imx6_pcie, 1);
 	if (ret)
 		return ret;
 
 	val = addr << PCIE_PHY_CTRL_DATA_LOC;
 	writel(val, dbi_base + PCIE_PHY_CTRL);
 
-	return pcie_phy_poll_ack(dbi_base, 0);
+	return pcie_phy_poll_ack(imx6_pcie, 0);
 }
 
 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
-static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
+static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr , int *data)
 {
+	void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
 	u32 val, phy_ctl;
 	int ret;
 
-	ret = pcie_phy_wait_ack(dbi_base, addr);
+	ret = pcie_phy_wait_ack(imx6_pcie, addr);
 	if (ret)
 		return ret;
 
@@ -149,7 +152,7 @@ static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
 	phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
 	writel(phy_ctl, dbi_base + PCIE_PHY_CTRL);
 
-	ret = pcie_phy_poll_ack(dbi_base, 1);
+	ret = pcie_phy_poll_ack(imx6_pcie, 1);
 	if (ret)
 		return ret;
 
@@ -159,17 +162,18 @@ static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data)
 	/* deassert Read signal */
 	writel(0x00, dbi_base + PCIE_PHY_CTRL);
 
-	return pcie_phy_poll_ack(dbi_base, 0);
+	return pcie_phy_poll_ack(imx6_pcie, 0);
 }
 
-static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
+static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
 {
+	void __iomem *dbi_base = imx6_pcie->pp.dbi_base;
 	u32 var;
 	int ret;
 
 	/* write addr */
 	/* cap addr */
-	ret = pcie_phy_wait_ack(dbi_base, addr);
+	ret = pcie_phy_wait_ack(imx6_pcie, addr);
 	if (ret)
 		return ret;
 
@@ -180,7 +184,7 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 	var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
 	writel(var, dbi_base + PCIE_PHY_CTRL);
 
-	ret = pcie_phy_poll_ack(dbi_base, 1);
+	ret = pcie_phy_poll_ack(imx6_pcie, 1);
 	if (ret)
 		return ret;
 
@@ -189,7 +193,7 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 	writel(var, dbi_base + PCIE_PHY_CTRL);
 
 	/* wait for ack de-assertion */
-	ret = pcie_phy_poll_ack(dbi_base, 0);
+	ret = pcie_phy_poll_ack(imx6_pcie, 0);
 	if (ret)
 		return ret;
 
@@ -198,7 +202,7 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 	writel(var, dbi_base + PCIE_PHY_CTRL);
 
 	/* wait for ack */
-	ret = pcie_phy_poll_ack(dbi_base, 1);
+	ret = pcie_phy_poll_ack(imx6_pcie, 1);
 	if (ret)
 		return ret;
 
@@ -207,7 +211,7 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 	writel(var, dbi_base + PCIE_PHY_CTRL);
 
 	/* wait for ack de-assertion */
-	ret = pcie_phy_poll_ack(dbi_base, 0);
+	ret = pcie_phy_poll_ack(imx6_pcie, 0);
 	if (ret)
 		return ret;
 
@@ -218,19 +222,20 @@ static int pcie_phy_write(void __iomem *dbi_base, int addr, int data)
 
 static void imx6_pcie_reset_phy(struct pcie_port *pp)
 {
+	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	uint32_t temp;
 
-	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
+	pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &temp);
 	temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 		 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+	pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, temp);
 
 	udelay(2000);
 
-	pcie_phy_read(pp->dbi_base, PHY_RX_OVRD_IN_LO, &temp);
+	pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &temp);
 	temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 		  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
-	pcie_phy_write(pp->dbi_base, PHY_RX_OVRD_IN_LO, temp);
+	pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, temp);
 }
 
 static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
-- 
2.19.1


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  parent reply	other threads:[~2018-12-17  5:20 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-17  5:18 [PATCH v2 00/65] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 01/65] PCI: desginware: Remove bogus prototypes Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 02/65] PCI: designware: Consolidate outbound iATU programming functions Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 03/65] PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 04/65] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 05/65] PCI: designware: Use exact access size in dw_pcie_cfg_read() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 06/65] PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 07/65] PCI: designware: Require config accesses to be naturally aligned Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 08/65] PCI: designware: Make "num-lanes" an optional DT property Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 09/65] PCI: designware: Ensure ATU is enabled before IO/conf space accesses Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 10/65] PCI: designware: Simplify control flow Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 11/65] PCI: designware: Make config accessor override checking symmetric Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 12/65] PCI: designware: Explain why we don't program ATU for some platforms Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 13/65] PCI: imx6: Move link up check into imx6_pcie_wait_for_link() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 14/65] PCI: designware: Add generic dw_pcie_wait_for_link() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 15/65] PCI: designware: Add default link up check if sub-driver doesn't override Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 16/65] PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 17/65] PCI: designware: Remove incorrect RC memory base/limit configuration Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 18/65] PCI: designware: Return data directly from dw_pcie_readl_rc() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 19/65] PCI: designware: Move link wait definitions to .c file Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 20/65] PCI: designware: Wait for iATU enable Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 21/65] PCI: designware: Add iATU Unroll feature Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 22/65] PCI: designware: Check LTSSM training bit before deciding link is up Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 23/65] PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 24/65] PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 25/65] PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 26/65] PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 27/65] PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 28/65] PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 29/65] PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 30/65] PCI: designware: Uninline register accessors Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 31/65] PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 32/65] PCI: designware: Check for iATU unroll only on platforms that use ATU Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 33/65] PCI: dwc: designware: Move register defines to designware header file Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 34/65] PCI: dwc: all: Rename cfg_read/cfg_write to read/write Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 35/65] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 36/65] PCI: imx6: Add local struct device pointers Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 37/65] PCI: imx6: Removed unused struct imx6_pcie.mem_base Andrey Smirnov
2018-12-17  5:18 ` Andrey Smirnov [this message]
2018-12-17  5:18 ` [PATCH v2 39/65] PCI: imx6: Pass device-specific struct to internal functions Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 40/65] PCI: imx6: Use generic DesignWare accessors Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 41/65] PCI: imx6: Reorder struct imx6_pcie Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 42/65] PCI: imx6: Port error messages for imx6_pcie_deassert_core_reset() Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 43/65] PCI: imx6: Remove unused return values Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 44/65] PCI: imx6: Factor out ref clock enable Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 45/65] PCI: imx6: Add DT property for link gen, default to Gen1 Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 46/65] PCI: imx6: Remove redundant "Link never came up" message Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 47/65] PCI: imx6: Remove LTSSM disable workaround Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 48/65] PCI: dwc: all: Split struct pcie_port into host-only and core structures Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 49/65] PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 50/65] PCI: dwc: designware: Fix style errors in pcie-designware.c Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 51/65] PCI: dwc: Split pcie-designware.c into host and core files Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 52/65] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 53/65] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 54/65] PCI: dwc: designware: Move _unroll configurations to a separate function Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 55/65] PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 56/65] PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 57/65] PCI: Fix typos and whitespace errors Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 58/65] PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 59/65] PCI: dwc: Replace lower into upper case characters Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 60/65] PCI: dwc: designware: Handle ->host_init() failures Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 61/65] PCI: dwc: Add accessors for write permission of DBI Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 62/65] PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 63/65] PCI: dwc: Fix enumeration end when reaching root subordinate Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 64/65] PCI: dwc: Small computation improvement Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 65/65] PCI: dwc: Constify dw_pcie_host_ops structures Andrey Smirnov
2019-01-07 22:55 ` [PATCH v2 00/65] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov
2019-01-08 15:31   ` Sascha Hauer

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