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From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: barebox@lists.infradead.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>
Subject: [PATCH v2 39/65] PCI: imx6: Pass device-specific struct to internal functions
Date: Sun, 16 Dec 2018 21:18:59 -0800	[thread overview]
Message-ID: <20181217051925.17582-40-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20181217051925.17582-1-andrew.smirnov@gmail.com>

Port of a Linux commit e7d7705ace9494949863848ec77536d5a3287b0a

   Only interfaces used from outside the driver, e.g., those called by
   the DesignWare core, need to accept pointers to the generic struct
   pcie_port.  Internal interfaces can accept pointers to the
   device-specific struct, which makes them more straightforward.  No
   functional change intended.

   Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 drivers/pci/pci-imx6.c | 53 ++++++++++++++++++++----------------------
 1 file changed, 25 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index 8b78f3ec1..4692dab5b 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -220,9 +220,8 @@ static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
 	return 0;
 }
 
-static void imx6_pcie_reset_phy(struct pcie_port *pp)
+static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
 {
-	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	uint32_t temp;
 
 	pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &temp);
@@ -238,9 +237,9 @@ static void imx6_pcie_reset_phy(struct pcie_port *pp)
 	pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, temp);
 }
 
-static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
+static int imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 {
-	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+	struct pcie_port *pp = &imx6_pcie->pp;
 	u32 val, gpr1, gpr12;
 
 	switch (imx6_pcie->variant) {
@@ -289,9 +288,8 @@ static int imx6_pcie_assert_core_reset(struct pcie_port *pp)
 	return 0;
 }
 
-static int imx6_pcie_deassert_core_reset(struct pcie_port *pp)
+static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 {
-	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	int ret;
 	u32 gpr1;
 
@@ -358,9 +356,8 @@ err_pcie_phy:
 
 }
 
-static void imx6_pcie_init_phy(struct pcie_port *pp)
+static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 {
-	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 	u32 gpr12, gpr8;
 
 	gpr12 = readl(imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
@@ -398,13 +395,14 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
 	writel(gpr8, imx6_pcie->iomuxc_gpr + IOMUXC_GPR8);
 }
 
-static int imx6_pcie_wait_for_link(struct pcie_port *pp)
+static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
 {
-	return dw_pcie_wait_for_link(pp);
+	return dw_pcie_wait_for_link(&imx6_pcie->pp);
 }
 
-static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
+static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
 {
+	struct pcie_port *pp = &imx6_pcie->pp;
 	struct device_d *dev = pp->dev;
 	uint32_t tmp;
 	uint64_t start = get_time_ns();
@@ -421,9 +419,9 @@ static int imx6_pcie_wait_for_speed_change(struct pcie_port *pp)
 }
 
 
-static int imx6_pcie_establish_link(struct pcie_port *pp)
+static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
 {
-	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
+	struct pcie_port *pp = &imx6_pcie->pp;
 	struct device_d *dev = pp->dev;
 	uint32_t tmp;
 	int ret;
@@ -444,7 +442,7 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
 	gpr12 |= IMX6Q_GPR12_PCIE_CTL_2;
 	writel(gpr12, imx6_pcie->iomuxc_gpr + IOMUXC_GPR12);
 
-	ret = imx6_pcie_wait_for_link(pp);
+	ret = imx6_pcie_wait_for_link(imx6_pcie);
 	if (ret) {
 		dev_info(dev, "Link never came up\n");
 		goto err_reset_phy;
@@ -464,14 +462,14 @@ static int imx6_pcie_establish_link(struct pcie_port *pp)
 	tmp |= PORT_LOGIC_SPEED_CHANGE;
 	writel(tmp, pp->dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
 
-	ret = imx6_pcie_wait_for_speed_change(pp);
+	ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
 	if (ret) {
 		dev_err(dev, "Failed to bring link up!\n");
 		goto err_reset_phy;
 	}
 
 	/* Make sure link training is finished as well! */
-	ret = imx6_pcie_wait_for_link(pp);
+	ret = imx6_pcie_wait_for_link(imx6_pcie);
 	if (ret) {
 		dev_err(dev, "Failed to bring link up!\n");
 		goto err_reset_phy;
@@ -486,22 +484,20 @@ err_reset_phy:
        dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
                readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
                readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
-       imx6_pcie_reset_phy(pp);
+       imx6_pcie_reset_phy(imx6_pcie);
 
        return ret;
 }
 
 static void imx6_pcie_host_init(struct pcie_port *pp)
 {
-	imx6_pcie_assert_core_reset(pp);
-
-	imx6_pcie_init_phy(pp);
-
-	imx6_pcie_deassert_core_reset(pp);
+	struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp);
 
+	imx6_pcie_assert_core_reset(imx6_pcie);
+	imx6_pcie_init_phy(imx6_pcie);
+	imx6_pcie_deassert_core_reset(imx6_pcie);
 	dw_pcie_setup_rc(pp);
-
-	imx6_pcie_establish_link(pp);
+	imx6_pcie_establish_link(imx6_pcie);
 }
 
 static int imx6_pcie_link_up(struct pcie_port *pp)
@@ -550,9 +546,10 @@ static struct pcie_host_ops imx6_pcie_host_ops = {
 	.host_init = imx6_pcie_host_init,
 };
 
-static int __init imx6_add_pcie_port(struct pcie_port *pp,
-			struct device_d *dev)
+static int __init imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
+				     struct device_d *dev)
 {
+	struct pcie_port *pp = &imx6_pcie->pp;
 	int ret;
 
 	pp->root_bus_nr = -1;
@@ -642,7 +639,7 @@ static int __init imx6_pcie_probe(struct device_d *dev)
 				 &imx6_pcie->tx_swing_low))
 		imx6_pcie->tx_swing_low = 127;
 
-	ret = imx6_add_pcie_port(pp, dev);
+	ret = imx6_add_pcie_port(imx6_pcie, dev);
 	if (ret < 0)
 		return ret;
 
@@ -655,7 +652,7 @@ static void imx6_pcie_remove(struct device_d *dev)
 {
 	struct imx6_pcie *imx6_pcie = dev->priv;
 
-	imx6_pcie_assert_core_reset(&imx6_pcie->pp);
+	imx6_pcie_assert_core_reset(imx6_pcie);
 }
 
 static struct of_device_id imx6_pcie_of_match[] = {
-- 
2.19.1


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  parent reply	other threads:[~2018-12-17  5:20 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-12-17  5:18 [PATCH v2 00/65] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 01/65] PCI: desginware: Remove bogus prototypes Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 02/65] PCI: designware: Consolidate outbound iATU programming functions Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 03/65] PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 04/65] PCI: designware: Fix PORT_LOGIC_LINK_WIDTH_MASK Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 05/65] PCI: designware: Use exact access size in dw_pcie_cfg_read() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 06/65] PCI: designware: Simplify dw_pcie_cfg_read/write() interfaces Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 07/65] PCI: designware: Require config accesses to be naturally aligned Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 08/65] PCI: designware: Make "num-lanes" an optional DT property Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 09/65] PCI: designware: Ensure ATU is enabled before IO/conf space accesses Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 10/65] PCI: designware: Simplify control flow Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 11/65] PCI: designware: Make config accessor override checking symmetric Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 12/65] PCI: designware: Explain why we don't program ATU for some platforms Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 13/65] PCI: imx6: Move link up check into imx6_pcie_wait_for_link() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 14/65] PCI: designware: Add generic dw_pcie_wait_for_link() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 15/65] PCI: designware: Add default link up check if sub-driver doesn't override Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 16/65] PCI: designware: Move Root Complex setup code to dw_pcie_setup_rc() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 17/65] PCI: designware: Remove incorrect RC memory base/limit configuration Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 18/65] PCI: designware: Return data directly from dw_pcie_readl_rc() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 19/65] PCI: designware: Move link wait definitions to .c file Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 20/65] PCI: designware: Wait for iATU enable Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 21/65] PCI: designware: Add iATU Unroll feature Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 22/65] PCI: designware: Check LTSSM training bit before deciding link is up Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 23/65] PCI: designware: Keep viewport fixed for IO transaction if num_viewport > 2 Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 24/65] PCI: designware: Exchange viewport of `MEMORYs' and `CFGs/IOs' Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 25/65] PCI: designware: Rename dw_pcie_valid_config() to dw_pcie_valid_device() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 26/65] PCI: designware: Simplify dw_pcie_readl_unroll(), dw_pcie_writel_unroll() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 27/65] PCI: designware: Simplify pcie_host_ops.readl_rc() and .writel_rc() interfaces Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 28/65] PCI: designware: Swap order of dw_pcie_writel_rc() reg/val arguments Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 29/65] PCI: designware: Export dw_pcie_readl_rc(), dw_pcie_writel_rc() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 30/65] PCI: designware: Uninline register accessors Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 31/65] PCI: designware: Swap order of dw_pcie_writel_unroll() reg/val arguments Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 32/65] PCI: designware: Check for iATU unroll only on platforms that use ATU Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 33/65] PCI: dwc: designware: Move register defines to designware header file Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 34/65] PCI: dwc: all: Rename cfg_read/cfg_write to read/write Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 35/65] PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init() Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 36/65] PCI: imx6: Add local struct device pointers Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 37/65] PCI: imx6: Removed unused struct imx6_pcie.mem_base Andrey Smirnov
2018-12-17  5:18 ` [PATCH v2 38/65] PCI: imx6: Pass struct imx6_pcie to PHY accessors Andrey Smirnov
2018-12-17  5:18 ` Andrey Smirnov [this message]
2018-12-17  5:19 ` [PATCH v2 40/65] PCI: imx6: Use generic DesignWare accessors Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 41/65] PCI: imx6: Reorder struct imx6_pcie Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 42/65] PCI: imx6: Port error messages for imx6_pcie_deassert_core_reset() Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 43/65] PCI: imx6: Remove unused return values Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 44/65] PCI: imx6: Factor out ref clock enable Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 45/65] PCI: imx6: Add DT property for link gen, default to Gen1 Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 46/65] PCI: imx6: Remove redundant "Link never came up" message Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 47/65] PCI: imx6: Remove LTSSM disable workaround Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 48/65] PCI: dwc: all: Split struct pcie_port into host-only and core structures Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 49/65] PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc() Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 50/65] PCI: dwc: designware: Fix style errors in pcie-designware.c Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 51/65] PCI: dwc: Split pcie-designware.c into host and core files Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 52/65] PCI: dwc: all: Modify dbi accessors to take dbi_base as argument Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 53/65] PCI: dwc: all: Modify dbi accessors to access data of 4/2/1 bytes Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 54/65] PCI: dwc: designware: Move _unroll configurations to a separate function Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 55/65] PCI: dwc: designware: Test PCIE_ATU_ENABLE bit specifically Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 56/65] PCI: dwc: designware: Make dw_pcie_prog_*_atu_unroll() static Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 57/65] PCI: Fix typos and whitespace errors Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 58/65] PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplate Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 59/65] PCI: dwc: Replace lower into upper case characters Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 60/65] PCI: dwc: designware: Handle ->host_init() failures Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 61/65] PCI: dwc: Add accessors for write permission of DBI Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 62/65] PCI: dwc: Enable write permission for Class Code, Interrupt Pin updates Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 63/65] PCI: dwc: Fix enumeration end when reaching root subordinate Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 64/65] PCI: dwc: Small computation improvement Andrey Smirnov
2018-12-17  5:19 ` [PATCH v2 65/65] PCI: dwc: Constify dw_pcie_host_ops structures Andrey Smirnov
2019-01-07 22:55 ` [PATCH v2 00/65] PCI i.MX6/DesignWare sync up with 4.20-rc1 Andrey Smirnov
2019-01-08 15:31   ` Sascha Hauer

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