From: Lukasz Madej <l.madej@grinn-global.com>
To: barebox@lists.infradead.org
Cc: Lukasz Madej <l.madej@grinn-global.com>
Subject: [PATCH] ARM: imx7: missing config for AIPS3 bridge added
Date: Thu, 3 Jan 2019 10:22:21 +0100 [thread overview]
Message-ID: <20190103092221.5937-1-l.madej@grinn-global.com> (raw)
Access priviledges for AIPS3 bridge have been configured so peripherals
connected to it (like SDMA, SAI etc.) can work properly.
Signed-off-by: Lukasz Madej <l.madej@grinn-global.com>
---
arch/arm/mach-imx/imx7.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/mach-imx/imx7.c b/arch/arm/mach-imx/imx7.c
index ca11e8345..ff2a828c7 100644
--- a/arch/arm/mach-imx/imx7.c
+++ b/arch/arm/mach-imx/imx7.c
@@ -26,6 +26,7 @@ void imx7_init_lowlevel(void)
{
void __iomem *aips1 = IOMEM(MX7_AIPS1_CONFIG_BASE_ADDR);
void __iomem *aips2 = IOMEM(MX7_AIPS2_CONFIG_BASE_ADDR);
+ void __iomem *aips3 = IOMEM(MX7_AIPS3_CONFIG_BASE_ADDR);
/*
* Set all MPROTx to be non-bufferable, trusted for R/W,
@@ -46,6 +47,14 @@ void imx7_init_lowlevel(void)
writel(0, aips2 + 0x48);
writel(0, aips2 + 0x4c);
writel(0, aips2 + 0x50);
+
+ writel(0x77777777, aips3);
+ writel(0x77777777, aips3 + 0x4);
+ writel(0, aips3 + 0x40);
+ writel(0, aips3 + 0x44);
+ writel(0, aips3 + 0x48);
+ writel(0, aips3 + 0x4c);
+ writel(0, aips3 + 0x50);
}
#define SC_CNTCR 0x0
--
2.11.0
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next reply other threads:[~2019-01-03 9:22 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-03 9:22 Lukasz Madej [this message]
2019-01-03 11:18 ` Sascha Hauer
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