* [PATCH 01/11] ARM: at91: clk: prune never-compiled h32mx code
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 02/11] ARM: at91: sama5d3: remove never referenced empty header file Ahmad Fatoum
` (10 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
This code is conditionally compiled when CONFIG_HAVE_AT91_H32MX
is defined, which never happens as it neither has a prompt
nor does another option select it.
As no one seems to miss it till now, just remove it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Kconfig | 3 -
drivers/clk/at91/Makefile | 1 -
drivers/clk/at91/clk-h32mx.c | 125 -----------------------------------
3 files changed, 129 deletions(-)
delete mode 100644 drivers/clk/at91/clk-h32mx.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index b101e61d221d..63e6e7285931 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -30,9 +30,6 @@ config MACH_AT91SAM9263EK_DT
config HAVE_AT91_SMD
bool
-config HAVE_AT91_H32MX
- bool
-
config HAVE_AT91_GENERATED_CLK
bool
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 13e67bd35cff..b1fe8b010797 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -9,5 +9,4 @@ obj-y += clk-system.o clk-peripheral.o clk-programmable.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
-obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
deleted file mode 100644
index e0daa4a31f88..000000000000
--- a/drivers/clk/at91/clk-h32mx.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * clk-h32mx.c
- *
- * Copyright (C) 2014 Atmel
- *
- * Alexandre Belloni <alexandre.belloni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- */
-
-#include <linux/clk-provider.h>
-#include <linux/clkdev.h>
-#include <linux/clk/at91_pmc.h>
-#include <linux/of.h>
-#include <linux/regmap.h>
-#include <linux/mfd/syscon.h>
-
-#include "pmc.h"
-
-#define H32MX_MAX_FREQ 90000000
-
-struct clk_sama5d4_h32mx {
- struct clk_hw hw;
- struct regmap *regmap;
-};
-
-#define to_clk_sama5d4_h32mx(hw) container_of(hw, struct clk_sama5d4_h32mx, hw)
-
-static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
- unsigned long parent_rate)
-{
- struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
- unsigned int mckr;
-
- regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr);
- if (mckr & AT91_PMC_H32MXDIV)
- return parent_rate / 2;
-
- if (parent_rate > H32MX_MAX_FREQ)
- pr_warn("H32MX clock is too fast\n");
- return parent_rate;
-}
-
-static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
-{
- unsigned long div;
-
- if (rate > *parent_rate)
- return *parent_rate;
- div = *parent_rate / 2;
- if (rate < div)
- return div;
-
- if (rate - div < *parent_rate - rate)
- return div;
-
- return *parent_rate;
-}
-
-static int clk_sama5d4_h32mx_set_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long parent_rate)
-{
- struct clk_sama5d4_h32mx *h32mxclk = to_clk_sama5d4_h32mx(hw);
- u32 mckr = 0;
-
- if (parent_rate != rate && (parent_rate / 2) != rate)
- return -EINVAL;
-
- if ((parent_rate / 2) == rate)
- mckr = AT91_PMC_H32MXDIV;
-
- regmap_update_bits(h32mxclk->regmap, AT91_PMC_MCKR,
- AT91_PMC_H32MXDIV, mckr);
-
- return 0;
-}
-
-static const struct clk_ops h32mx_ops = {
- .recalc_rate = clk_sama5d4_h32mx_recalc_rate,
- .round_rate = clk_sama5d4_h32mx_round_rate,
- .set_rate = clk_sama5d4_h32mx_set_rate,
-};
-
-static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
-{
- struct clk_sama5d4_h32mx *h32mxclk;
- struct clk_init_data init;
- const char *parent_name;
- struct regmap *regmap;
- int ret;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
- if (!h32mxclk)
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- init.name = np->name;
- init.ops = &h32mx_ops;
- init.parent_names = parent_name ? &parent_name : NULL;
- init.num_parents = parent_name ? 1 : 0;
- init.flags = CLK_SET_RATE_GATE;
-
- h32mxclk->hw.init = &init;
- h32mxclk->regmap = regmap;
-
- ret = clk_hw_register(NULL, &h32mxclk->hw);
- if (ret) {
- kfree(h32mxclk);
- return;
- }
-
- of_clk_add_hw_provider(np, of_clk_hw_simple_get, &h32mxclk->hw);
-}
-CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
- of_sama5d4_clk_h32mx_setup);
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 02/11] ARM: at91: sama5d3: remove never referenced empty header file
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 01/11] ARM: at91: clk: prune never-compiled h32mx code Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 03/11] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's Ahmad Fatoum
` (9 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
The file was added along with the sama5d3 support, but never used,
so remove it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/include/mach/sama5d3_matrix.h | 15 ---------------
1 file changed, 15 deletions(-)
delete mode 100644 arch/arm/mach-at91/include/mach/sama5d3_matrix.h
diff --git a/arch/arm/mach-at91/include/mach/sama5d3_matrix.h b/arch/arm/mach-at91/include/mach/sama5d3_matrix.h
deleted file mode 100644
index 8176b38bd328..000000000000
--- a/arch/arm/mach-at91/include/mach/sama5d3_matrix.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Matrix-centric header file for the SAMA5D3 family
- *
- * Copyright (C) 2009-2012 Atmel Corporation.
- *
- * Only EBI related registers.
- * Write Protect register definitions may be useful.
- *
- * Licensed under GPLv2 or later.
- */
-
-#ifndef SAMA5D3_MATRIX_H
-#define SAMA5D3_MATRIX_H
-
-#endif
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 03/11] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 01/11] ARM: at91: clk: prune never-compiled h32mx code Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 02/11] ARM: at91: sama5d3: remove never referenced empty header file Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 18:24 ` Sam Ravnborg
2019-01-16 17:45 ` [PATCH 04/11] ARM: at91: watchdog: implement at91_wdt_disable Ahmad Fatoum
` (8 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
Only at91sam9g45_reset.S and the header itself actually use
any of the macros defined within.
Instead of adding missing definitions and adapting the incoming DDRAMC
initialization code from at91bootstrap, just include the at91_ddrsdrc.h
header wholesale.
This patch shouldn't affect resulting binaries.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/boards/at91sam9m10g45ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9m10ihd/lowlevel.c | 2 +-
arch/arm/boards/at91sam9n12ek/lowlevel.c | 2 +-
arch/arm/boards/at91sam9x5ek/lowlevel.c | 2 +-
arch/arm/boards/pm9g45/lowlevel.c | 3 +-
arch/arm/boards/sama5d3_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d3xek/lowlevel.c | 2 +-
arch/arm/boards/sama5d4_xplained/lowlevel.c | 2 +-
arch/arm/boards/sama5d4ek/lowlevel.c | 2 +-
arch/arm/mach-at91/at91sam9g45_devices.c | 2 +-
arch/arm/mach-at91/at91sam9g45_reset.S | 8 +-
arch/arm/mach-at91/at91sam9n12_devices.c | 2 +-
arch/arm/mach-at91/at91sam9x5_devices.c | 2 +-
.../arm/mach-at91/include/mach/at91_ddrsdrc.h | 426 ++++++++++++++++++
.../mach-at91/include/mach/at91sam9_ddrsdr.h | 264 -----------
arch/arm/mach-at91/sama5d3_devices.c | 2 +-
arch/arm/mach-at91/sama5d4_devices.c | 2 +-
17 files changed, 445 insertions(+), 282 deletions(-)
create mode 100644 arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
delete mode 100644 arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
diff --git a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
index 478ff11e1dfe..b0161553ed05 100644
--- a/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10g45ek/lowlevel.c
@@ -11,7 +11,7 @@
#include <asm/barebox-arm.h>
#include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
void __naked __bare_init barebox_arm_reset_vector(void)
{
diff --git a/arch/arm/boards/at91sam9m10ihd/lowlevel.c b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
index d5940b987afa..c660b18e8854 100644
--- a/arch/arm/boards/at91sam9m10ihd/lowlevel.c
+++ b/arch/arm/boards/at91sam9m10ihd/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/at91sam9g45.h>
#include <mach/hardware.h>
diff --git a/arch/arm/boards/at91sam9n12ek/lowlevel.c b/arch/arm/boards/at91sam9n12ek/lowlevel.c
index 47079336e632..de8308725ac9 100644
--- a/arch/arm/boards/at91sam9n12ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9n12ek/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/at91sam9x5ek/lowlevel.c b/arch/arm/boards/at91sam9x5ek/lowlevel.c
index 9aa0e8ba9b2b..aefe18d1c92e 100644
--- a/arch/arm/boards/at91sam9x5ek/lowlevel.c
+++ b/arch/arm/boards/at91sam9x5ek/lowlevel.c
@@ -1,6 +1,6 @@
#include <common.h>
#include <linux/sizes.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
#include <io.h>
diff --git a/arch/arm/boards/pm9g45/lowlevel.c b/arch/arm/boards/pm9g45/lowlevel.c
index 67454bde268c..d64ebef27407 100644
--- a/arch/arm/boards/pm9g45/lowlevel.c
+++ b/arch/arm/boards/pm9g45/lowlevel.c
@@ -10,7 +10,8 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
+
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/sama5d3_xplained/lowlevel.c b/arch/arm/boards/sama5d3_xplained/lowlevel.c
index b791f2a03cc7..41cc0e1f49db 100644
--- a/arch/arm/boards/sama5d3_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d3_xplained/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/sama5d3xek/lowlevel.c b/arch/arm/boards/sama5d3xek/lowlevel.c
index b791f2a03cc7..41cc0e1f49db 100644
--- a/arch/arm/boards/sama5d3xek/lowlevel.c
+++ b/arch/arm/boards/sama5d3xek/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/sama5d4_xplained/lowlevel.c b/arch/arm/boards/sama5d4_xplained/lowlevel.c
index b791f2a03cc7..41cc0e1f49db 100644
--- a/arch/arm/boards/sama5d4_xplained/lowlevel.c
+++ b/arch/arm/boards/sama5d4_xplained/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/boards/sama5d4ek/lowlevel.c b/arch/arm/boards/sama5d4ek/lowlevel.c
index b791f2a03cc7..41cc0e1f49db 100644
--- a/arch/arm/boards/sama5d4ek/lowlevel.c
+++ b/arch/arm/boards/sama5d4ek/lowlevel.c
@@ -10,7 +10,7 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/hardware.h>
void __naked __bare_init barebox_arm_reset_vector(void)
diff --git a/arch/arm/mach-at91/at91sam9g45_devices.c b/arch/arm/mach-at91/at91sam9g45_devices.c
index 43d8d5fbd6a2..389d88c17d4f 100644
--- a/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -17,7 +17,7 @@
#include <mach/hardware.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9g45_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/at91_rtt.h>
#include <mach/board.h>
#include <mach/iomux.h>
diff --git a/arch/arm/mach-at91/at91sam9g45_reset.S b/arch/arm/mach-at91/at91sam9g45_reset.S
index 6a58de618ce0..9f2a90ff82f1 100644
--- a/arch/arm/mach-at91/at91sam9g45_reset.S
+++ b/arch/arm/mach-at91/at91sam9g45_reset.S
@@ -12,7 +12,7 @@
#include <linux/linkage.h>
#include <mach/hardware.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/at91_rstc.h>
.arm
@@ -20,13 +20,13 @@
.globl at91sam9g45_reset
at91sam9g45_reset: mov r2, #1
- mov r3, #AT91_DDRSDRC_LPCB_POWER_DOWN
+ mov r3, #AT91C_DDRC2_LPCB_POWERDOWN
ldr r4, =AT91_RSTC_KEY | AT91_RSTC_PERRST | AT91_RSTC_PROCRST
.balign 32 @ align to cache line
- str r2, [r0, #AT91_DDRSDRC_RTR] @ disable DDR0 access
- str r3, [r0, #AT91_DDRSDRC_LPR] @ power down DDR0
+ str r2, [r0, #HDDRSDRC2_RTR] @ disable DDR0 access
+ str r3, [r0, #HDDRSDRC2_LPR] @ power down DDR0
str r4, [r1] @ reset processor
b .
diff --git a/arch/arm/mach-at91/at91sam9n12_devices.c b/arch/arm/mach-at91/at91sam9n12_devices.c
index 43cbb79af4a5..91b3e9b2fbc5 100644
--- a/arch/arm/mach-at91/at91sam9n12_devices.c
+++ b/arch/arm/mach-at91/at91sam9n12_devices.c
@@ -18,7 +18,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9n12_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/at91sam9x5_devices.c b/arch/arm/mach-at91/at91sam9x5_devices.c
index ab506a1f4236..022e4fb59ab9 100644
--- a/arch/arm/mach-at91/at91sam9x5_devices.c
+++ b/arch/arm/mach-at91/at91sam9x5_devices.c
@@ -17,7 +17,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
new file mode 100644
index 000000000000..263d51f3ee9a
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_ddrsdrc.h
@@ -0,0 +1,426 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+#ifndef __AT91_DDRSDRC_H__
+#define __AT91_DDRSDRC_H__
+
+/**** Register offset in AT91S_HDDRSDRC2 structure ***/
+#define HDDRSDRC2_MR 0x00 /* Mode Register */
+#define HDDRSDRC2_RTR 0x04 /* Refresh Timer Register */
+#define HDDRSDRC2_CR 0x08 /* Configuration Register */
+#define HDDRSDRC2_T0PR 0x0C /* Timing Parameter 0 Register */
+#define HDDRSDRC2_T1PR 0x10 /* Timing Parameter 1 Register */
+#define HDDRSDRC2_T2PR 0x14 /* Timing Parameter 2 Register */
+#define HDDRSDRC2_T3PR 0x18 /* Timing Parameter 3 Register */
+#define HDDRSDRC2_LPR 0x1C /* Low-power Register */
+#define HDDRSDRC2_MDR 0x20 /* Memory Device Register */
+#define HDDRSDRC2_DLL 0x24 /* DLL Information Register */
+#define HDDRSDRC2_HS 0x2C /* High Speed Register */
+
+/* below items defined for sama5d3x */
+#define MPDDRC_LPDDR2_HS 0x24 /* MPDDRC LPDDR2 High Speed Register */
+#define MPDDRC_LPDDR2_LPR 0x28 /* MPDDRC LPDDR2 Low-power Register */
+#define MPDDRC_LPDDR2_CAL_MR4 0x2C /* MPDDRC LPDDR2 Calibration and MR4 Register */
+#define MPDDRC_LPDDR2_TIM_CAL 0x30 /* MPDDRC LPDDR2 Timing Calibration Register */
+#define MPDDRC_IO_CALIBR 0x34 /* MPDDRC IO Calibration */
+#define MPDDRC_OCMS 0x38 /* MPDDRC OCMS Register */
+#define MPDDRC_OCMS_KEY1 0x3C /* MPDDRC OCMS KEY1 Register */
+#define MPDDRC_OCMS_KEY2 0x40 /* MPDDRC OCMS KEY2 Register */
+/* 0x54 ~ 0x70 Reserved */
+#define MPDDRC_DLL_MOR 0x74 /* MPDDRC DLL Master Offset Register */
+#define MPDDRC_DLL_SOR 0x78 /* MPDDRC DLL Slave Offset Register */
+#define MPDDRC_DLL_MSR 0x7C /* MPDDRC DLL Master Status Register */
+#define MPDDRC_DLL_S0SR 0x80 /* MPDDRC DLL Slave 0 Status Register */
+#define MPDDRC_DLL_S1SR 0x84 /* MPDDRC DLL Slave 1 Status Register */
+
+#define MPDDRC_RD_DATA_PATH 0x5C /* MPDDRC Read Data Path */
+
+/* 0x94 ~ 0xE0 Reserved */
+#define HDDRSDRC2_WPCR 0xE4 /* Write Protect Mode Register */
+#define HDDRSDRC2_WPSR 0xE8 /* Write Protect Status Register */
+
+/* -------- HDDRSDRC2_MR : (HDDRSDRC2 Offset: 0x0) Mode Register --------*/
+#define AT91C_DDRC2_MODE (0x7UL << 0)
+#define AT91C_DDRC2_MODE_NORMAL_CMD (0x0UL)
+#define AT91C_DDRC2_MODE_NOP_CMD (0x1UL)
+#define AT91C_DDRC2_MODE_PRCGALL_CMD (0x2UL)
+#define AT91C_DDRC2_MODE_LMR_CMD (0x3UL)
+#define AT91C_DDRC2_MODE_RFSH_CMD (0x4UL)
+#define AT91C_DDRC2_MODE_EXT_LMR_CMD (0x5UL)
+#define AT91C_DDRC2_MODE_DEEP_CMD (0x6UL)
+#define AT91C_DDRC2_MODE_LPDDR2_CMD (0x7UL)
+#define AT91C_DDRC2_MRS(value) (value << 8)
+
+/* -------- HDDRSDRC2_RTR : (HDDRSDRC2 Offset: 0x4) Refresh Timer Register -------- */
+#define AT91C_DDRC2_COUNT (0xFFFUL << 0)
+
+/* -------- HDDRSDRC2_CR : (HDDRSDRC2 Offset: 0x8) Configuration Register --------*/
+#define AT91C_DDRC2_NC (0x3UL << 0)
+#define AT91C_DDRC2_NC_DDR9_SDR8 (0x0UL)
+#define AT91C_DDRC2_NC_DDR10_SDR9 (0x1UL)
+#define AT91C_DDRC2_NC_DDR11_SDR10 (0x2UL)
+#define AT91C_DDRC2_NC_DDR12_SDR11 (0x3UL)
+#define AT91C_DDRC2_NR (0x3UL << 2)
+#define AT91C_DDRC2_NR_11 (0x0UL << 2)
+#define AT91C_DDRC2_NR_12 (0x1UL << 2)
+#define AT91C_DDRC2_NR_13 (0x2UL << 2)
+#define AT91C_DDRC2_NR_14 (0x3UL << 2)
+#define AT91C_DDRC2_CAS (0x7UL << 4)
+#define AT91C_DDRC2_CAS_2 (0x2UL << 4)
+#define AT91C_DDRC2_CAS_3 (0x3UL << 4)
+#define AT91C_DDRC2_CAS_4 (0x4UL << 4)
+#define AT91C_DDRC2_CAS_5 (0x5UL << 4)
+#define AT91C_DDRC2_CAS_6 (0x6UL << 4)
+#define AT91C_DDRC2_RESET_DLL (0x1UL << 7)
+#define AT91C_DDRC2_DISABLE_RESET_DLL (0x0UL << 7)
+#define AT91C_DDRC2_ENABLE_RESET_DLL (0x1UL << 7)
+#define AT91C_DDRC2_DIC_DS (0x1UL << 8)
+#define AT91C_DDRC2_NORMAL_STRENGTH_RZQ6 (0x0UL << 8)
+#define AT91C_DDRC2_WEAK_STRENGTH_RZQ7 (0x1UL << 8)
+#define AT91C_DDRC2_DLL (0x1UL << 9)
+#define AT91C_DDRC2_ENABLE_DLL (0x0UL << 9)
+#define AT91C_DDRC2_DISABLE_DLL (0x1UL << 9)
+#define AT91C_DDRC2_ZQ (0x03 << 10)
+#define AT91C_DDRC2_ZQ_INIT (0x0 << 10)
+#define AT91C_DDRC2_ZQ_LONG (0x1 << 10)
+#define AT91C_DDRC2_ZQ_SHORT (0x2 << 10)
+#define AT91C_DDRC2_ZQ_RESET (0x3 << 10)
+#define AT91C_DDRC2_OCD (0x7UL << 12)
+#define AT91C_DDRC2_OCD_EXIT (0x0UL << 12)
+#define AT91C_DDRC2_OCD_DEFAULT (0x7UL << 12)
+#define AT91C_DDRC2_EBISHARE (0x1UL << 16)
+#define AT91C_DDRC2_DQMS (0x1UL << 16)
+#define AT91C_DDRC2_DQMS_NOT_SHARED (0x0UL << 16)
+#define AT91C_DDRC2_DQMS_SHARED (0x1UL << 16)
+#define AT91C_DDRC2_ENRDM (0x1UL << 17)
+#define AT91C_DDRC2_ENRDM_DISABLE (0x0UL << 17)
+#define AT91C_DDRC2_ENRDM_ENABLE (0x1UL << 17)
+#define AT91C_DDRC2_ACTBST (0x1UL << 18)
+#define AT91C_DDRC2_NB_BANKS (0x1UL << 20)
+#define AT91C_DDRC2_NB_BANKS_4 (0x0UL << 20)
+#define AT91C_DDRC2_NB_BANKS_8 (0x1UL << 20)
+#define AT91C_DDRC2_NDQS (0x1UL << 21) /* Not DQS(sama5d3x only) */
+#define AT91C_DDRC2_NDQS_ENABLED (0x0UL << 21)
+#define AT91C_DDRC2_NDQS_DISABLED (0x1UL << 21)
+#define AT91C_DDRC2_DECOD (0x1UL << 22)
+#define AT91C_DDRC2_DECOD_SEQUENTIAL (0x0UL << 22)
+#define AT91C_DDRC2_DECOD_INTERLEAVED (0x1UL << 22)
+#define AT91C_DDRC2_UNAL (0x1UL << 23) /* Support Unaligned Access(sama5d3x only) */
+#define AT91C_DDRC2_UNAL_UNSUPPORTED (0x0UL << 23)
+#define AT91C_DDRC2_UNAL_SUPPORTED (0x1UL << 23)
+
+/* -------- HDDRSDRC2_T0PR : (HDDRSDRC2 Offset: 0xc) Timing0 Register --------*/
+#define AT91C_DDRC2_TRAS (0xFUL << 0)
+#define AT91C_DDRC2_TRAS_(x) (x & 0x0f)
+#define AT91C_DDRC2_TRCD (0xFUL << 4)
+#define AT91C_DDRC2_TRCD_(x) ((x & 0x0f) << 4)
+#define AT91C_DDRC2_TWR (0xFUL << 8)
+#define AT91C_DDRC2_TWR_(x) ((x & 0x0f) << 8)
+#define AT91C_DDRC2_TRC (0xFUL << 12)
+#define AT91C_DDRC2_TRC_(x) ((x & 0x0f) << 12)
+#define AT91C_DDRC2_TRP (0xFUL << 16)
+#define AT91C_DDRC2_TRP_(x) ((x & 0x0f) << 16)
+#define AT91C_DDRC2_TRRD (0xFUL << 20)
+#define AT91C_DDRC2_TRRD_(x) ((x & 0x0f) << 20)
+#define AT91C_DDRC2_TWTR (0xFUL << 24)
+#define AT91C_DDRC2_TWTR_(x) ((x & 0x0f) << 24)
+#define AT91C_DDRC2_TMRD (0xFUL << 28)
+#define AT91C_DDRC2_TMRD_(x) ((x & 0x0f) << 28)
+
+/* -------- HDDRSDRC2_T1PR : (HDDRSDRC2 Offset: 0x10) Timing1 Register -------- */
+#define AT91C_DDRC2_TRFC (0x7FUL << 0)
+#define AT91C_DDRC2_TRFC_(x) (x & 0x7f)
+#define AT91C_DDRC2_TXSNR (0xFFUL << 8)
+#define AT91C_DDRC2_TXSNR_(x) ((x & 0xff) << 8)
+#define AT91C_DDRC2_TXSRD (0xFFUL << 16)
+#define AT91C_DDRC2_TXSRD_(x) ((x & 0xff) << 16)
+#define AT91C_DDRC2_TXP (0xFUL << 24)
+#define AT91C_DDRC2_TXP_(x) ((x & 0x0f) << 24)
+
+/* -------- HDDRSDRC2_T2PR : (HDDRSDRC2 Offset: 0x14) Timing2 Register --------*/
+#define AT91C_DDRC2_TXARD (0xFUL << 0)
+#define AT91C_DDRC2_TXARD_(x) (x & 0x0f)
+#define AT91C_DDRC2_TXARDS (0xFUL << 4)
+#define AT91C_DDRC2_TXARDS_(x) ((x & 0x0f) << 4)
+#define AT91C_DDRC2_TRPA (0xFUL << 8)
+#define AT91C_DDRC2_TRPA_(x) ((x & 0x0f) << 8)
+#define AT91C_DDRC2_TRT (0xFUL << 12)
+#define AT91C_DDRC2_TRTP_(x) ((x & 0x0f) << 12)
+#define AT91C_DDRC2_TFA (0xFUL << 16)
+#define AT91C_DDRC2_TFAW_(x) ((x & 0x0f) << 16)
+
+/* -------- HDDRSDRC2_LPR : (HDDRSDRC2 Offset: 0x1c) --------*/
+#define AT91C_DDRC2_LPCB (0x3UL << 0)
+#define AT91C_DDRC2_LPCB_DISABLED (0x0UL)
+#define AT91C_DDRC2_LPCB_SELFREFRESH (0x1UL)
+#define AT91C_DDRC2_LPCB_POWERDOWN (0x2UL)
+#define AT91C_DDRC2_LPCB_DEEP_PWD (0x3UL)
+#define AT91C_DDRC2_CLK_FR (0x1UL << 2)
+#define AT91C_DDRC2_PASR (0x7UL << 4)
+#define AT91C_DDRC2_PASR_(x) ((x & 0x7) << 4)
+#define AT91C_DDRC2_DS (0x7UL << 8)
+#define AT91C_DDRC2_DS_(x) ((x & 0x7) << 8)
+#define AT91C_DDRC2_TIMEOUT (0x3UL << 12)
+#define AT91C_DDRC2_TIMEOUT_0 (0x0UL << 12)
+#define AT91C_DDRC2_TIMEOUT_64 (0x1UL << 12)
+#define AT91C_DDRC2_TIMEOUT_128 (0x2UL << 12)
+#define AT91C_DDRC2_TIMEOUT_Reserved (0x3UL << 12)
+#define AT91C_DDRC2_ADPE (0x1UL << 16)
+#define AT91C_DDRC2_ADPE_FAST (0x0UL << 16)
+#define AT91C_DDRC2_ADPE_SLOW (0x1UL << 16)
+#define AT91C_DDRC2_UPD_MR (0x3UL << 20)
+#define AT91C_DDRC2_UPD_MR_NO_UPDATE (0x0UL << 20)
+#define AT91C_DDRC2_UPD_MR_SHARED_BUS (0x1UL << 20)
+#define AT91C_DDRC2_UPD_MR_NO_SHARED_BUS (0x2UL << 20)
+#define AT91C_DDRC2_SELF_DONE (0x1UL << 25)
+
+/* -------- HDDRSDRC2_MDR : (HDDRSDRC2 Offset: 0x20) Memory Device Register -------- */
+#define AT91C_DDRC2_MD (0x7UL << 0)
+#define AT91C_DDRC2_MD_SDR_SDRAM (0x0UL)
+#define AT91C_DDRC2_MD_LP_SDR_SDRAM (0x1UL)
+#define AT91C_DDRC2_MD_DDR_SDRAM (0x2UL)
+#define AT91C_DDRC2_MD_LP_DDR_SDRAM (0x3UL)
+#define AT91C_DDRC2_MD_DDR3_SDRAM (0x4UL)
+#define AT91C_DDRC2_MD_LPDDR3_SDRAM (0x5UL)
+#define AT91C_DDRC2_MD_DDR2_SDRAM (0x6UL)
+#define AT91C_DDRC2_MD_LPDDR2_SDRAM (0x7UL)
+#define AT91C_DDRC2_DBW (0x1UL << 4)
+#define AT91C_DDRC2_DBW_32_BITS (0x0UL << 4)
+#define AT91C_DDRC2_DBW_16_BITS (0x1UL << 4)
+
+/* -------- HDDRSDRC2_DLL : (HDDRSDRC2 Offset: 0x24) DLL Information Register --------*/
+#define AT91C_DDRC2_MDINC (0x1UL << 0)
+#define AT91C_DDRC2_MDDEC (0x1UL << 1)
+#define AT91C_DDRC2_MDOVF (0x1UL << 2)
+#define AT91C_DDRC2_MDVAL (0xFFUL << 8)
+
+/* ------- MPDDRC_LPDDR2_LPR (offset: 0x28) */
+#define AT91C_LPDDRC2_BK_MASK_PASR(value) (value << 0)
+#define AT91C_LPDDRC2_SEG_MASK(value) (value << 8)
+#define AT91C_LPDDRC2_DS(value) (value << 24)
+
+/* -------- HDDRSDRC2_HS : (HDDRSDRC2 Offset: 0x2c) High Speed Register --------*/
+#define AT91C_DDRC2_NO_ANT (0x1UL << 2)
+
+/* -------- MPDDRC_LPDDR2_CAL_MR4: (MPDDRC Offset: 0x2c) Calibration and MR4 Register --------*/
+#define AT91C_DDRC2_COUNT_CAL_MASK (0xFFFFUL)
+#define AT91C_DDRC2_COUNT_CAL(value) (((value) & AT91C_DDRC2_COUNT_CAL_MASK) << 0)
+
+/* -------- MPDDRC_LPDDR2_TIM_CAL : (MPDDRC Offset: 0x30) */
+#define AT91C_DDRC2_ZQCS(value) (value << 0)
+
+/* -------- MPDDRC_IO_CALIBR : (MPDDRC Offset: 0x34) IO Calibration --------*/
+#define AT91C_MPDDRC_RDIV (0x7UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_34 (0x1UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_48 (0x3UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_60 (0x4UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR2_RZQ_120 (0x7UL << 0)
+
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_33_3 (0x2UL << 0)
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_50 (0x4UL << 0)
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_66_7 (0x6UL << 0)
+#define AT91C_MPDDRC_RDIV_DDR2_RZQ_100 (0x7UL << 0)
+
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_38 (0x02UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_46 (0x03UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_57 (0x04UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_77 (0x06UL << 0)
+#define AT91C_MPDDRC_RDIV_LPDDR3_RZQ_115 (0x07UL << 0)
+
+#define AT91C_MPDDRC_ENABLE_CALIB (0x01 << 4)
+#define AT91C_MPDDRC_DISABLE_CALIB (0x00 << 4)
+#define AT91C_MPDDRC_EN_CALIB (0x01 << 4)
+
+#define AT91C_MPDDRC_TZQIO (0x7FUL << 8)
+#define AT91C_MPDDRC_TZQIO_(x) ((x) << 8)
+#define AT91C_MPDDRC_TZQIO_0 (0x0UL << 8)
+#define AT91C_MPDDRC_TZQIO_1 (0x1UL << 8)
+#define AT91C_MPDDRC_TZQIO_3 (0x3UL << 8)
+#define AT91C_MPDDRC_TZQIO_4 (0x4UL << 8)
+#define AT91C_MPDDRC_TZQIO_5 (0x5UL << 8)
+#define AT91C_MPDDRC_TZQIO_31 (0x1FUL << 8)
+
+#define AT91C_MPDDRC_CALCODEP (0xFUL << 16)
+#define AT91C_MPDDRC_CALCODEP_(x) ((x) << 16)
+
+#define AT91C_MPDDRC_CALCODEN (0xFUL << 20)
+#define AT91C_MPDDRC_CALCODEN_(x) ((x) << 20)
+
+/* ---- MPDDRC_RD_DATA_PATH : (MPDDRC Offset: 0x5c) MPDDRC Read Data Path */
+#define AT91_MPDDRC_SHIFT_SAMPLING (0x03 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_NO_SHIFT (0x00 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_ONE_CYCLES (0x01 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_TWO_CYCLES (0x02 << 0)
+#define AT91C_MPDDRC_RD_DATA_PATH_THREE_CYCLES (0x03 << 0)
+
+/* -------- MPDDRC_DLL_MOR : (MPDDRC Offset: 0x74) DLL Master Offset Register --------*/
+#define AT91C_MPDDRC_MOFF(value) (value << 0)
+#define AT91C_MPDDRC_MOFF_1 (0x1UL << 0)
+#define AT91C_MPDDRC_MOFF_7 (0x7UL << 0)
+#define AT91C_MPDDRC_CLK90OFF(value) (value << 8)
+#define AT91C_MPDDRC_CLK90OFF_1 (0x1UL << 8)
+#define AT91C_MPDDRC_CLK90OFF_31 (0x1FUL << 8)
+#define AT91C_MPDDRC_SELOFF (0x1UL << 16)
+#define AT91C_MPDDRC_SELOFF_DISABLED (0x0UL << 16)
+#define AT91C_MPDDRC_SELOFF_ENABLED (0x1UL << 16)
+#define AT91C_MPDDRC_KEY (0xC5UL << 24)
+
+/* -------- MPDDRC_DLL_SOR : (MPDDRC Offset: 0x78) DLL Slave Offset Register --------*/
+#define AT91C_MPDDRC_S0OFF_1 (0x1UL << 0)
+#define AT91C_MPDDRC_S1OFF_1 (0x1UL << 8)
+#define AT91C_MPDDRC_S2OFF_1 (0x1UL << 16)
+#define AT91C_MPDDRC_S3OFF_1 (0x1UL << 24)
+
+#define AT91C_MPDDRC_S0OFF(value) (value << 0)
+#define AT91C_MPDDRC_S1OFF(value) (value << 8)
+#define AT91C_MPDDRC_S2OFF(value) (value << 16)
+#define AT91C_MPDDRC_S3OFF(value) (value << 24)
+
+/* -------- HDDRSDRC2_WPCR : (HDDRSDRC2 Offset: 0xe4) Write Protect Control Register --------*/
+#define AT91C_DDRC2_WPEN (0x1UL << 0)
+#define AT91C_DDRC2_WPKEY (0xFFFFFFUL << 8)
+
+/* -------- HDDRSDRC2_WPSR : (HDDRSDRC2 Offset: 0xe8) Write Protect Status Register --------*/
+#define AT91C_DDRC2_WPVS (0x1UL << 0)
+#define AT91C_DDRC2_WPSRC (0xFFFFUL << 8)
+
+/*
+ * Header file for the Atmel DDR/SDR SDRAM Controller
+ *
+ * Copyright (C) 2010 Atmel Corporation
+ * Nicolas Ferre <nicolas.ferre@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __ASSEMBLY__
+#include <common.h>
+#include <io.h>
+
+static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
+{
+ u32 cr;
+ u32 mdr;
+ u32 size;
+ bool is_sdram;
+
+ cr = __raw_readl(base + HDDRSDRC2_CR);
+ mdr = __raw_readl(base + HDDRSDRC2_MDR);
+
+ is_sdram = (mdr & AT91C_DDRC2_MD) <= AT91C_DDRC2_MD_LP_SDR_SDRAM;
+
+ /* Formula:
+ * size = bank << (col + row + 1);
+ * if (bandwidth == 32 bits)
+ * size <<= 1;
+ */
+ size = 1;
+ /* COL */
+ size += (cr & AT91C_DDRC2_NC) + 8;
+ if (!is_sdram)
+ size ++;
+ /* ROW */
+ size += ((cr & AT91C_DDRC2_NR) >> 2) + 11;
+ /* BANK */
+ if (is_nb)
+ size = ((cr & AT91C_DDRC2_NB_BANKS) ? 8 : 4) << size;
+ else
+ size = 4 << size;
+
+ /* bandwidth */
+ if (!(mdr & AT91C_DDRC2_DBW))
+ size <<= 1;
+
+ return size;
+}
+
+#ifdef CONFIG_SOC_AT91SAM9G45
+#include <mach/at91sam9g45.h>
+static inline u32 at91sam9g45_get_ddram_size(int bank)
+{
+ switch (bank) {
+ case 0:
+ return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false);
+ case 1:
+ return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false);
+ default:
+ return 0;
+ }
+}
+#else
+static inline u32 at91sam9g45_get_ddram_size(int bank)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SOC_AT91SAM9X5
+#include <mach/at91sam9x5.h>
+static inline u32 at91sam9x5_get_ddram_size(void)
+{
+ return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true);
+}
+#else
+static inline u32 at91sam9x5_get_ddram_size(void)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SOC_AT91SAM9N12
+#include <mach/at91sam9n12.h>
+static inline u32 at91sam9n12_get_ddram_size(void)
+{
+ return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true);
+}
+#else
+static inline u32 at91sam9n12_get_ddram_size(void)
+{
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_SOC_SAMA5
+#include <mach/sama5d3.h>
+static inline u32 at91sama5_get_ddram_size(void)
+{
+ u32 cr;
+ u32 mdr;
+ u32 size;
+ void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC);
+
+ cr = __raw_readl(base + HDDRSDRC2_CR);
+ mdr = __raw_readl(base + HDDRSDRC2_MDR);
+
+ /* Formula:
+ * size = bank << (col + row + 1);
+ * if (bandwidth == 32 bits)
+ * size <<= 1;
+ */
+ size = 1;
+ /* COL */
+ size += (cr & AT91C_DDRC2_NC) + 9;
+ /* ROW */
+ size += ((cr & AT91C_DDRC2_NR) >> 2) + 11;
+ /* BANK */
+ size = ((cr & AT91C_DDRC2_NB_BANKS) ? 8 : 4) << size;
+
+ /* bandwidth */
+ if (!(mdr & AT91C_DDRC2_DBW))
+ size <<= 1;
+
+ return size;
+}
+#else
+static inline u32 at91sama5_get_ddram_size(void)
+{
+ return 0;
+}
+#endif
+
+#endif
+#endif /* #ifndef __AT91_DDRSDRC_H__ */
diff --git a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h b/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
deleted file mode 100644
index 1c4d313eb486..000000000000
--- a/arch/arm/mach-at91/include/mach/at91sam9_ddrsdr.h
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * Header file for the Atmel DDR/SDR SDRAM Controller
- *
- * Copyright (C) 2010 Atmel Corporation
- * Nicolas Ferre <nicolas.ferre@atmel.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-#ifndef AT91SAM9_DDRSDR_H
-#define AT91SAM9_DDRSDR_H
-
-#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
-#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
-#define AT91_DDRSDRC_MODE_NORMAL 0
-#define AT91_DDRSDRC_MODE_NOP 1
-#define AT91_DDRSDRC_MODE_PRECHARGE 2
-#define AT91_DDRSDRC_MODE_LMR 3
-#define AT91_DDRSDRC_MODE_REFRESH 4
-#define AT91_DDRSDRC_MODE_EXT_LMR 5
-#define AT91_DDRSDRC_MODE_DEEP 6
-
-#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
-#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
-
-#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
-#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
-#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
-#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
-#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
-#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
-#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
-#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
-#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
-#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
-#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
-#define AT91_DDRSDRC_NR_11 (0 << 2)
-#define AT91_DDRSDRC_NR_12 (1 << 2)
-#define AT91_DDRSDRC_NR_13 (2 << 2)
-#define AT91_DDRSDRC_NR_14 (3 << 2)
-#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
-#define AT91_DDRSDRC_CAS_2 (2 << 4)
-#define AT91_DDRSDRC_CAS_3 (3 << 4)
-#define AT91_DDRSDRC_CAS_25 (6 << 4)
-#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
-#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
-#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
-#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
-#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
-#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
-#define AT91_DDRSDRC_NB (1 << 20) /* Number of
-Banks [not SAM9G45] */
-#define AT91_SDRAMC_NB_4 (0 << 20)
-#define AT91_SDRAMC_NB_8 (1 << 20)
-
-#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
-#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
-#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
-#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
-#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
-#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
-#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
-#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
-#define AT91CAP9_DDRSDRC_TWTR (1 << 24) /* Internal Write to Read delay */
-#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
-#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
-
-#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
-#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
-#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
-#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
-#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
-
-#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
-#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
-#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
-#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
-#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
-
-#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
-#define AT91CAP9_DDRSDRC_LPR 0x18 /* Low Power Register */
-#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
-#define AT91_DDRSDRC_LPCB_DISABLE 0
-#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
-#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
-#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
-#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
-#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
-#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
-#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
-#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
-#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
-#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
-#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
-#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
-#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
-
-#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
-#define AT91CAP9_DDRSDRC_MDR 0x1C /* Memory Device Register */
-#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
-#define AT91_DDRSDRC_MD_SDR 0
-#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
-#define AT91CAP9_DDRSDRC_MD_DDR 2
-#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
-#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
-#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
-#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
-#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
-
-#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
-#define AT91CAP9_DDRSDRC_DLL 0x20 /* DLL Information Register */
-#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
-#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
-#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
-#define AT91CAP9_DDRSDRC_SDCOVF (1 << 3) /* Slave Delay Correction Overflow */
-#define AT91CAP9_DDRSDRC_SDCUDF (1 << 4) /* Slave Delay Correction Underflow */
-#define AT91CAP9_DDRSDRC_SDERF (1 << 5) /* Slave Delay Correction error */
-#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
-#define AT91CAP9_DDRSDRC_SDVAL (0xff << 16) /* Slave Delay value */
-#define AT91CAP9_DDRSDRC_SDCVAL (0xff << 24) /* Slave Delay Correction value */
-
-#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
-#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
-
-#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
-
-#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
-#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
-#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
-#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
-
-#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
-#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
-#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
-
-#ifndef __ASSEMBLY__
-#include <io.h>
-
-static inline u32 at91_get_ddram_size(void * __iomem base, bool is_nb)
-{
- u32 cr;
- u32 mdr;
- u32 size;
- bool is_sdram;
-
- cr = __raw_readl(base + AT91_DDRSDRC_CR);
- mdr = __raw_readl(base + AT91_DDRSDRC_MDR);
-
- is_sdram = (mdr & AT91_DDRSDRC_MD) <= AT91_DDRSDRC_MD_LOW_POWER_SDR;
-
- /* Formula:
- * size = bank << (col + row + 1);
- * if (bandwidth == 32 bits)
- * size <<= 1;
- */
- size = 1;
- /* COL */
- size += (cr & AT91_DDRSDRC_NC) + 8;
- if (!is_sdram)
- size ++;
- /* ROW */
- size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11;
- /* BANK */
- if (is_nb)
- size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size;
- else
- size = 4 << size;
-
- /* bandwidth */
- if (!(mdr & AT91_DDRSDRC_DBW))
- size <<= 1;
-
- return size;
-}
-
-#ifdef CONFIG_SOC_AT91SAM9G45
-#include <mach/at91sam9g45.h>
-static inline u32 at91sam9g45_get_ddram_size(int bank)
-{
- switch (bank) {
- case 0:
- return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC0), false);
- case 1:
- return at91_get_ddram_size(IOMEM(AT91SAM9G45_BASE_DDRSDRC1), false);
- default:
- return 0;
- }
-}
-#else
-static inline u32 at91sam9g45_get_ddram_size(int bank)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9X5
-#include <mach/at91sam9x5.h>
-static inline u32 at91sam9x5_get_ddram_size(void)
-{
- return at91_get_ddram_size(IOMEM(AT91SAM9X5_BASE_DDRSDRC0), true);
-}
-#else
-static inline u32 at91sam9x5_get_ddram_size(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SOC_AT91SAM9N12
-#include <mach/at91sam9n12.h>
-static inline u32 at91sam9n12_get_ddram_size(void)
-{
- return at91_get_ddram_size(IOMEM(AT91SAM9N12_BASE_DDRSDRC0), true);
-}
-#else
-static inline u32 at91sam9n12_get_ddram_size(void)
-{
- return 0;
-}
-#endif
-
-#ifdef CONFIG_SOC_SAMA5
-#include <mach/sama5d3.h>
-static inline u32 at91sama5_get_ddram_size(void)
-{
- u32 cr;
- u32 mdr;
- u32 size;
- void * __iomem base = IOMEM(SAMA5D3_BASE_MPDDRC);
-
- cr = __raw_readl(base + AT91_DDRSDRC_CR);
- mdr = __raw_readl(base + AT91_DDRSDRC_MDR);
-
- /* Formula:
- * size = bank << (col + row + 1);
- * if (bandwidth == 32 bits)
- * size <<= 1;
- */
- size = 1;
- /* COL */
- size += (cr & AT91_DDRSDRC_NC) + 9;
- /* ROW */
- size += ((cr & AT91_DDRSDRC_NR) >> 2) + 11;
- /* BANK */
- size = ((cr & AT91_DDRSDRC_NB) ? 8 : 4) << size;
-
- /* bandwidth */
- if (!(mdr & AT91_DDRSDRC_DBW))
- size <<= 1;
-
- return size;
-}
-#else
-static inline u32 at91sama5_get_ddram_size(void)
-{
- return 0;
-}
-#endif
-
-#endif
-
-#endif
diff --git a/arch/arm/mach-at91/sama5d3_devices.c b/arch/arm/mach-at91/sama5d3_devices.c
index f5075b39374f..f6d5e47c33ed 100644
--- a/arch/arm/mach-at91/sama5d3_devices.c
+++ b/arch/arm/mach-at91/sama5d3_devices.c
@@ -18,7 +18,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
diff --git a/arch/arm/mach-at91/sama5d4_devices.c b/arch/arm/mach-at91/sama5d4_devices.c
index 4064e4441f9f..f5c0367ca844 100644
--- a/arch/arm/mach-at91/sama5d4_devices.c
+++ b/arch/arm/mach-at91/sama5d4_devices.c
@@ -19,7 +19,7 @@
#include <mach/board.h>
#include <mach/at91_pmc.h>
#include <mach/at91sam9x5_matrix.h>
-#include <mach/at91sam9_ddrsdr.h>
+#include <mach/at91_ddrsdrc.h>
#include <mach/iomux.h>
#include <mach/cpu.h>
#include <i2c/i2c-gpio.h>
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 03/11] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's
2019-01-16 17:45 ` [PATCH 03/11] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's Ahmad Fatoum
@ 2019-01-16 18:24 ` Sam Ravnborg
2019-01-17 9:28 ` Ahmad Fatoum
0 siblings, 1 reply; 20+ messages in thread
From: Sam Ravnborg @ 2019-01-16 18:24 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Wed, Jan 16, 2019 at 06:45:51PM +0100, Ahmad Fatoum wrote:
> Only at91sam9g45_reset.S and the header itself actually use
> any of the macros defined within.
>
> Instead of adding missing definitions and adapting the incoming DDRAMC
> initialization code from at91bootstrap, just include the at91_ddrsdrc.h
> header wholesale.
This seems to go in the opposite direction
of what we did in for example this commit:
eaa7fcf934826d519f532227c304c09a62cfe685 ("ARM: at91: Add SoC namespace to matrix defines")
It adds a lot of defines that are not prefixed with SOC names,
so asking for conflicts.
Also the patch was a little hard to follow with several types of
changes in one patch.
(Adding files, replacing header files, deleting files)
Sam
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 03/11] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's
2019-01-16 18:24 ` Sam Ravnborg
@ 2019-01-17 9:28 ` Ahmad Fatoum
0 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-17 9:28 UTC (permalink / raw)
To: Sam Ravnborg; +Cc: barebox
Hello Sam,
On 16/1/19 19:24, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Wed, Jan 16, 2019 at 06:45:51PM +0100, Ahmad Fatoum wrote:
>> Only at91sam9g45_reset.S and the header itself actually use
>> any of the macros defined within.
>>
>> Instead of adding missing definitions and adapting the incoming DDRAMC
>> initialization code from at91bootstrap, just include the at91_ddrsdrc.h
>> header wholesale.
>
> This seems to go in the opposite direction
> of what we did in for example this commit:
> eaa7fcf934826d519f532227c304c09a62cfe685 ("ARM: at91: Add SoC namespace to matrix defines")
>
> It adds a lot of defines that are not prefixed with SOC names,
> so asking for conflicts.
You refer to the {HDDRSDRC2,MPDDRC}_* ones?
I'll prefix those in v2.
>
> Also the patch was a little hard to follow with several types of
> changes in one patch.
> (Adding files, replacing header files, deleting files)
Will split it for v2.
>
> Sam
>
Thanks
Ahmad
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 04/11] ARM: at91: watchdog: implement at91_wdt_disable
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (2 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 03/11] ARM: at91: replace at91sam9_ddrsdr.h with at91bootstrap's Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 05/11] ARM: at91: import lowlevel clock initialization from at91bootstrap Ahmad Fatoum
` (7 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
Low level init code might want to disable the watchdog in PBL.
Provide a helper to do so.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91_wdt.h | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/mach-at91/include/mach/at91_wdt.h b/arch/arm/mach-at91/include/mach/at91_wdt.h
index 36d37b9d2d64..ecb50edc8c70 100644
--- a/arch/arm/mach-at91/include/mach/at91_wdt.h
+++ b/arch/arm/mach-at91/include/mach/at91_wdt.h
@@ -35,4 +35,20 @@
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
+#ifndef __ASSEMBLY__
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <asm-generic/io.h>
+
+static inline void at91_wdt_disable(void __iomem *wdt_base)
+{
+ u32 reg = __raw_readl(wdt_base + AT91_WDT_MR);
+ reg |= AT91_WDT_WDDIS;
+ __raw_writel(reg, wdt_base + AT91_WDT_MR);
+}
+
+#endif /* __ASSEMBLY__ */
#endif
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 05/11] ARM: at91: import lowlevel clock initialization from at91bootstrap
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (3 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 04/11] ARM: at91: watchdog: implement at91_wdt_disable Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 06/11] ARM: at91: import early_udelay " Ahmad Fatoum
` (6 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
For use by future at91 first stage bootloaders, this commit imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/pmc.c
to do the low level clock initialization.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Makefile | 1 +
.../include/mach/at91_lowlevel_clock.h | 30 ++++
arch/arm/mach-at91/include/mach/at91_pmc.h | 5 +-
arch/arm/mach-at91/lowlevel_clock.c | 164 ++++++++++++++++++
4 files changed, 199 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-at91/include/mach/at91_lowlevel_clock.h
create mode 100644 arch/arm/mach-at91/lowlevel_clock.c
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index d81683ac121a..7c4c58b080a1 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,4 +1,5 @@
obj-y += setup.o
+pbl-y += lowlevel_clock.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/include/mach/at91_lowlevel_clock.h b/arch/arm/mach-at91/include/mach/at91_lowlevel_clock.h
new file mode 100644
index 000000000000..5b32cfdc69bf
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/at91_lowlevel_clock.h
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#ifndef AT91_LOWLEVEL_CLOCK_H
+#define AT91_LOWLEVEL_CLOCK_H
+
+#include <errno.h>
+#include <asm/io.h>
+#include <mach/at91_pmc.h>
+
+void at91_lowlevel_clock_init(void __iomem *pmc_base);
+void at91_pmc_cfg_mck(void __iomem *pmc_base, unsigned int pmc_mckr);
+static inline int at91_pmc_enable_periph_clock(void __iomem *pmc_base,
+ unsigned periph_id)
+{
+ u32 mask = 0x01 << (periph_id % 32);
+
+ if ((periph_id / 32) == 1)
+ __raw_writel(mask, pmc_base + AT91_PMC_PCER1);
+ else if ((periph_id / 32) == 0)
+ __raw_writel(mask, pmc_base + AT91_PMC_PCER);
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+#endif
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index bbbd497afaed..0f13e4f4d391 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -50,7 +50,9 @@
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
-#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
+#define AT91_PMC_OSCOUNT_(x) ((x) << 8)
+#define AT91_PMC_KEY_MASK (0xff << 16) /* MOR Writing Key */
+#define AT91_PMC_KEY (0x37 << 16)
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
@@ -133,6 +135,7 @@
#define AT91_PMC_CSSMCK_MCK (1 << 8)
#define AT91_PMC_IER 0x60 /* Interrupt Enable Register */
+#define AT91_PMC_MOSCXTS (1 << 0) /* Oscillator Startup Time */
#define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */
#define AT91_PMC_SR 0x68 /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
diff --git a/arch/arm/mach-at91/lowlevel_clock.c b/arch/arm/mach-at91/lowlevel_clock.c
new file mode 100644
index 000000000000..c974409a99fc
--- /dev/null
+++ b/arch/arm/mach-at91/lowlevel_clock.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+
+#include <common.h>
+#include <mach/at91_lowlevel_clock.h>
+#include <mach/at91_pmc.h>
+
+#define at91_pmc_write(off, val) writel(val, pmc_base + off)
+#define at91_pmc_read(off) readl(pmc_base + off)
+
+void at91_lowlevel_clock_init(void __iomem *pmc_base)
+{
+ unsigned long tmp;
+
+ /*
+ * Switch the master clock to the slow clock without modifying other
+ * parameters. It is assumed that ROM code set H32MXDIV, PLLADIV2,
+ * PCK_DIV3.
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= AT91_PMC_CSS_SLOW;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+
+ if (IS_ENABLED(CONFIG_SOC_AT91SAM9X5) || IS_ENABLED(CONFIG_SOC_AT91SAM9N12)
+ || IS_ENABLED(CONFIG_SOC_SAMA5)) {
+ /*
+ * Enable the Main Crystal Oscillator
+ * tST_max = 2ms
+ * Startup Time: 32768 * 2ms / 8 = 8
+ */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCOUNT;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_MOSCEN;
+ tmp |= AT91_PMC_OSCOUNT_(8);
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCS))
+ ;
+
+ /* Switch from internal 12MHz RC to the Main Cristal Oscillator */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCBYPASS;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp |= AT91_PMC_MOSCSEL;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCSELS))
+ ;
+
+ if (!IS_ENABLED(CONFIG_ARCH_SAMA5D4)) {
+ /* Disable the 12MHz RC Oscillator */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_MOSCRCEN;
+ tmp &= ~AT91_PMC_KEY_MASK;
+ tmp |= AT91_PMC_KEY;
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+ }
+
+ } else {
+ /*
+ * Enable the Main Crystal Oscillator
+ * tST_max = 2ms
+ * Startup Time: 32768 * 2ms / 8 = 8
+ */
+ tmp = at91_pmc_read(AT91_CKGR_MOR);
+ tmp &= ~AT91_PMC_OSCOUNT;
+ tmp |= AT91_PMC_MOSCEN;
+ tmp |= AT91_PMC_OSCOUNT_(8);
+ at91_pmc_write(AT91_CKGR_MOR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MOSCXTS))
+ ;
+ }
+
+ /* After stablization, switch to Main Clock */
+ if ((at91_pmc_read(AT91_PMC_MCKR) & AT91_PMC_ALT_PCKR_CSS) == AT91_PMC_CSS_SLOW) {
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~(0x1 << 13);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= AT91_PMC_CSS_MAIN;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+
+ tmp &= ~AT91_PMC_PRES;
+ tmp |= AT91_PMC_PRES_1;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+ }
+}
+
+void at91_pmc_cfg_mck(void __iomem *pmc_base, unsigned int pmc_mckr)
+{
+ u32 tmp;
+
+ /*
+ * Program the PRES field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~(0x1 << 13);
+ if (IS_ENABLED(CONFIG_SOC_AT91SAM9X5)
+ || IS_ENABLED(CONFIG_SOC_AT91SAM9N12)
+ || IS_ENABLED(CONFIG_SOC_SAMA5)) {
+ tmp &= ~AT91_PMC_ALT_PRES;
+ tmp |= pmc_mckr & AT91_PMC_ALT_PRES;
+ } else {
+ tmp &= ~AT91_PMC_PRES;
+ tmp |= pmc_mckr & AT91_PMC_PRES;
+ }
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the MDIV field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_MDIV;
+ tmp |= pmc_mckr & AT91_PMC_MDIV;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the PLLADIV2 field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_PLLADIV2;
+ tmp |= pmc_mckr & AT91_PMC_PLLADIV2;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the H32MXDIV field in the AT91_PMC_MCKR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_H32MXDIV;
+ tmp |= pmc_mckr & AT91_PMC_H32MXDIV;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ /*
+ * Program the CSS field in the AT91_PMC_MCKR register,
+ * wait for MCKRDY bit to be set in the PMC_SR register
+ */
+ tmp = at91_pmc_read(AT91_PMC_MCKR);
+ tmp &= ~AT91_PMC_ALT_PCKR_CSS;
+ tmp |= pmc_mckr & AT91_PMC_ALT_PCKR_CSS;
+ at91_pmc_write(AT91_PMC_MCKR, tmp);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_MCKRDY))
+ ;
+}
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 06/11] ARM: at91: import early_udelay from at91bootstrap
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (4 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 05/11] ARM: at91: import lowlevel clock initialization from at91bootstrap Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 07/11] ARM: at91: import low level DDRAMC initialization code " Ahmad Fatoum
` (5 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
For use by the incoming at91bootstrap DDRAMC initialization code,
this commit provides an early_udelay function usable in PBL imported from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_pit.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Kconfig | 4 ++
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/early_udelay.c | 61 +++++++++++++++++++
.../arm/mach-at91/include/mach/early_udelay.h | 13 ++++
4 files changed, 79 insertions(+)
create mode 100644 arch/arm/mach-at91/early_udelay.c
create mode 100644 arch/arm/mach-at91/include/mach/early_udelay.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 63e6e7285931..98d18c8b26db 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -15,6 +15,9 @@ config HAVE_AT91_UTMI
config HAVE_AT91_USB_CLK
bool
+config HAVE_AT91_H32MXDIV
+ bool
+
config COMMON_CLK_AT91
bool
select COMMON_CLK
@@ -196,6 +199,7 @@ config ARCH_SAMA5D4
select HAVE_AT91_DBGU2
select HAS_MACB
select HAVE_MACH_ARM_HEAD
+ select HAVE_AT91_H32MXDIV
endchoice
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 7c4c58b080a1..b8ff6428d05a 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,5 +1,6 @@
obj-y += setup.o
pbl-y += lowlevel_clock.o
+pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/early_udelay.c b/arch/arm/mach-at91/early_udelay.c
new file mode 100644
index 000000000000..b25b5d558833
--- /dev/null
+++ b/arch/arm/mach-at91/early_udelay.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2012, Atmel Corporation
+ */
+
+#include <mach/hardware.h>
+#include <asm/io.h>
+#include <mach/at91_lowlevel_clock.h>
+#include <mach/at91_pit.h>
+#include <mach/early_udelay.h>
+
+static unsigned int master_clock;
+static void __iomem *pmc, *pit;
+
+static bool pmc_check_mck_h32mxdiv(void)
+{
+ if (IS_ENABLED(CONFIG_HAVE_AT91_H32MXDIV))
+ return __raw_readl(pmc + AT91_PMC_MCKR) & AT91_PMC_H32MXDIV;
+
+ return false;
+}
+
+/* Because the below statement is used in the function:
+ * ((MASTER_CLOCK >> 10) * usec) is used,
+ * to our 32-bit system. the argu "usec" maximum value is:
+ * supposed "MASTER_CLOCK" is 132M.
+ * 132000000 / 1024 = 128906
+ * (0xffffffff) / 128906 = 33318.
+ * So the maximum delay time is 33318 us.
+ */
+/* requires PIT to be initialized, but not the clocksource framework */
+void early_udelay(unsigned int usec)
+{
+ unsigned int delay;
+ unsigned int current;
+ unsigned int base = __raw_readl(pit + AT91_PIT_PIIR);
+
+ if (pmc_check_mck_h32mxdiv())
+ master_clock /= 2;
+
+ delay = ((master_clock >> 10) * usec) >> 14;
+
+ do {
+ current = __raw_readl(pit + AT91_PIT_PIIR);
+ current -= base;
+ } while (current < delay);
+}
+
+void early_udelay_init(void __iomem *pmc_base,
+ void __iomem *pit_base,
+ unsigned clock,
+ unsigned int master_clock_rate)
+{
+ master_clock = master_clock_rate;
+ pmc = pmc_base;
+ pit = pit_base;
+
+ __raw_writel(AT91_PIT_PIV | AT91_PIT_PITEN, pit + AT91_PIT_MR);
+
+ at91_pmc_enable_periph_clock(pmc_base, clock);
+}
diff --git a/arch/arm/mach-at91/include/mach/early_udelay.h b/arch/arm/mach-at91/include/mach/early_udelay.h
new file mode 100644
index 000000000000..120b586310f0
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/early_udelay.h
@@ -0,0 +1,13 @@
+#ifndef __EARLY_UDELAY_H__
+#define __EARLY_UDELAY_H__
+
+#include <linux/compiler.h>
+
+/* requires PIT to be initialized, but not the clocksource framework */
+void early_udelay(unsigned int usec);
+void early_udelay_init(void __iomem *pmc_base,
+ void __iomem *pit_base,
+ unsigned clock,
+ unsigned int master_clock_rate);
+
+#endif
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 07/11] ARM: at91: import low level DDRAMC initialization code from at91bootstrap
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (5 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 06/11] ARM: at91: import early_udelay " Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-17 8:11 ` Sascha Hauer
2019-01-16 17:45 ` [PATCH 08/11] ARM: at91: import lowlevel dbgu UART init " Ahmad Fatoum
` (4 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
This commit imports DDRAMC initialization routines for use in PBL from
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Makefile | 1 +
arch/arm/mach-at91/ddramc.c | 518 +++++++++++++++++++++++
arch/arm/mach-at91/include/mach/ddramc.h | 35 ++
3 files changed, 554 insertions(+)
create mode 100644 arch/arm/mach-at91/ddramc.c
create mode 100644 arch/arm/mach-at91/include/mach/ddramc.h
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index b8ff6428d05a..ac88f83f9fe5 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -1,6 +1,7 @@
obj-y += setup.o
pbl-y += lowlevel_clock.o
pbl-$(CONFIG_CLOCKSOURCE_ATMEL_PIT) += early_udelay.o
+pbl-y += ddramc.o
ifeq ($(CONFIG_COMMON_CLK_OF_PROVIDER),)
obj-y += clock.o
diff --git a/arch/arm/mach-at91/ddramc.c b/arch/arm/mach-at91/ddramc.c
new file mode 100644
index 000000000000..837711345bbf
--- /dev/null
+++ b/arch/arm/mach-at91/ddramc.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2007, Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Copyright (c) 2007 Lead Tech Design <www.leadtechdesign.com>
+ */
+
+#include <linux/kconfig.h>
+#include <asm/system.h>
+#include <mach/at91_ddrsdrc.h>
+#include <mach/ddramc.h>
+#include <mach/early_udelay.h>
+
+static bool ddramc_decodtype_is_seq(unsigned long ddramc_cr)
+{
+ if (IS_ENABLED(CONFIG_SOC_AT91SAM9X5) || IS_ENABLED(CONFIG_SOC_AT91SAM9N12)
+ || IS_ENABLED(CONFIG_SOC_SAMA5)) {
+ if (ddramc_cr & AT91C_DDRC2_DECOD_INTERLEAVED)
+ return false;
+ }
+ return true;
+}
+
+
+void ddram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct ddramc_register *ddramc_config)
+{
+ unsigned long ba_offset;
+ unsigned long cr = 0;
+
+ /* compute BA[] offset according to CR configuration */
+ ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 9;
+ if (ddramc_decodtype_is_seq(ddramc_config->cr))
+ ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
+
+ ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
+
+ /*
+ * Step 1: Program the memory device type into the Memory Device Register
+ */
+ __raw_writel(ddramc_config->mdr, base_address + HDDRSDRC2_MDR);
+
+ /*
+ * Step 2: Program the feature of DDR2-SDRAM device into
+ * the Timing Register, and into the Configuration Register
+ */
+ __raw_writel(ddramc_config->cr, base_address + HDDRSDRC2_CR);
+
+ __raw_writel(ddramc_config->t0pr, base_address + HDDRSDRC2_T0PR);
+ __raw_writel(ddramc_config->t1pr, base_address + HDDRSDRC2_T1PR);
+ __raw_writel(ddramc_config->t2pr, base_address + HDDRSDRC2_T2PR);
+
+ /*
+ * Step 3: An NOP command is issued to the DDR2-SDRAM
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+ /* Now, clocks which drive the DDR2-SDRAM device are enabled */
+
+ /* A minimum pause wait 200 us is provided to precede any signal toggle.
+ (6 core cycles per iteration, core is at 396MHz: min 13340 loops) */
+ early_udelay(200);
+
+ /*
+ * Step 4: An NOP command is issued to the DDR2-SDRAM
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+ /* Now, CKE is driven high */
+ /* wait 400 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 5: An all banks precharge command is issued to the DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 6: An Extended Mode Register set(EMRS2) cycle is issued to chose between commercial or high
+ * temperature operations.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 0.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x2 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 7: An Extended Mode Register set(EMRS3) cycle is issued
+ * to set the Extended Mode Register to "0".
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 1 and BA[0] is set to 1.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x3 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 8: An Extened Mode Register set(EMRS1) cycle is issued to enable DLL,
+ * and to program D.I.C(Output Driver Impedance Control)
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x1 << ba_offset));
+
+ /* An additional 200 cycles of clock are required for locking DLL */
+ early_udelay(1);
+
+ /*
+ * Step 9: Program DLL field into the Configuration Register to high(Enable DLL reset)
+ */
+ cr = __raw_readl(base_address + HDDRSDRC2_CR);
+ __raw_writel(cr | AT91C_DDRC2_ENABLE_RESET_DLL, base_address + HDDRSDRC2_CR);
+
+ /*
+ * Step 10: A Mode Register set(MRS) cycle is issied to reset DLL.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1:0] bits are set to 0.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x0 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 11: An all banks precharge command is issued to the DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /* wait 400 ns min (not needed on certain DDR2 devices) */
+ early_udelay(1);
+
+ /*
+ * Step 12: Two auto-refresh (CBR) cycles are provided.
+ * Program the auto refresh command (CBR) into the Mode Register.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /* wait TRFC cycles min (135 ns min) extended to 400 ns */
+ early_udelay(1);
+
+ /* Set 2nd CBR */
+ __raw_writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /* wait TRFC cycles min (135 ns min) extended to 400 ns */
+ early_udelay(1);
+
+ /*
+ * Step 13: Program DLL field into the Configuration Register to low(Disable DLL reset).
+ */
+ cr = __raw_readl(base_address + HDDRSDRC2_CR);
+ __raw_writel(cr & ~AT91C_DDRC2_ENABLE_RESET_DLL, base_address + HDDRSDRC2_CR);
+
+ /*
+ * Step 14: A Mode Register set (MRS) cycle is issued to program
+ * the parameters of the DDR2-SDRAM devices, in particular CAS latency,
+ * burst length and to disable DDL reset.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1:0] bits are set to 0.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x0 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 15: Program OCD field into the Configuration Register
+ * to high (OCD calibration default).
+ */
+ cr = __raw_readl(base_address + HDDRSDRC2_CR);
+ __raw_writel(cr | AT91C_DDRC2_OCD_DEFAULT, base_address + HDDRSDRC2_CR);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 16: An Extended Mode Register set (EMRS1) cycle is issued to OCD default value.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x1 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 17: Program OCD field into the Configuration Register
+ * to low (OCD calibration mode exit).
+ */
+ cr = __raw_readl(base_address + HDDRSDRC2_CR);
+ __raw_writel(cr & ~AT91C_DDRC2_OCD_DEFAULT, base_address + HDDRSDRC2_CR);
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 18: An Extended Mode Register set (EMRS1) cycle is issued to enable OCD exit.
+ * Perform a write access to DDR2-SDRAM to acknowledge this command.
+ * The write address must be chosen so that BA[1] is set to 0 and BA[0] is set to 1.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x1 << ba_offset));
+
+ /* wait 2 cycles min (of tCK) = 15 ns min */
+ early_udelay(1);
+
+ /*
+ * Step 19: A Nornal mode command is provided.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NORMAL_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 20: Perform a write access to any DDR2-SDRAM address
+ */
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 21: Write the refresh rate into the count field in the Refresh Timer register.
+ */
+ __raw_writel(ddramc_config->rtr, base_address + HDDRSDRC2_RTR);
+
+ /*
+ * Now we are ready to work on the DDRSDR
+ * wait for end of calibration
+ */
+ early_udelay(10);
+}
+
+/* This initialization sequence is sama5d3 and sama5d4 LP-DDR2 specific */
+
+void lpddr2_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct ddramc_register *ddramc_config)
+{
+ unsigned long reg;
+
+ __raw_writel(ddramc_config->lpddr2_lpr, base_address + MPDDRC_LPDDR2_LPR);
+
+ __raw_writel(ddramc_config->tim_calr, base_address + MPDDRC_LPDDR2_TIM_CAL);
+
+ /*
+ * Step 1: Program the memory device type.
+ */
+ __raw_writel(ddramc_config->mdr, base_address + HDDRSDRC2_MDR);
+
+ /*
+ * Step 2: Program the feature of the low-power DDR2-SDRAM device.
+ */
+ __raw_writel(ddramc_config->cr, base_address + HDDRSDRC2_CR);
+
+ __raw_writel(ddramc_config->t0pr, base_address + HDDRSDRC2_T0PR);
+ __raw_writel(ddramc_config->t1pr, base_address + HDDRSDRC2_T1PR);
+ __raw_writel(ddramc_config->t2pr, base_address + HDDRSDRC2_T2PR);
+
+ /*
+ * Step 3: A NOP command is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + HDDRSDRC2_MR);
+
+ /*
+ * Step 3bis: Add memory barrier then Perform a write access to
+ * any low-power DDR2-SDRAM address to acknowledge the command.
+ */
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 4: A pause of at least 100 ns must be observed before
+ * a single toggle.
+ */
+ early_udelay(1);
+
+ /*
+ * Step 5: A NOP command is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 6: A pause of at least 200 us must be observed before a Reset
+ * Command.
+ */
+ early_udelay(200);
+
+ /*
+ * Step 7: A Reset command is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MRS(63) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 8: A pause of at least tINIT5 must be observed before issuing
+ * any commands.
+ */
+ early_udelay(1);
+
+ /*
+ * Step 9: A Calibration command is issued to the low-power DDR2-SDRAM.
+ */
+ reg = __raw_readl(base_address + HDDRSDRC2_CR);
+ reg &= ~AT91C_DDRC2_ZQ;
+ reg |= AT91C_DDRC2_ZQ_RESET;
+ __raw_writel(reg, base_address + HDDRSDRC2_CR);
+
+ __raw_writel(AT91C_DDRC2_MRS(10) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 9bis: The ZQ Calibration command is now issued.
+ * Program the type of calibration in the MPDDRC_CR: set the
+ * ZQ field to the SHORT value.
+ */
+ reg = __raw_readl(base_address + HDDRSDRC2_CR);
+ reg &= ~AT91C_DDRC2_ZQ;
+ reg |= AT91C_DDRC2_ZQ_SHORT;
+ __raw_writel(reg, base_address + HDDRSDRC2_CR);
+
+ /*
+ * Step 10: A Mode Register Write command with 1 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MRS(1) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 11: A Mode Register Write command with 2 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MRS(2) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 12: A Mode Register Write command with 3 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MRS(3) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 13: A Mode Register Write command with 16 to the MRS field
+ * is issued to the low-power DDR2-SDRAM.
+ */
+ __raw_writel(AT91C_DDRC2_MRS(16) | AT91C_DDRC2_MODE_LPDDR2_CMD,
+ base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 14: A Normal Mode command is provided.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NORMAL_CMD, base_address + HDDRSDRC2_MR);
+ dmb();
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 15: close the input buffers: error in documentation: no need.
+ */
+
+ /*
+ * Step 16: Write the refresh rate into the COUNT field in the MPDDRC
+ * Refresh Timer Register.
+ */
+ __raw_writel(ddramc_config->rtr, base_address + HDDRSDRC2_RTR);
+
+ /*
+ * Now configure the CAL MR4 register.
+ */
+ __raw_writel(ddramc_config->cal_mr4r, base_address + MPDDRC_LPDDR2_CAL_MR4);
+}
+
+void lpddr1_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct ddramc_register *ddramc_config)
+{
+ unsigned long ba_offset;
+
+ /* Compute BA[] offset according to CR configuration */
+ ba_offset = (ddramc_config->cr & AT91C_DDRC2_NC) + 8;
+ if (!(ddramc_config->cr & AT91C_DDRC2_DECOD_INTERLEAVED))
+ ba_offset += ((ddramc_config->cr & AT91C_DDRC2_NR) >> 2) + 11;
+
+ ba_offset += (ddramc_config->mdr & AT91C_DDRC2_DBW) ? 1 : 2;
+
+ /*
+ * Step 1: Program the memory device type in the MPDDRC Memory Device Register
+ */
+ __raw_writel(ddramc_config->mdr, base_address + HDDRSDRC2_MDR);
+
+ /*
+ * Step 2: Program the features of the low-power DDR1-SDRAM device
+ * in the MPDDRC Configuration Register and in the MPDDRC Timing
+ * Parameter 0 Register/MPDDRC Timing Parameter 1 Register.
+ */
+ __raw_writel(ddramc_config->cr, base_address + HDDRSDRC2_CR);
+
+ __raw_writel(ddramc_config->t0pr, base_address + HDDRSDRC2_T0PR);
+ __raw_writel(ddramc_config->t1pr, base_address + HDDRSDRC2_T1PR);
+ __raw_writel(ddramc_config->t2pr, base_address + HDDRSDRC2_T2PR);
+
+ /*
+ * Step 3: Program Temperature Compensated Self-refresh (TCR),
+ * Partial Array Self-refresh (PASR) and Drive Strength (DS) parameters
+ * in the MPDDRC Low-power Register.
+ */
+ __raw_writel(ddramc_config->lpr, base_address + HDDRSDRC2_LPR);
+
+ /*
+ * Step 4: A NOP command is issued to the low-power DDR1-SDRAM.
+ * Program the NOP command in the MPDDRC Mode Register (MPDDRC_MR).
+ * The clocks which drive the low-power DDR1-SDRAM device
+ * are now enabled.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 5: A pause of at least 200 us must be observed before
+ * a signal toggle.
+ */
+ early_udelay(200);
+
+ /*
+ * Step 6: A NOP command is issued to the low-power DDR1-SDRAM.
+ * Program the NOP command in the MPDDRC_MR. calibration request is
+ * now made to the I/O pad.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NOP_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 7: An All Banks Precharge command is issued
+ * to the low-power DDR1-SDRAM.
+ * Program All Banks Precharge command in the MPDDRC_MR.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_PRCGALL_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 8: Two auto-refresh (CBR) cycles are provided.
+ * Program the Auto Refresh command (CBR) in the MPDDRC_MR.
+ * The application must write a four to the MODE field
+ * in the MPDDRC_MR. Perform a write access to any low-power
+ * DDR1-SDRAM location twice to acknowledge these commands.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ __raw_writel(AT91C_DDRC2_MODE_RFSH_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 9: An Extended Mode Register Set (EMRS) cycle is issued to
+ * program the low-power DDR1-SDRAM parameters (TCSR, PASR, DS).
+ * The application must write a five to the MODE field in the MPDDRC_MR
+ * and perform a write access to the SDRAM to acknowledge this command.
+ * The write address must be chosen so that signal BA[1] is set to 1
+ * and BA[0] is set to 0.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_EXT_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x2 << ba_offset));
+
+ /*
+ * Step 10: A Mode Register Set (MRS) cycle is issued to program
+ * parameters of the low-power DDR1-SDRAM devices, in particular
+ * CAS latency.
+ * The application must write a three to the MODE field in the MPDDRC_MR
+ * and perform a write access to the SDRAM to acknowledge this command.
+ * The write address must be chosen so that signals BA[1:0] are set to 0.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_LMR_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address + (0x0 << ba_offset));
+
+ /*
+ * Step 11: The application must enter Normal mode, write a zero
+ * to the MODE field in the MPDDRC_MR and perform a write access
+ * at any location in the SDRAM to acknowledge this command.
+ */
+ __raw_writel(AT91C_DDRC2_MODE_NORMAL_CMD, base_address + HDDRSDRC2_MR);
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 12: Perform a write access to any low-power DDR1-SDRAM address.
+ */
+ __raw_writel(0, ram_address);
+
+ /*
+ * Step 14: Write the refresh rate into the COUNT field in the MPDDRC
+ * Refresh Timer Register (MPDDRC_RTR):
+ */
+ __raw_writel(ddramc_config->rtr, base_address + HDDRSDRC2_RTR);
+}
diff --git a/arch/arm/mach-at91/include/mach/ddramc.h b/arch/arm/mach-at91/include/mach/ddramc.h
new file mode 100644
index 000000000000..e5151b2999d9
--- /dev/null
+++ b/arch/arm/mach-at91/include/mach/ddramc.h
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: BSD-1-Clause
+/*
+ * Copyright (c) 2006, Atmel Corporation
+ */
+#ifndef __DDRAMC_H__
+#define __DDRAMC_H__
+
+struct ddramc_register {
+ unsigned long mdr;
+ unsigned long cr;
+ unsigned long rtr;
+ unsigned long t0pr;
+ unsigned long t1pr;
+ unsigned long t2pr;
+ unsigned long lpr;
+ unsigned long lpddr2_lpr;
+ unsigned long tim_calr;
+ unsigned long cal_mr4r;
+};
+
+void ddram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct ddramc_register *ddramc_config);
+
+void lpddr2_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct ddramc_register *ddramc_config);
+
+
+void lpddr1_sdram_initialize(unsigned long base_address,
+ unsigned long ram_address,
+ struct ddramc_register *ddramc_config);
+
+
+#endif /* #ifndef __DDRAMC_H__ */
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 07/11] ARM: at91: import low level DDRAMC initialization code from at91bootstrap
2019-01-16 17:45 ` [PATCH 07/11] ARM: at91: import low level DDRAMC initialization code " Ahmad Fatoum
@ 2019-01-17 8:11 ` Sascha Hauer
2019-01-17 9:28 ` Ahmad Fatoum
0 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2019-01-17 8:11 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Wed, Jan 16, 2019 at 06:45:55PM +0100, Ahmad Fatoum wrote:
> This commit imports DDRAMC initialization routines for use in PBL from
> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> +
> +void ddram_initialize(unsigned long base_address,
> + unsigned long ram_address,
> + struct ddramc_register *ddramc_config)
All the exported functions should have a proper at91_ or whatever
prefix.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 07/11] ARM: at91: import low level DDRAMC initialization code from at91bootstrap
2019-01-17 8:11 ` Sascha Hauer
@ 2019-01-17 9:28 ` Ahmad Fatoum
0 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-17 9:28 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox
On 17/1/19 09:11, Sascha Hauer wrote:
> On Wed, Jan 16, 2019 at 06:45:55PM +0100, Ahmad Fatoum wrote:
>> This commit imports DDRAMC initialization routines for use in PBL from
>> https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/ddramc.c
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> +
>> +void ddram_initialize(unsigned long base_address,
>> + unsigned long ram_address,
>> + struct ddramc_register *ddramc_config)
>
> All the exported functions should have a proper at91_ or whatever
> prefix.
>
> Sascha
>
>
Will do in v2.
Thanks
Ahmad
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 08/11] ARM: at91: import lowlevel dbgu UART init code from at91bootstrap
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (6 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 07/11] ARM: at91: import low level DDRAMC initialization code " Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 09/11] ARM: at91: microchip-ksz9477-evb: reintroduce board code for first stage Ahmad Fatoum
` (3 subsequent siblings)
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
From: Ahmad Fatoum <ahmad@a3f.at>
For use in PBL, import dbgu init code from:
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/driver/at91_usart.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/include/mach/at91_dbgu.h | 57 ++++++++++++++++++++-
1 file changed, 56 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 3b5948566e52..a6f44f744f2a 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -5,7 +5,7 @@
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
- * Based on AT91RM9200 datasheet revision E.
+ * Based on AT91RM9200 datasheet revision E and SAMA5D3 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -16,9 +16,37 @@
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
+#include <asm/io.h>
+
#if !defined(CONFIG_ARCH_AT91X40)
#define AT91_DBGU_CR (0x00) /* Control Register */
+#define AT91_DBGU_RSTRX (1 << 2) /* Reset Receiver */
+#define AT91_DBGU_RSTTX (1 << 3) /* Reset Transmitter */
+#define AT91_DBGU_RXEN (1 << 4) /* Receiver Enable */
+#define AT91_DBGU_RXDIS (1 << 5) /* Receiver Disable */
+#define AT91_DBGU_TXEN (1 << 6) /* Transmitter Enable */
+#define AT91_DBGU_TXDIS (1 << 7) /* Transmitter Disable */
+#define AT91_DBGU_RSTSTA (1 << 8) /* Reset Status Bits */
#define AT91_DBGU_MR (0x04) /* Mode Register */
+#define AT91_DBGU_NBSTOP_1BIT (0 << 12) /* 1 stop bit */
+#define AT91_DBGU_NBSTOP_1_5BIT (1 << 12) /* 1.5 stop bits */
+#define AT91_DBGU_NBSTOP_2BIT (2 << 12) /* 2 stop bits */
+
+#define AT91_DBGU_CHRL_5BIT (0 << 6) /* 5 bit character length */
+#define AT91_DBGU_CHRL_6BIT (1 << 6) /* 6 bit character length */
+#define AT91_DBGU_CHRL_7BIT (2 << 6) /* 7 bit character length */
+#define AT91_DBGU_CHRL_8BIT (3 << 6) /* 8 bit character length */
+
+#define AT91_DBGU_PAR_EVEN (0 << 9) /* Even Parity */
+#define AT91_DBGU_PAR_ODD (1 << 9) /* Odd Parity */
+#define AT91_DBGU_PAR_SPACE (2 << 9) /* Space: Force Parity to 0 */
+#define AT91_DBGU_PAR_MARK (3 << 9) /* Mark: Force Parity to 1 */
+#define AT91_DBGU_PAR_NONE (4 << 9) /* No Parity */
+
+#define AT91_DBGU_CHMODE_NORMAL (0 << 14) /* Normal mode */
+#define AT91_DBGU_CHMODE_AUTO (1 << 14) /* Automatic Echo */
+#define AT91_DBGU_CHMODE_LOCAL (2 << 14) /* Local Loopback */
+#define AT91_DBGU_CHMODE_REMOTE (3 << 14) /* Remote Loopback */
#define AT91_DBGU_IER (0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
@@ -63,4 +91,31 @@
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_DEBUG_LL
+static inline void at91_dbgu_setup_ll(unsigned long dbgu_base, unsigned baudrate)
+{
+ __raw_writel(~0, dbgu_base + AT91_DBGU_IDR);
+
+ __raw_writel(AT91_DBGU_RSTRX
+ | AT91_DBGU_RSTTX
+ | AT91_DBGU_RXDIS
+ | AT91_DBGU_TXDIS,
+ dbgu_base + AT91_DBGU_CR);
+
+ __raw_writel(baudrate, dbgu_base + AT91_DBGU_BRGR);
+
+ __raw_writel(AT91_DBGU_PAR_NONE
+ | AT91_DBGU_CHMODE_NORMAL
+ | AT91_DBGU_CHRL_8BIT
+ | AT91_DBGU_NBSTOP_1BIT,
+ dbgu_base + AT91_DBGU_MR);
+
+ __raw_writel(AT91_DBGU_RXEN | AT91_DBGU_TXEN, dbgu_base + AT91_DBGU_CR);
+}
+#else
+static inline void at91_dbgu_setup_ll(unsigned long dbgu_base, unsigned baudrate) {}
+#endif
+#endif
+
#endif
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 09/11] ARM: at91: microchip-ksz9477-evb: reintroduce board code for first stage
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (7 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 08/11] ARM: at91: import lowlevel dbgu UART init " Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-17 8:25 ` Sascha Hauer
2019-01-16 17:45 ` [PATCH 10/11] ARM: at91: microchip-ksz9477-evb: import low level init from at91bootstrap Ahmad Fatoum
` (2 subsequent siblings)
11 siblings, 1 reply; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox; +Cc: Ahmad Fatoum
From: Ahmad Fatoum <ahmad@a3f.at>
We are limited to 64K in the first stage, but we still need MMC and FAT
support, so to make place, make the device tree support optional by
providing the sama5d3's board code for NAND/MMC as an alternative.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
arch/arm/boards/microchip-ksz9477-evb/init.c | 143 ++++++++++++++++++
.../configs/microchip_ksz9477_evb_defconfig | 1 +
arch/arm/dts/Makefile | 2 +-
arch/arm/mach-at91/Kconfig | 11 +-
5 files changed, 157 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boards/microchip-ksz9477-evb/init.c
diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile
index b08c4a93ca27..0ca5b98a9b33 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/Makefile
+++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
@@ -1 +1,4 @@
lwl-y += lowlevel.o
+ifeq ($(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT),)
+obj-y += init.o
+endif
diff --git a/arch/arm/boards/microchip-ksz9477-evb/init.c b/arch/arm/boards/microchip-ksz9477-evb/init.c
new file mode 100644
index 000000000000..39febad84c5d
--- /dev/null
+++ b/arch/arm/boards/microchip-ksz9477-evb/init.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2014 Bo Shen <voice.shen@gmail.com>
+ */
+
+#include <init.h>
+#include <mach/board.h>
+#include <mach/iomux.h>
+
+#if defined(CONFIG_NAND_ATMEL)
+static struct atmel_nand_data nand_pdata = {
+ .ale = 21,
+ .cle = 22,
+ .det_pin = -EINVAL,
+ .rdy_pin = -EINVAL,
+ .enable_pin = -EINVAL,
+ .ecc_mode = NAND_ECC_HW,
+ .has_pmecc = 1,
+ .pmecc_sector_size = 512,
+ .pmecc_corr_cap = 4,
+#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
+ .bus_width_16 = 1,
+#endif
+ .on_flash_bbt = 1,
+};
+
+static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
+ .ncs_read_setup = 1,
+ .nrd_setup = 2,
+ .ncs_write_setup = 1,
+ .nwe_setup = 2,
+
+ .ncs_read_pulse = 5,
+ .nrd_pulse = 3,
+ .ncs_write_pulse = 5,
+ .nwe_pulse = 3,
+
+ .read_cycle = 8,
+ .write_cycle = 8,
+
+ .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
+ .tdf_cycles = 3,
+
+ .tclr = 3,
+ .tadl = 10,
+ .tar = 3,
+ .ocms = 0,
+ .trr = 4,
+ .twb = 5,
+ .rbnsel = 3,
+ .nfsel = 1
+};
+
+static void ek_add_device_nand(void)
+{
+ struct clk *clk = clk_get(NULL, "smc_clk");
+
+ clk_enable(clk);
+
+ /* setup bus-width (8 or 16) */
+ if (nand_pdata.bus_width_16)
+ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
+ else
+ sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
+
+ /* configure chip-select 3 (NAND) */
+ sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
+
+ at91_add_device_nand(&nand_pdata);
+}
+#else
+static void ek_add_device_nand(void) {}
+#endif
+
+#if defined(CONFIG_MCI_ATMEL)
+/*
+ * MCI (SD/MMC)
+ */
+static struct atmel_mci_platform_data mci0_data = {
+ .bus_width = 8,
+ .detect_pin = AT91_PIN_PE0,
+ .wp_pin = -EINVAL,
+};
+
+static void ek_add_device_mci(void)
+{
+ /* MMC0 */
+ at91_add_device_mci(0, &mci0_data);
+}
+#else
+static void ek_add_device_mci(void) {}
+#endif
+
+static int sama5d3_xplained_mem_init(void)
+{
+ at91_add_device_sdram(0);
+
+ return 0;
+}
+mem_initcall(sama5d3_xplained_mem_init);
+
+static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
+ {
+ .offset = 0x00000,
+ .size = SZ_256K,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "at91bootstrap_raw",
+ .bbname = "at91bootstrap",
+ }, {
+ .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
+ .size = SZ_256K + SZ_128K,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "self_raw",
+ .bbname = "self0",
+ },
+ /* hole of 128 KiB */
+ {
+ .offset = SZ_512K + SZ_256K,
+ .size = SZ_256K,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "env_raw",
+ .bbname = "env0",
+ }, {
+ .offset = DEVFS_PARTITION_APPEND, /* 1 MiB */
+ .size = SZ_256K,
+ .flags = DEVFS_PARTITION_FIXED,
+ .name = "env_raw1",
+ .bbname = "env1",
+ }, {
+ /* sentinel */
+ }
+};
+
+static int sama5d3_xplained_devices_init(void)
+{
+ ek_add_device_nand();
+ ek_add_device_mci();
+
+ devfs_create_partitions("nand0", sama5d3_xplained_nand0_partitions);
+
+ return 0;
+}
+device_initcall(sama5d3_xplained_devices_init);
diff --git a/arch/arm/configs/microchip_ksz9477_evb_defconfig b/arch/arm/configs/microchip_ksz9477_evb_defconfig
index e7d05bd13b46..33cf2198a696 100644
--- a/arch/arm/configs/microchip_ksz9477_evb_defconfig
+++ b/arch/arm/configs/microchip_ksz9477_evb_defconfig
@@ -59,6 +59,7 @@ CONFIG_CMD_OFTREE=y
CONFIG_CMD_TIME=y
CONFIG_NET=y
CONFIG_NET_NFS=y
+CONFIG_OFDEVICE=y
CONFIG_OF_BAREBOX_DRIVERS=y
CONFIG_OF_BAREBOX_ENV_IN_FS=y
CONFIG_DRIVER_NET_MACB=y
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c08b35a10132..ef2a1961e165 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -118,7 +118,7 @@ pbl-dtb-$(CONFIG_MACH_ZII_VF610_DEV) += \
vf610-zii-ssmb-spu3.dtb.o \
vf610-zii-scu4-aib-rev-c.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9263EK_DT) += at91sam9263ek.dtb.o
-pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB) += at91-microchip-ksz9477-evb.dtb.o
+pbl-dtb-$(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT) += at91-microchip-ksz9477-evb.dtb.o
pbl-dtb-$(CONFIG_MACH_AT91SAM9X5EK) += at91sam9x5ek.dtb.o
pbl-dtb-$(CONFIG_MACH_ZII_IMX7D_RPU2) += imx7d-zii-rpu2.dtb.o
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 98d18c8b26db..068fb139f2a7 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -30,6 +30,13 @@ config MACH_AT91SAM9263EK_DT
Enabled for at91sam9263ek - evaluation kit.
But only if we need the device tree (bootstrap do not use DT)
+config MACH_MICROCHIP_KSZ9477_EVB_DT
+ def_bool y
+ depends on MACH_MICROCHIP_KSZ9477_EVB && OFDEVICE
+ help
+ Enabled for Microchip KSZ9477 - evaluation kit.
+ But only if we need the device tree (bootstrap do not use DT)
+
config HAVE_AT91_SMD
bool
@@ -540,8 +547,8 @@ config MACH_AT91SAM9X5EK
config MACH_MICROCHIP_KSZ9477_EVB
bool "Microchip EVB-KSZ9477 Evaluation Kit"
depends on ARCH_SAMA5D3
- select OFDEVICE
- select COMMON_CLK_OF_PROVIDER
+ select HAVE_AT91_BOOTSTRAP
+ select COMMON_CLK_OF_PROVIDER if MACH_MICROCHIP_KSZ9477_EVB_DT
help
Select this if you are using Microchip's EVB-KSZ9477 Evaluation Kit.
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 09/11] ARM: at91: microchip-ksz9477-evb: reintroduce board code for first stage
2019-01-16 17:45 ` [PATCH 09/11] ARM: at91: microchip-ksz9477-evb: reintroduce board code for first stage Ahmad Fatoum
@ 2019-01-17 8:25 ` Sascha Hauer
2019-01-17 9:37 ` Ahmad Fatoum
0 siblings, 1 reply; 20+ messages in thread
From: Sascha Hauer @ 2019-01-17 8:25 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox, Ahmad Fatoum
On Wed, Jan 16, 2019 at 06:45:57PM +0100, Ahmad Fatoum wrote:
> From: Ahmad Fatoum <ahmad@a3f.at>
>
> We are limited to 64K in the first stage, but we still need MMC and FAT
> support, so to make place, make the device tree support optional by
> providing the sama5d3's board code for NAND/MMC as an alternative.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> .../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
> arch/arm/boards/microchip-ksz9477-evb/init.c | 143 ++++++++++++++++++
> .../configs/microchip_ksz9477_evb_defconfig | 1 +
> arch/arm/dts/Makefile | 2 +-
> arch/arm/mach-at91/Kconfig | 11 +-
> 5 files changed, 157 insertions(+), 3 deletions(-)
> create mode 100644 arch/arm/boards/microchip-ksz9477-evb/init.c
>
> diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile
> index b08c4a93ca27..0ca5b98a9b33 100644
> --- a/arch/arm/boards/microchip-ksz9477-evb/Makefile
> +++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
> @@ -1 +1,4 @@
> lwl-y += lowlevel.o
> +ifeq ($(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT),)
> +obj-y += init.o
> +endif
> diff --git a/arch/arm/boards/microchip-ksz9477-evb/init.c b/arch/arm/boards/microchip-ksz9477-evb/init.c
> new file mode 100644
> index 000000000000..39febad84c5d
> --- /dev/null
> +++ b/arch/arm/boards/microchip-ksz9477-evb/init.c
> @@ -0,0 +1,143 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2014 Bo Shen <voice.shen@gmail.com>
> + */
> +
> +#include <init.h>
> +#include <mach/board.h>
> +#include <mach/iomux.h>
> +
> +#if defined(CONFIG_NAND_ATMEL)
> +static struct atmel_nand_data nand_pdata = {
> + .ale = 21,
> + .cle = 22,
> + .det_pin = -EINVAL,
> + .rdy_pin = -EINVAL,
> + .enable_pin = -EINVAL,
> + .ecc_mode = NAND_ECC_HW,
> + .has_pmecc = 1,
> + .pmecc_sector_size = 512,
> + .pmecc_corr_cap = 4,
> +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
> + .bus_width_16 = 1,
> +#endif
> + .on_flash_bbt = 1,
> +};
> +
> +static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
> + .ncs_read_setup = 1,
> + .nrd_setup = 2,
> + .ncs_write_setup = 1,
> + .nwe_setup = 2,
> +
> + .ncs_read_pulse = 5,
> + .nrd_pulse = 3,
> + .ncs_write_pulse = 5,
> + .nwe_pulse = 3,
> +
> + .read_cycle = 8,
> + .write_cycle = 8,
> +
> + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
> + .tdf_cycles = 3,
> +
> + .tclr = 3,
> + .tadl = 10,
> + .tar = 3,
> + .ocms = 0,
> + .trr = 4,
> + .twb = 5,
> + .rbnsel = 3,
> + .nfsel = 1
> +};
> +
> +static void ek_add_device_nand(void)
> +{
> + struct clk *clk = clk_get(NULL, "smc_clk");
> +
> + clk_enable(clk);
> +
> + /* setup bus-width (8 or 16) */
> + if (nand_pdata.bus_width_16)
> + sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
> + else
> + sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
> +
> + /* configure chip-select 3 (NAND) */
> + sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
> +
> + at91_add_device_nand(&nand_pdata);
> +}
> +#else
> +static void ek_add_device_nand(void) {}
> +#endif
> +
> +#if defined(CONFIG_MCI_ATMEL)
> +/*
> + * MCI (SD/MMC)
> + */
> +static struct atmel_mci_platform_data mci0_data = {
> + .bus_width = 8,
> + .detect_pin = AT91_PIN_PE0,
> + .wp_pin = -EINVAL,
> +};
> +
> +static void ek_add_device_mci(void)
> +{
> + /* MMC0 */
> + at91_add_device_mci(0, &mci0_data);
> +}
> +#else
> +static void ek_add_device_mci(void) {}
> +#endif
> +
> +static int sama5d3_xplained_mem_init(void)
> +{
> + at91_add_device_sdram(0);
> +
> + return 0;
> +}
> +mem_initcall(sama5d3_xplained_mem_init);
> +
> +static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
> + {
> + .offset = 0x00000,
> + .size = SZ_256K,
> + .flags = DEVFS_PARTITION_FIXED,
> + .name = "at91bootstrap_raw",
> + .bbname = "at91bootstrap",
> + }, {
> + .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
> + .size = SZ_256K + SZ_128K,
384K can get tight quite fast for bigger barebox images. I would at
least add the 128KiB hole below, but preferrably go to something like
1MiB for barebox.
> + .flags = DEVFS_PARTITION_FIXED,
> + .name = "self_raw",
> + .bbname = "self0",
> + },
> + /* hole of 128 KiB */
> + {
> + .offset = SZ_512K + SZ_256K,
> + .size = SZ_256K,
> + .flags = DEVFS_PARTITION_FIXED,
> + .name = "env_raw",
> + .bbname = "env0",
> + }, {
> + .offset = DEVFS_PARTITION_APPEND, /* 1 MiB */
> + .size = SZ_256K,
> + .flags = DEVFS_PARTITION_FIXED,
> + .name = "env_raw1",
> + .bbname = "env1",
> + }, {
The environment partitions end up unused, right? So I think you should
remove them here.
Sascha
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 09/11] ARM: at91: microchip-ksz9477-evb: reintroduce board code for first stage
2019-01-17 8:25 ` Sascha Hauer
@ 2019-01-17 9:37 ` Ahmad Fatoum
0 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-17 9:37 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox, Ahmad Fatoum
Hello,
On 17/1/19 09:25, Sascha Hauer wrote:
> On Wed, Jan 16, 2019 at 06:45:57PM +0100, Ahmad Fatoum wrote:
>> From: Ahmad Fatoum <ahmad@a3f.at>
>>
>> We are limited to 64K in the first stage, but we still need MMC and FAT
>> support, so to make place, make the device tree support optional by
>> providing the sama5d3's board code for NAND/MMC as an alternative.
>>
>> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
>> ---
>> .../arm/boards/microchip-ksz9477-evb/Makefile | 3 +
>> arch/arm/boards/microchip-ksz9477-evb/init.c | 143 ++++++++++++++++++
>> .../configs/microchip_ksz9477_evb_defconfig | 1 +
>> arch/arm/dts/Makefile | 2 +-
>> arch/arm/mach-at91/Kconfig | 11 +-
>> 5 files changed, 157 insertions(+), 3 deletions(-)
>> create mode 100644 arch/arm/boards/microchip-ksz9477-evb/init.c
>>
>> diff --git a/arch/arm/boards/microchip-ksz9477-evb/Makefile b/arch/arm/boards/microchip-ksz9477-evb/Makefile
>> index b08c4a93ca27..0ca5b98a9b33 100644
>> --- a/arch/arm/boards/microchip-ksz9477-evb/Makefile
>> +++ b/arch/arm/boards/microchip-ksz9477-evb/Makefile
>> @@ -1 +1,4 @@
>> lwl-y += lowlevel.o
>> +ifeq ($(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT),)
>> +obj-y += init.o
>> +endif
>> diff --git a/arch/arm/boards/microchip-ksz9477-evb/init.c b/arch/arm/boards/microchip-ksz9477-evb/init.c
>> new file mode 100644
>> index 000000000000..39febad84c5d
>> --- /dev/null
>> +++ b/arch/arm/boards/microchip-ksz9477-evb/init.c
>> @@ -0,0 +1,143 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * Copyright (C) 2014 Bo Shen <voice.shen@gmail.com>
>> + */
>> +
>> +#include <init.h>
>> +#include <mach/board.h>
>> +#include <mach/iomux.h>
>> +
>> +#if defined(CONFIG_NAND_ATMEL)
>> +static struct atmel_nand_data nand_pdata = {
>> + .ale = 21,
>> + .cle = 22,
>> + .det_pin = -EINVAL,
>> + .rdy_pin = -EINVAL,
>> + .enable_pin = -EINVAL,
>> + .ecc_mode = NAND_ECC_HW,
>> + .has_pmecc = 1,
>> + .pmecc_sector_size = 512,
>> + .pmecc_corr_cap = 4,
>> +#if defined(CONFIG_MTD_NAND_ATMEL_BUSWIDTH_16)
>> + .bus_width_16 = 1,
>> +#endif
>> + .on_flash_bbt = 1,
>> +};
>> +
>> +static struct sam9_smc_config sama5d3_xplained_nand_smc_config = {
>> + .ncs_read_setup = 1,
>> + .nrd_setup = 2,
>> + .ncs_write_setup = 1,
>> + .nwe_setup = 2,
>> +
>> + .ncs_read_pulse = 5,
>> + .nrd_pulse = 3,
>> + .ncs_write_pulse = 5,
>> + .nwe_pulse = 3,
>> +
>> + .read_cycle = 8,
>> + .write_cycle = 8,
>> +
>> + .mode = AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE,
>> + .tdf_cycles = 3,
>> +
>> + .tclr = 3,
>> + .tadl = 10,
>> + .tar = 3,
>> + .ocms = 0,
>> + .trr = 4,
>> + .twb = 5,
>> + .rbnsel = 3,
>> + .nfsel = 1
>> +};
>> +
>> +static void ek_add_device_nand(void)
>> +{
>> + struct clk *clk = clk_get(NULL, "smc_clk");
>> +
>> + clk_enable(clk);
>> +
>> + /* setup bus-width (8 or 16) */
>> + if (nand_pdata.bus_width_16)
>> + sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_16;
>> + else
>> + sama5d3_xplained_nand_smc_config.mode |= AT91_SMC_DBW_8;
>> +
>> + /* configure chip-select 3 (NAND) */
>> + sama5_smc_configure(0, 3, &sama5d3_xplained_nand_smc_config);
>> +
>> + at91_add_device_nand(&nand_pdata);
>> +}
>> +#else
>> +static void ek_add_device_nand(void) {}
>> +#endif
>> +
>> +#if defined(CONFIG_MCI_ATMEL)
>> +/*
>> + * MCI (SD/MMC)
>> + */
>> +static struct atmel_mci_platform_data mci0_data = {
>> + .bus_width = 8,
>> + .detect_pin = AT91_PIN_PE0,
>> + .wp_pin = -EINVAL,
>> +};
>> +
>> +static void ek_add_device_mci(void)
>> +{
>> + /* MMC0 */
>> + at91_add_device_mci(0, &mci0_data);
>> +}
>> +#else
>> +static void ek_add_device_mci(void) {}
>> +#endif
>> +
>> +static int sama5d3_xplained_mem_init(void)
>> +{
>> + at91_add_device_sdram(0);
>> +
>> + return 0;
>> +}
>> +mem_initcall(sama5d3_xplained_mem_init);
>> +
>> +static const struct devfs_partition sama5d3_xplained_nand0_partitions[] = {
>> + {
>> + .offset = 0x00000,
>> + .size = SZ_256K,
>> + .flags = DEVFS_PARTITION_FIXED,
>> + .name = "at91bootstrap_raw",
>> + .bbname = "at91bootstrap",
>> + }, {
>> + .offset = DEVFS_PARTITION_APPEND, /* 256 KiB */
>> + .size = SZ_256K + SZ_128K,
>
> 384K can get tight quite fast for bigger barebox images. I would at
> least add the 128KiB hole below, but preferrably go to something like
> 1MiB for barebox.
I see. The code is a straight copy of the sama5d3_xplained/init.c,
and untested because I tested only SD card boot.
I'll bump this to 1M.
>
>> + .flags = DEVFS_PARTITION_FIXED,
>> + .name = "self_raw",
>> + .bbname = "self0",
>> + },
>> + /* hole of 128 KiB */
>> + {
>> + .offset = SZ_512K + SZ_256K,
>> + .size = SZ_256K,
>> + .flags = DEVFS_PARTITION_FIXED,
>> + .name = "env_raw",
>> + .bbname = "env0",
>> + }, {
>> + .offset = DEVFS_PARTITION_APPEND, /* 1 MiB */
>> + .size = SZ_256K,
>> + .flags = DEVFS_PARTITION_FIXED,
>> + .name = "env_raw1",
>> + .bbname = "env1",
>> + }, {
>
> The environment partitions end up unused, right? So I think you should
> remove them here.
And if a user wants an environment, they encode this into the second
stage's device tree instead? Ye, I can do that.
>
> Sascha
>
Thanks
Ahmad
--
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^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 10/11] ARM: at91: microchip-ksz9477-evb: import low level init from at91bootstrap
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (8 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 09/11] ARM: at91: microchip-ksz9477-evb: reintroduce board code for first stage Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 17:45 ` [PATCH 11/11] ARM: at91: microchip-ksz9477-evb: add first stage MMC defconfig Ahmad Fatoum
2019-01-16 18:47 ` [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Sam Ravnborg
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
This imports
https://github.com/linux4sam/at91bootstrap/blob/v3.8.12/board/sama5d3_xplained/sama5d3_xplained.c
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
.../boards/microchip-ksz9477-evb/lowlevel.c | 196 +++++++++++++++++-
arch/arm/mach-at91/include/mach/at91_pmc.h | 19 ++
arch/arm/mach-at91/include/mach/sama5d3.h | 1 +
3 files changed, 211 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
index 639958a459ad..110a93e8cd13 100644
--- a/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
+++ b/arch/arm/boards/microchip-ksz9477-evb/lowlevel.c
@@ -10,19 +10,205 @@
#include <asm/barebox-arm-head.h>
#include <asm/barebox-arm.h>
-#include <mach/hardware.h>
+#include <debug_ll.h>
+#include <linux/kconfig.h>
+#include <mach/at91_dbgu.h>
+#include <mach/at91_ddrsdrc.h>
+#include <mach/at91_lowlevel_clock.h>
+#include <mach/at91_pio.h>
+#include <mach/at91_pmc.h>
+#include <mach/at91_wdt.h>
+#include <mach/ddramc.h>
+#include <mach/early_udelay.h>
+#include <mach/gpio.h>
+#include <mach/iomux.h>
-extern char __dtb_at91_microchip_ksz9477_evb_start[];
+/* PCK = 528MHz, MCK = 132MHz */
+#define MASTER_CLOCK 132000000
-ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
+#define sama5d3_pmc_enable_periph_clock(clk) \
+ at91_pmc_enable_periph_clock(IOMEM(SAMA5D3_BASE_PMC), clk)
+
+#define at91_pmc_write(off, val) writel(val, IOMEM(SAMA5D3_BASE_PMC) + off)
+#define at91_pmc_read(off) readl(IOMEM(SAMA5D3_BASE_PMC) + off)
+
+#define BAUDRATE(mck, baud) \
+ (((((mck) * 10) / ((baud) * 16)) % 10) >= 5) ? \
+ (mck / (baud * 16) + 1) : ((mck) / (baud * 16))
+
+
+static void configure_pin(unsigned pin)
+{
+ void __iomem *pio = IOMEM(SAMA5D3_BASE_PIOB);
+ unsigned mask = pin_to_mask(pin);
+
+ at91_mux_disable_interrupt(pio, mask);
+ at91_mux_set_pullup(pio, mask, 0);
+ at91_mux_pio3_set_pulldown(pio, mask, 0);
+
+ at91_mux_pio3_set_A_periph(pio, mask);
+
+ at91_mux_gpio_disable(pio, mask);
+}
+
+static void dbgu_init(void)
+{
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_PIOB);
+
+ configure_pin(AT91_PIN_PB30);
+ configure_pin(AT91_PIN_PB31);
+
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_DBGU);
+ at91_dbgu_setup_ll(AT91_BASE_DBGU1, BAUDRATE(MASTER_CLOCK, 115200));
+
+ putc_ll('>');
+}
+
+static void ddramc_reg_config(struct ddramc_register *ddramc_config)
+{
+ ddramc_config->mdr = (AT91C_DDRC2_DBW_32_BITS
+ | AT91C_DDRC2_MD_DDR2_SDRAM);
+
+ ddramc_config->cr = (AT91C_DDRC2_NC_DDR10_SDR9
+ | AT91C_DDRC2_NR_13
+ | AT91C_DDRC2_CAS_3
+ | AT91C_DDRC2_DISABLE_RESET_DLL
+ | AT91C_DDRC2_ENABLE_DLL
+ | AT91C_DDRC2_ENRDM_ENABLE
+ | AT91C_DDRC2_NB_BANKS_8
+ | AT91C_DDRC2_NDQS_DISABLED
+ | AT91C_DDRC2_DECOD_INTERLEAVED
+ | AT91C_DDRC2_UNAL_SUPPORTED);
+
+ /*
+ * The DDR2-SDRAM device requires a refresh every 15.625 us or 7.81 us.
+ * With a 133 MHz frequency, the refresh timer count register must to be
+ * set with (15.625 x 133 MHz) ~ 2084 i.e. 0x824
+ * or (7.81 x 133 MHz) ~ 1039 i.e. 0x40F.
+ */
+ ddramc_config->rtr = 0x40F; /* Refresh timer: 7.812us */
+
+ /* One clock cycle @ 133 MHz = 7.5 ns */
+ ddramc_config->t0pr = (AT91C_DDRC2_TRAS_(6) /* 6 * 7.5 = 45 ns */
+ | AT91C_DDRC2_TRCD_(2) /* 2 * 7.5 = 22.5 ns */
+ | AT91C_DDRC2_TWR_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TRC_(8) /* 8 * 7.5 = 75 ns */
+ | AT91C_DDRC2_TRP_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TRRD_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TWTR_(2) /* 2 clock cycles min */
+ | AT91C_DDRC2_TMRD_(2)); /* 2 clock cycles */
+
+ ddramc_config->t1pr = (AT91C_DDRC2_TXP_(2) /* 2 clock cycles */
+ | AT91C_DDRC2_TXSRD_(200) /* 200 clock cycles */
+ | AT91C_DDRC2_TXSNR_(19) /* 19 * 7.5 = 142.5 ns */
+ | AT91C_DDRC2_TRFC_(17)); /* 17 * 7.5 = 127.5 ns */
+
+ ddramc_config->t2pr = (AT91C_DDRC2_TFAW_(6) /* 6 * 7.5 = 45 ns */
+ | AT91C_DDRC2_TRTP_(2) /* 2 clock cycles min */
+ | AT91C_DDRC2_TRPA_(2) /* 2 * 7.5 = 15 ns */
+ | AT91C_DDRC2_TXARDS_(8) /* = TXARD */
+ | AT91C_DDRC2_TXARD_(8)); /* MR12 = 1 */
+}
+
+static void sama5d3_ddramc_init(void)
{
+ struct ddramc_register ddramc_reg;
+ unsigned int reg;
+
+ ddramc_reg_config(&ddramc_reg);
+
+ /* enable ddr2 clock */
+ sama5d3_pmc_enable_periph_clock(SAMA5D3_ID_MPDDRC);
+ at91_pmc_write(AT91_PMC_SCER, AT91CAP9_PMC_DDR);
+
+
+ /* Init the special register for sama5d3x */
+ /* MPDDRC DLL Slave Offset Register: DDR2 configuration */
+ reg = AT91C_MPDDRC_S0OFF_1
+ | AT91C_MPDDRC_S2OFF_1
+ | AT91C_MPDDRC_S3OFF_1;
+ writel(reg, (SAMA5D3_BASE_MPDDRC + MPDDRC_DLL_SOR));
+
+ /* MPDDRC DLL Master Offset Register */
+ /* write master + clk90 offset */
+ reg = AT91C_MPDDRC_MOFF_7
+ | AT91C_MPDDRC_CLK90OFF_31
+ | AT91C_MPDDRC_SELOFF_ENABLED | AT91C_MPDDRC_KEY;
+ writel(reg, (SAMA5D3_BASE_MPDDRC + MPDDRC_DLL_MOR));
+
+ /* MPDDRC I/O Calibration Register */
+ /* DDR2 RZQ = 50 Ohm */
+ /* TZQIO = 4 */
+ reg = AT91C_MPDDRC_RDIV_DDR2_RZQ_50
+ | AT91C_MPDDRC_TZQIO_4;
+ writel(reg, (SAMA5D3_BASE_MPDDRC + MPDDRC_IO_CALIBR));
+
+ /* DDRAM2 Controller initialize */
+ ddram_initialize(SAMA5D3_BASE_MPDDRC, SAMA5_DDRCS, &ddramc_reg);
+}
+
+extern char __dtb_at91_microchip_ksz9477_evb_start[];
+
+static void noinline board_init(void) {
void *fdt;
+ if (get_pc() < SAMA5_DDRCS) {
+ at91_wdt_disable(IOMEM(SAMA5D3_BASE_WDT));
+ at91_lowlevel_clock_init(IOMEM(SAMA5D3_BASE_PMC));
+
+ /* At this stage the main oscillator
+ * is supposed to be enabled PCK = MCK = MOSC
+ */
+
+ /* Configure PLLA = MOSC * (PLL_MULA + 1) / PLL_DIVA */
+ at91_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA);
+ at91_pmc_write(AT91_CKGR_PLLAR, AT91_PMC_PLLA_WR_ERRATA
+ | AT91_PMC3_MUL_(43) | AT91_PMC_OUT_0
+ | AT91_PMC_PLLCOUNT
+ | AT91_PMC_DIV_BYPASS);
+
+ while (!(at91_pmc_read(AT91_PMC_SR) & AT91_PMC_LOCKA))
+ ;
+
+ /* Initialize PLLA charge pump */
+ at91_pmc_write(AT91_PMC_PLLICPR, AT91_PMC_IPLLA_3);
+
+ /* Switch PCK/MCK on Main clock output */
+ at91_pmc_cfg_mck(IOMEM(SAMA5D3_BASE_PMC), AT91SAM9_PMC_MDIV_4
+ | AT91_PMC_CSS_MAIN);
+
+ /* Switch PCK/MCK on PLLA output */
+ at91_pmc_cfg_mck(IOMEM(SAMA5D3_BASE_PMC), AT91SAM9_PMC_MDIV_4
+ | AT91_PMC_CSS_PLLA);
+
+ early_udelay_init(IOMEM(SAMA5D3_BASE_PMC), IOMEM(SAMA5D3_BASE_PIT),
+ SAMA5D3_ID_PIT, MASTER_CLOCK);
+ }
+
+ if (IS_ENABLED(CONFIG_DEBUG_LL))
+ dbgu_init();
+
+ if (get_pc() < SAMA5_DDRCS)
+ sama5d3_ddramc_init();
+
+ if (IS_ENABLED(CONFIG_MACH_MICROCHIP_KSZ9477_EVB_DT))
+ fdt = __dtb_at91_microchip_ksz9477_evb_start + get_runtime_offset();
+ else
+ fdt = NULL;
+
+ barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
+}
+
+
+ENTRY_FUNCTION(start_sama5d3_xplained_ung8071, r0, r1, r2)
+{
arm_cpu_lowlevel_init();
arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);
- fdt = __dtb_at91_microchip_ksz9477_evb_start + get_runtime_offset();
+ relocate_to_current_adr();
+ setup_c();
+ barrier();
- barebox_arm_entry(SAMA5_DDRCS, SZ_256M, fdt);
+ board_init();
}
diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index 0f13e4f4d391..1e708f78d555 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -63,9 +63,17 @@
#define AT91_CKGR_PLLAR 0x28 /* PLL A Register */
#define AT91_CKGR_PLLBR 0x2c /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
+#define AT91_PMC_DIV_BYPASS (1 << 0) /* Divider bypass */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
+#define AT91_PMC_OUT_0 (0 << 14)
+#define AT91_PMC_OUT_1 (1 << 14)
+#define AT91_PMC_OUT_2 (2 << 14)
+#define AT91_PMC_OUT_3 (3 << 14)
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
+#define AT91_PMC_MUL_(n) (((n) << 16) & AT91_PMC_MUL)
+#define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only]*/
+#define AT91_PMC3_MUL_(n) (((n) << 18) & AT91_PMC3_MUL)
#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
#define AT91_PMC_USBDIV_1 (0 << 28)
#define AT91_PMC_USBDIV_2 (1 << 28)
@@ -151,6 +159,17 @@
#define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */
#define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
+#define AT91C_PMC_ICPPLLA (0xf << 0)
+#define AT91_PMC_ICPPLLA_0 (0 << 0)
+#define AT91_PMC_ICPPLLA_1 (1 << 0)
+#define AT91_PMC_REALLOCK (0x1 << 7)
+#define AT91_PMC_IPLLA (0xf << 8)
+#define AT91_PMC_IPLLA_0 (0 << 8)
+#define AT91_PMC_IPLLA_1 (1 << 8)
+#define AT91_PMC_IPLLA_2 (2 << 8)
+#define AT91_PMC_IPLLA_3 (3 << 8)
+
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
#define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index f0e53610c6c0..da6e825593e6 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -87,6 +87,7 @@
#define SAMA5D3_BASE_PIOC 0xfffff600
#define SAMA5D3_BASE_PIOD 0xfffff800
#define SAMA5D3_BASE_PIOE 0xfffffa00
+#define SAMA5D3_BASE_PMC 0xfffffc00
#define SAMA5D3_BASE_MPDDRC 0xffffea00
#define SAMA5D3_BASE_HSMC 0xffffc000
#define SAMA5D3_BASE_RSTC 0xfffffe00
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* [PATCH 11/11] ARM: at91: microchip-ksz9477-evb: add first stage MMC defconfig
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (9 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 10/11] ARM: at91: microchip-ksz9477-evb: import low level init from at91bootstrap Ahmad Fatoum
@ 2019-01-16 17:45 ` Ahmad Fatoum
2019-01-16 18:47 ` [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Sam Ravnborg
11 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-16 17:45 UTC (permalink / raw)
To: barebox
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
...chip_ksz9477_evb_first_stage_mmc_defconfig | 22 +++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 arch/arm/configs/microchip_ksz9477_evb_first_stage_mmc_defconfig
diff --git a/arch/arm/configs/microchip_ksz9477_evb_first_stage_mmc_defconfig b/arch/arm/configs/microchip_ksz9477_evb_first_stage_mmc_defconfig
new file mode 100644
index 000000000000..b20d4094159b
--- /dev/null
+++ b/arch/arm/configs/microchip_ksz9477_evb_first_stage_mmc_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARCH_SAMA5D3=y
+CONFIG_AT91_MULTI_BOARDS=y
+CONFIG_MACH_MICROCHIP_KSZ9477_EVB=y
+CONFIG_AT91_BOOTSTRAP=y
+CONFIG_BAREBOX_MAX_PBLX_SIZE=0x10000
+CONFIG_RELOCATABLE=y
+CONFIG_PROMPT="BOOT.BIN:"
+CONFIG_SHELL_NONE=y
+# CONFIG_TIMESTAMP is not set
+CONFIG_PBL_CONSOLE=y
+CONFIG_DEFAULT_LOGLEVEL=6
+CONFIG_MCI=y
+CONFIG_MCI_STARTUP=y
+# CONFIG_MCI_WRITE is not set
+CONFIG_MCI_ATMEL=y
+CONFIG_MFD_SYSCON=y
+# CONFIG_FS_RAMFS is not set
+# CONFIG_FS_DEVFS is not set
+CONFIG_FS_FAT=y
+CONFIG_FS_FAT_LFN=y
+CONFIG_BOOTSTRAP_DEVFS=y
+CONFIG_BOOTSTRAP_DISK=y
--
2.20.1
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot
2019-01-16 17:45 [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Ahmad Fatoum
` (10 preceding siblings ...)
2019-01-16 17:45 ` [PATCH 11/11] ARM: at91: microchip-ksz9477-evb: add first stage MMC defconfig Ahmad Fatoum
@ 2019-01-16 18:47 ` Sam Ravnborg
2019-01-17 9:43 ` Ahmad Fatoum
11 siblings, 1 reply; 20+ messages in thread
From: Sam Ravnborg @ 2019-01-16 18:47 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hi Ahmad.
On Wed, Jan 16, 2019 at 06:45:48PM +0100, Ahmad Fatoum wrote:
> This patch series imports the necessary infrastructure out of the
> at91bootstrap project to support first stage usage on the SAMA5.
Very nice, especillay as I have a shiny new SAMA5D4 Xplained Ultra
on my disk waiting to be toyed with.
I will take a closer look in a few days, but most looked good
at first look.
Could I ask you to update the very simple .rst file included
just a few days ago in Documentation/ so we get a better
board description and have the new defconfig also documented.
Sam
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^ permalink raw reply [flat|nested] 20+ messages in thread* Re: [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot
2019-01-16 18:47 ` [PATCH 00/11] ARM: at91: microchip-kz9477-evb: support first stage boot Sam Ravnborg
@ 2019-01-17 9:43 ` Ahmad Fatoum
0 siblings, 0 replies; 20+ messages in thread
From: Ahmad Fatoum @ 2019-01-17 9:43 UTC (permalink / raw)
To: barebox
Hello Sam,
On 16/1/19 19:47, Sam Ravnborg wrote:
> Hi Ahmad.
>
> On Wed, Jan 16, 2019 at 06:45:48PM +0100, Ahmad Fatoum wrote:
>> This patch series imports the necessary infrastructure out of the
>> at91bootstrap project to support first stage usage on the SAMA5.
>
> Very nice, especillay as I have a shiny new SAMA5D4 Xplained Ultra
> on my disk waiting to be toyed with.
:-)
>
> I will take a closer look in a few days, but most looked good
> at first look.
Ok, I'll wait till then with the v2.
>
> Could I ask you to update the very simple .rst file included
> just a few days ago in Documentation/ so we get a better
> board description and have the new defconfig also documented.
Will do.
>
> Sam
>
Cheers
Ahmad
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 20+ messages in thread