* [PATCH 1/7] PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 3:16 ` [PATCH 2/7] ARM: imx8mq: Add node for SRC IP block Andrey Smirnov
` (6 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Port of a Linux commit 29d6b80bc36be62ae38ed8ac3f7a426975fe7dfa
The PCIe IP block has an additional clock, "pcie_aux", that needs to
be controlled by the driver. Add code to support it.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
drivers/pci/pci-imx6.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/pci/pci-imx6.c b/drivers/pci/pci-imx6.c
index 138b4ca8b..85307bad3 100644
--- a/drivers/pci/pci-imx6.c
+++ b/drivers/pci/pci-imx6.c
@@ -65,6 +65,7 @@ struct imx6_pcie {
struct clk *pcie_bus;
struct clk *pcie_phy;
struct clk *pcie;
+ struct clk *pcie_aux;
void __iomem *iomuxc_gpr;
u32 controller_id;
struct reset_control *pciephy_reset;
@@ -299,8 +300,10 @@ static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
{
+ struct device_d *dev = imx6_pcie->pci->dev;
u32 gpr1, gpr1x;
unsigned int offset;
+ int ret;
switch (imx6_pcie->drvdata->variant) {
case IMX6QP:
@@ -323,6 +326,12 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
case IMX7D:
break;
case IMX8MQ:
+ ret = clk_enable(imx6_pcie->pcie_aux);
+ if (ret) {
+ dev_err(dev, "unable to enable pcie_aux clock\n");
+ return ret;
+ }
+
offset = imx6_pcie_grp_offset(imx6_pcie);
/*
* Set the over ride low and enabled
@@ -742,6 +751,13 @@ static int imx6_pcie_probe(struct device_d *dev)
if (iores->start == IMX8MQ_PCIE2_BASE_ADDR)
imx6_pcie->controller_id = 1;
+ imx6_pcie->pcie_aux = clk_get(dev, "pcie_aux");
+ if (IS_ERR(imx6_pcie->pcie_aux)) {
+ dev_err(dev,
+ "pcie_aux clock source missing or invalid\n");
+ return PTR_ERR(imx6_pcie->pcie_aux);
+ }
+
goto imx7d_init;
case IMX7D:
imx6_pcie->iomuxc_gpr = IOMEM(MX7_IOMUXC_GPR_BASE_ADDR);
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 2/7] ARM: imx8mq: Add node for SRC IP block
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
2019-02-27 3:16 ` [PATCH 1/7] PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 3:16 ` [PATCH 3/7] ARM: imx8mq: Add node for GPC " Andrey Smirnov
` (5 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add node for SRC IP block that is missing in upstream DTS. This patch
should be reverted once that changes.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/dts/imx8mq.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 1ddb51f89..90a1d5be0 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -106,6 +106,12 @@
reg = <0x30350000 0x10000>;
clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>;
};
+
+ src: src@30390000 {
+ compatible = "fsl,imx8mq-src", "syscon";
+ reg = <0x30390000 0x10000>;
+ #reset-cells = <1>;
+ };
};
bus@30800000 {
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 3/7] ARM: imx8mq: Add node for GPC IP block
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
2019-02-27 3:16 ` [PATCH 1/7] PCI: imx6: Add code to request/control "pcie_aux" clock for i.MX8MQ Andrey Smirnov
2019-02-27 3:16 ` [PATCH 2/7] ARM: imx8mq: Add node for SRC IP block Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 3:16 ` [PATCH 4/7] ARM: imx8mq: Add nodes for PCIE1 and PCIE2 IP blocks Andrey Smirnov
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add node for GPC IP block that is missing in upstream DTS. This patch
should be reverted once that changes.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/dts/imx8mq.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 90a1d5be0..eece19a7a 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -112,6 +112,22 @@
reg = <0x30390000 0x10000>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mq-gpc", "fsl,imx7d-gpc";
+ reg = <0x303a0000 0x10000>;
+ #power-domain-cells = <1>;
+
+ interrupt-controller;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
};
bus@30800000 {
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 4/7] ARM: imx8mq: Add nodes for PCIE1 and PCIE2 IP blocks
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
` (2 preceding siblings ...)
2019-02-27 3:16 ` [PATCH 3/7] ARM: imx8mq: Add node for GPC " Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 3:16 ` [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2 Andrey Smirnov
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add node for PCE1 and PCIE2 IP block that is missing in upstream DTS. This patch
should be reverted once that changes.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/dts/imx8mq.dtsi | 89 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index eece19a7a..153808b1c 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -4,6 +4,7 @@
* Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
+#include <dt-bindings/reset/imx8mq-reset.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -126,6 +127,35 @@
pgc {
#address-cells = <1>;
#size-cells = <0>;
+
+ /*
+ * As per comment in ATF source code:
+ *
+ * PCIE1 and PCIE2 share the
+ * same reset signal, if we power
+ * down PCIE2, PCIE1 will be held
+ * in reset too.
+ *
+ * So instead of creating two
+ * separate power domains for
+ * PCIE1 and PCIE2. We create
+ * a link between 1 and 10 and
+ * use what was supposed to be
+ * domain 1 as a shared PCIE
+ * power domain powering both
+ * PCIE1 and PCIE2 at the same
+ * time
+ */
+ pgc_pcie_phy: gpc_power_domain@1 {
+ #power-domain-cells = <0>;
+ reg = <1>;
+ power-domains = <&pgc_pcie2_phy>;
+ };
+
+ pgc_pcie2_phy: gpc_power_domain@10 {
+ #power-domain-cells = <0>;
+ reg = <10>;
+ };
};
};
};
@@ -141,6 +171,65 @@
status = "disabled";
};
};
+
+ pcie0: pcie@33800000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33800000 0x400000>,
+ <0x1ff00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ bus-range = <0x00 0xff>;
+ ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie_phy>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ fsl,controller-id = <0>;
+ status = "disabled";
+ };
+
+ pcie1: pcie@33c00000 {
+ compatible = "fsl,imx8mq-pcie";
+ reg = <0x33c00000 0x400000>,
+ <0x27f00000 0x80000>;
+ reg-names = "dbi", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */
+ 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie_phy>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ fsl,controller-id = <1>;
+ status = "disabled";
+ };
};
};
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
` (3 preceding siblings ...)
2019-02-27 3:16 ` [PATCH 4/7] ARM: imx8mq: Add nodes for PCIE1 and PCIE2 IP blocks Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 11:18 ` Lucas Stach
2019-02-27 3:16 ` [PATCH 6/7] ARM: dts: imx8mq: Add nodes for USB IP blocks Andrey Smirnov
` (2 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Enable PCIE1 and PCIE2 used on both Zest and RMB3 boards.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/dts/imx8mq-zii-ultra.dtsi | 62 ++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
index a6b2b8966..83d57916e 100644
--- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
+++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
@@ -37,6 +37,18 @@
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ pcie0_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
+
+ pcie1_refclk: pcie0-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <100000000>;
+ };
};
&fec1 {
@@ -227,6 +239,42 @@
barebox,provide-mac-address = <&fec1 0x640>;
};
+&pcie0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie0>;
+ reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE1_AUX>,
+ <&clk IMX8MQ_CLK_PCIE1_PHY>,
+ <&pcie0_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+};
+
+&pcie1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcie1>;
+ reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&pcie1_refclk>;
+ clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+ status = "okay";
+
+ pcie@0,0 {
+ reg = <0x000000 0 0 0 0>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ /* pcie endpoint 01:00.0 */
+ eth1: intel,i210@pcie0,0 {
+ reg = <0x010000 0 0 0 0>;
+ };
+ };
+};
+
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
@@ -344,6 +392,20 @@
>;
};
+ pinctrl_pcie0: pcie0grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x16
+ >;
+ };
+
+ pinctrl_pcie1: pcie1grp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x76
+ MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
+ >;
+ };
+
pinctrl_reg_usdhc2: regusdhc2grpgpio {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2
2019-02-27 3:16 ` [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2 Andrey Smirnov
@ 2019-02-27 11:18 ` Lucas Stach
2019-02-28 2:42 ` Andrey Smirnov
0 siblings, 1 reply; 13+ messages in thread
From: Lucas Stach @ 2019-02-27 11:18 UTC (permalink / raw)
To: Andrey Smirnov, barebox
Am Dienstag, den 26.02.2019, 19:16 -0800 schrieb Andrey Smirnov:
> Enable PCIE1 and PCIE2 used on both Zest and RMB3 boards.
>
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> arch/arm/dts/imx8mq-zii-ultra.dtsi | 62 ++++++++++++++++++++++++++++++
> 1 file changed, 62 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> index a6b2b8966..83d57916e 100644
> --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
> +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> @@ -37,6 +37,18 @@
> > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > enable-active-high;
> > };
> +
> > + pcie0_refclk: pcie0-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> +
> > + pcie1_refclk: pcie0-refclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + };
> };
>
> &fec1 {
> @@ -227,6 +239,42 @@
> > barebox,provide-mac-address = <&fec1 0x640>;
> };
>
> +&pcie0 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie0>;
> > + reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
> > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> > + <&clk IMX8MQ_CLK_PCIE1_AUX>,
> > + <&clk IMX8MQ_CLK_PCIE1_PHY>,
> > + <&pcie0_refclk>;
> > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > + status = "okay";
> +};
> +
> +&pcie1 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_pcie1>;
> > + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
> > + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> > + <&clk IMX8MQ_CLK_PCIE2_AUX>,
> > + <&clk IMX8MQ_CLK_PCIE2_PHY>,
> > + <&pcie1_refclk>;
> > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > + status = "okay";
> +
> > + pcie@0,0 {
> + reg = <0x000000 0 0 0 0>;
Drop leading zeros from reg properties.
> +
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> +
> + /* pcie endpoint 01:00.0 */
> + eth1: intel,i210@pcie0,0 {
Node name with "," seems strange.
> + reg = <0x010000 0 0 0 0>;
This should also be 0 in the first cell of the reg. The bus number is
defined by the DT node hierarchy. While this might match with the
current implementation, the PCIe enumeration could decide to start the
PCIe bus numbering from a different base during enumeration, so the
PCIe DT nodes should not have fixed/misleading bus numbers. Actually
they are ignored during matching of the nodes.
> + };
> > + };
> +};
> +
> &uart1 {
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_uart1>;
> @@ -344,6 +392,20 @@
> > >;
> > };
>
> > + pinctrl_pcie0: pcie0grp {
> > + fsl,pins = <
> > > + MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x76
> > > + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x16
> > + >;
> > + };
> +
> > + pinctrl_pcie1: pcie1grp {
> > + fsl,pins = <
> > > + MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x76
> > > + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
> > + >;
> > + };
> +
> > pinctrl_reg_usdhc2: regusdhc2grpgpio {
> > fsl,pins = <
> > > MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2
2019-02-27 11:18 ` Lucas Stach
@ 2019-02-28 2:42 ` Andrey Smirnov
0 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-28 2:42 UTC (permalink / raw)
To: Lucas Stach; +Cc: Barebox List
On Wed, Feb 27, 2019 at 3:18 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Dienstag, den 26.02.2019, 19:16 -0800 schrieb Andrey Smirnov:
> > Enable PCIE1 and PCIE2 used on both Zest and RMB3 boards.
> >
> > > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> > arch/arm/dts/imx8mq-zii-ultra.dtsi | 62 ++++++++++++++++++++++++++++++
> > 1 file changed, 62 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> > index a6b2b8966..83d57916e 100644
> > --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
> > +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> > @@ -37,6 +37,18 @@
> > > gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> > > enable-active-high;
> > > };
> > +
> > > + pcie0_refclk: pcie0-refclk {
> > > + compatible = "fixed-clock";
> > > + #clock-cells = <0>;
> > > + clock-frequency = <100000000>;
> > > + };
> > +
> > > + pcie1_refclk: pcie0-refclk {
> > > + compatible = "fixed-clock";
> > > + #clock-cells = <0>;
> > > + clock-frequency = <100000000>;
> > > + };
> > };
> >
> > &fec1 {
> > @@ -227,6 +239,42 @@
> > > barebox,provide-mac-address = <&fec1 0x640>;
> > };
> >
> > +&pcie0 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_pcie0>;
> > > + reset-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
> > > + clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> > > + <&clk IMX8MQ_CLK_PCIE1_AUX>,
> > > + <&clk IMX8MQ_CLK_PCIE1_PHY>,
> > > + <&pcie0_refclk>;
> > > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > > + status = "okay";
> > +};
> > +
> > +&pcie1 {
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_pcie1>;
> > > + reset-gpio = <&gpio1 6 GPIO_ACTIVE_LOW>;
> > > + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
> > > + <&clk IMX8MQ_CLK_PCIE2_AUX>,
> > > + <&clk IMX8MQ_CLK_PCIE2_PHY>,
> > > + <&pcie1_refclk>;
> > > + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
> > > + status = "okay";
> > +
> > > + pcie@0,0 {
> > + reg = <0x000000 0 0 0 0>;
>
> Drop leading zeros from reg properties.
>
> > +
> > > + #address-cells = <3>;
> > > + #size-cells = <2>;
> > +
> > + /* pcie endpoint 01:00.0 */
> > + eth1: intel,i210@pcie0,0 {
>
> Node name with "," seems strange.
>
> > + reg = <0x010000 0 0 0 0>;
>
> This should also be 0 in the first cell of the reg. The bus number is
> defined by the DT node hierarchy. While this might match with the
> current implementation, the PCIe enumeration could decide to start the
> PCIe bus numbering from a different base during enumeration, so the
> PCIe DT nodes should not have fixed/misleading bus numbers. Actually
> they are ignored during matching of the nodes.
>
Noted, will send a fixup for this.
Thanks
Andrey Smirnov
>
> > + };
> > > + };
> > +};
> > +
> > &uart1 {
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&pinctrl_uart1>;
> > @@ -344,6 +392,20 @@
> > > >;
> > > };
> >
> > > + pinctrl_pcie0: pcie0grp {
> > > + fsl,pins = <
> > > > + MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B 0x76
> > > > + MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x16
> > > + >;
> > > + };
> > +
> > > + pinctrl_pcie1: pcie1grp {
> > > + fsl,pins = <
> > > > + MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B 0x76
> > > > + MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x16
> > > + >;
> > > + };
> > +
> > > pinctrl_reg_usdhc2: regusdhc2grpgpio {
> > > fsl,pins = <
> > > > MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [PATCH 6/7] ARM: dts: imx8mq: Add nodes for USB IP blocks
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
` (4 preceding siblings ...)
2019-02-27 3:16 ` [PATCH 5/7] ARM: imx8mq-zii-ultra: Enable PCIE1 and PCIE2 Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 3:16 ` [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes Andrey Smirnov
2019-02-27 7:43 ` [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Sascha Hauer
7 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add node for USB IP block that is missing in upstream DTS. This patch
should be reverted once that changes.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/dts/imx8mq.dtsi | 73 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/imx8mq.dtsi b/arch/arm/dts/imx8mq.dtsi
index 153808b1c..4bb384f66 100644
--- a/arch/arm/dts/imx8mq.dtsi
+++ b/arch/arm/dts/imx8mq.dtsi
@@ -152,6 +152,16 @@
power-domains = <&pgc_pcie2_phy>;
};
+ pgc_otg1: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <2>;
+ };
+
+ pgc_otg2: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <3>;
+ };
+
pgc_pcie2_phy: gpc_power_domain@10 {
#power-domain-cells = <0>;
reg = <10>;
@@ -172,6 +182,69 @@
};
};
+
+ usb_dwc3_0: usb@38100000 {
+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+ reg = <0x38100000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF>,
+ <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+ <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <500000000>, <100000000>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy0>, <&usb3_phy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ power-domains = <&pgc_otg1>;
+ status = "disabled";
+ };
+
+ usb3_phy0: phy@381f0040 {
+ compatible = "fsl,imx8mq-usb-phy";
+ reg = <0x381f0040 0x40>;
+ clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ usb_dwc3_1: usb@38200000 {
+ compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
+ reg = <0x38200000 0x10000>;
+ clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF>,
+ <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>;
+ clock-names = "bus_early", "ref", "suspend";
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
+ <&clk IMX8MQ_CLK_USB_CORE_REF>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
+ <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <500000000>, <100000000>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&usb3_phy1>, <&usb3_phy1>;
+ phy-names = "usb2-phy", "usb3-phy";
+ power-domains = <&pgc_otg2>;
+ status = "disabled";
+ };
+
+ usb3_phy1: phy@382f0040 {
+ compatible = "fsl,imx8mq-usb-phy";
+ reg = <0x382f0040 0x40>;
+ clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>;
+ clock-names = "phy";
+ assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
+ assigned-clock-rates = <100000000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
pcie0: pcie@33800000 {
compatible = "fsl,imx8mq-pcie";
reg = <0x33800000 0x400000>,
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
` (5 preceding siblings ...)
2019-02-27 3:16 ` [PATCH 6/7] ARM: dts: imx8mq: Add nodes for USB IP blocks Andrey Smirnov
@ 2019-02-27 3:16 ` Andrey Smirnov
2019-02-27 11:10 ` Lucas Stach
2019-02-27 7:43 ` [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Sascha Hauer
7 siblings, 1 reply; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-27 3:16 UTC (permalink / raw)
To: barebox; +Cc: Andrey Smirnov
Add nodes for exposed USB ports as well as USB hub connected to one of
them.
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/dts/imx8mq-zii-ultra-rmb3.dts | 4 +++
arch/arm/dts/imx8mq-zii-ultra.dtsi | 34 ++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
index b2b3a560b..78280029b 100644
--- a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
+++ b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
@@ -37,3 +37,7 @@
>;
};
};
+
+&usb_hub {
+ port-swap=<0x01>;
+};
diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
index 83d57916e..d46a26d81 100644
--- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
+++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
@@ -226,6 +226,16 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
+
+ usb_hub: usb2513b@2c {
+ compatible = "microchip,usb2513b";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2513b>;
+ #address-cells=<1>;
+ #size-cells=<1>;
+ reg = <0x2c>;
+ reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
+ };
};
&i2c4 {
@@ -312,6 +322,24 @@
};
};
+&usb_dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb3_phy0 {
+ status = "okay";
+};
+
+&usb_dwc3_1 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb3_phy1 {
+ status = "okay";
+};
+
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
@@ -426,6 +454,12 @@
>;
};
+ pinctrl_usb2513b: usb2513bgrp {
+ fsl,pins = <
+ MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
--
2.20.1
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes
2019-02-27 3:16 ` [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes Andrey Smirnov
@ 2019-02-27 11:10 ` Lucas Stach
2019-02-28 2:43 ` Andrey Smirnov
0 siblings, 1 reply; 13+ messages in thread
From: Lucas Stach @ 2019-02-27 11:10 UTC (permalink / raw)
To: Andrey Smirnov, barebox
Am Dienstag, den 26.02.2019, 19:16 -0800 schrieb Andrey Smirnov:
> Add nodes for exposed USB ports as well as USB hub connected to one of
> them.
>
> > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
> arch/arm/dts/imx8mq-zii-ultra-rmb3.dts | 4 +++
> arch/arm/dts/imx8mq-zii-ultra.dtsi | 34 ++++++++++++++++++++++++++
> 2 files changed, 38 insertions(+)
>
> diff --git a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
> index b2b3a560b..78280029b 100644
> --- a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
> +++ b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
> @@ -37,3 +37,7 @@
> > >;
> > };
> };
> +
> +&usb_hub {
> + port-swap=<0x01>;
This is wrong. With the upstream driver/binding this should be:
swap-dx-lanes = <0>;
> +};
> diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> index 83d57916e..d46a26d81 100644
> --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
> +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> @@ -226,6 +226,16 @@
> > pinctrl-names = "default";
> > pinctrl-0 = <&pinctrl_i2c3>;
> > status = "okay";
> +
> > > + usb_hub: usb2513b@2c {
> > + compatible = "microchip,usb2513b";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usb2513b>;
> > + #address-cells=<1>;
> + #size-cells=<1>;
Why the address-cells and size-cells here? I don't see why this is
needed.
Regards,
Lucas
> + reg = <0x2c>;
> > + reset-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
> > + };
> };
>
> &i2c4 {
> @@ -312,6 +322,24 @@
> > };
> };
>
> +&usb_dwc3_0 {
> > + status = "okay";
> > + dr_mode = "host";
> +};
> +
> +&usb3_phy0 {
> > + status = "okay";
> +};
> +
> +&usb_dwc3_1 {
> > + status = "okay";
> > + dr_mode = "host";
> +};
> +
> +&usb3_phy1 {
> > + status = "okay";
> +};
> +
> &usdhc1 {
> > pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > pinctrl-0 = <&pinctrl_usdhc1>;
> @@ -426,6 +454,12 @@
> > >;
> > };
>
> > + pinctrl_usb2513b: usb2513bgrp {
> > + fsl,pins = <
> > + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
> > + >;
> > + };
> +
> > pinctrl_usdhc1: usdhc1grp {
> > fsl,pins = <
> > > MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes
2019-02-27 11:10 ` Lucas Stach
@ 2019-02-28 2:43 ` Andrey Smirnov
0 siblings, 0 replies; 13+ messages in thread
From: Andrey Smirnov @ 2019-02-28 2:43 UTC (permalink / raw)
To: Lucas Stach; +Cc: Barebox List
On Wed, Feb 27, 2019 at 3:10 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Dienstag, den 26.02.2019, 19:16 -0800 schrieb Andrey Smirnov:
> > Add nodes for exposed USB ports as well as USB hub connected to one of
> > them.
> >
> > > Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> > ---
> > arch/arm/dts/imx8mq-zii-ultra-rmb3.dts | 4 +++
> > arch/arm/dts/imx8mq-zii-ultra.dtsi | 34 ++++++++++++++++++++++++++
> > 2 files changed, 38 insertions(+)
> >
> > diff --git a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
> > index b2b3a560b..78280029b 100644
> > --- a/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
> > +++ b/arch/arm/dts/imx8mq-zii-ultra-rmb3.dts
> > @@ -37,3 +37,7 @@
> > > >;
> > > };
> > };
> > +
> > +&usb_hub {
> > + port-swap=<0x01>;
>
> This is wrong. With the upstream driver/binding this should be:
> swap-dx-lanes = <0>;
>
Ugh, missed this one, will send a fixup.
> > +};
> > diff --git a/arch/arm/dts/imx8mq-zii-ultra.dtsi b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> > index 83d57916e..d46a26d81 100644
> > --- a/arch/arm/dts/imx8mq-zii-ultra.dtsi
> > +++ b/arch/arm/dts/imx8mq-zii-ultra.dtsi
> > @@ -226,6 +226,16 @@
> > > pinctrl-names = "default";
> > > pinctrl-0 = <&pinctrl_i2c3>;
> > > status = "okay";
> > +
> > > > + usb_hub: usb2513b@2c {
> > > + compatible = "microchip,usb2513b";
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&pinctrl_usb2513b>;
> > > + #address-cells=<1>;
> > + #size-cells=<1>;
>
> Why the address-cells and size-cells here? I don't see why this is
> needed.
>
Probably just a leftover from vendor tree where this node has
children. Will fix.
Thanks,
Andrey Smirnov
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^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 0/7] i.MX8MQ PCIe/USB DT changes
2019-02-27 3:16 [PATCH 0/7] i.MX8MQ PCIe/USB DT changes Andrey Smirnov
` (6 preceding siblings ...)
2019-02-27 3:16 ` [PATCH 7/7] ARM: imx8mq-zii-ultra: Add USB related nodes Andrey Smirnov
@ 2019-02-27 7:43 ` Sascha Hauer
7 siblings, 0 replies; 13+ messages in thread
From: Sascha Hauer @ 2019-02-27 7:43 UTC (permalink / raw)
To: Andrey Smirnov; +Cc: barebox
On Tue, Feb 26, 2019 at 07:16:50PM -0800, Andrey Smirnov wrote:
> Everyone:
>
> This series contains the last set of patches needed to enable both
> PCIe and USB on i.MX8MQ in general and ZII boards in
> particular. Hopefully each patch is self-explanatory.
>
> Feedback is welcome!
>
> Thanks,
> Andrey Smirnov
Applied, thanks
Sascha
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^ permalink raw reply [flat|nested] 13+ messages in thread