[PATCH 0/5] ESDHC xload: Prepare for Layerscape support

[PATCH 0/5] ESDHC xload: Prepare for Layerscape support

[Sascha Hauer]

The i.MX ESDHC xload support needs some preparations before Layerscape
support can be added. These are done here, the actual Layerscape support
comes in a later series.

Sascha

Sascha Hauer (5):
  esdhc-xload: Move to drivers/mci
  esdhc-xload: move some register defines to header file
  esdhc-xload: Use static inline io wrappers
  esdhc-xload: Add bigendian support
  esdhc-xload: check for PRSSTAT_BREN only after each block

 arch/arm/mach-imx/Kconfig                     |   2 +
 arch/arm/mach-imx/Makefile                    |   2 +-
 drivers/mci/Kconfig                           |   3 +
 drivers/mci/Makefile                          |   1 +
 .../mci/imx-esdhc-pbl.c                       | 105 +++++++++++-------
 drivers/mci/imx-esdhc.c                       |   9 --
 drivers/mci/imx-esdhc.h                       |   8 ++
 7 files changed, 79 insertions(+), 51 deletions(-)
 rename arch/arm/mach-imx/xload-esdhc.c => drivers/mci/imx-esdhc-pbl.c (79%)

-- 
2.20.1


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[PATCH 1/5] esdhc-xload: Move to drivers/mci

[Sascha Hauer]

The esdhc-xload code will be used by upcoming Layerscape support aswell,
so move it from architecture code to drivers/mci/.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-imx/Kconfig                            |  2 ++
 arch/arm/mach-imx/Makefile                           |  2 +-
 drivers/mci/Kconfig                                  |  3 +++
 drivers/mci/Makefile                                 |  1 +
 .../xload-esdhc.c => drivers/mci/imx-esdhc-pbl.c     | 12 ++++++++----
 5 files changed, 15 insertions(+), 5 deletions(-)
 rename arch/arm/mach-imx/xload-esdhc.c => drivers/mci/imx-esdhc-pbl.c (98%)

diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 3c69ce00a3..3d59228628 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -388,6 +388,7 @@ config MACH_TECHNEXION_WANDBOARD
 	bool "Technexion Wandboard"
 	select ARCH_IMX6
 	select ARM_USE_COMPRESSED_DTB
+	select MCI_IMX_ESDHC_PBL
 
 config MACH_EMBEST_RIOTBOARD
 	bool "Embest RIoTboard"
@@ -439,6 +440,7 @@ config MACH_ZII_RDU1
 config MACH_ZII_RDU2
 	bool "ZII i.MX6Q(+) RDU2"
 	select ARCH_IMX6
+	select MCI_IMX_ESDHC_PBL
 
 config MACH_ZII_IMX8MQ_DEV
 	bool "ZII i.MX8MQ based devices"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 97c54406e6..2b817e5dd8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -26,4 +26,4 @@ obj-$(CONFIG_BAREBOX_UPDATE) += imx-bbu-internal.o
 obj-$(CONFIG_BAREBOX_UPDATE_IMX_EXTERNAL_NAND) += imx-bbu-external-nand.o
 obj-$(CONFIG_RESET_IMX_SRC) += src.o
 lwl-y += cpu_init.o
-pbl-y += xload-spi.o xload-esdhc.o xload-common.o xload-imx-nand.o
+pbl-y += xload-spi.o xload-common.o xload-imx-nand.o
diff --git a/drivers/mci/Kconfig b/drivers/mci/Kconfig
index 2075151d67..cd28fefa43 100644
--- a/drivers/mci/Kconfig
+++ b/drivers/mci/Kconfig
@@ -93,6 +93,9 @@ config MCI_IMX_ESDHC_PIO
 	help
 	  mostly useful for debugging. Normally you should use DMA.
 
+config MCI_IMX_ESDHC_PBL
+	bool
+
 config MCI_OMAP_HSMMC
 	bool "OMAP HSMMC"
 	depends on ARCH_OMAP4 || ARCH_OMAP3 || ARCH_AM33XX
diff --git a/drivers/mci/Makefile b/drivers/mci/Makefile
index fe2c8adbac..f6214c0cbb 100644
--- a/drivers/mci/Makefile
+++ b/drivers/mci/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_MCI_BCM283X)	+= mci-bcm2835.o
 obj-$(CONFIG_MCI_DOVE)		+= dove-sdhci.o
 obj-$(CONFIG_MCI_IMX)		+= imx.o
 obj-$(CONFIG_MCI_IMX_ESDHC)	+= imx-esdhc.o
+pbl-$(CONFIG_MCI_IMX_ESDHC_PBL)	+= imx-esdhc-pbl.o
 obj-$(CONFIG_MCI_MXS)		+= mxs.o
 obj-$(CONFIG_MCI_OMAP_HSMMC)	+= omap_hsmmc.o
 obj-$(CONFIG_MCI_PXA)		+= pxamci.o
diff --git a/arch/arm/mach-imx/xload-esdhc.c b/drivers/mci/imx-esdhc-pbl.c
similarity index 98%
rename from arch/arm/mach-imx/xload-esdhc.c
rename to drivers/mci/imx-esdhc-pbl.c
index 6455cabf98..fb40ecf654 100644
--- a/arch/arm/mach-imx/xload-esdhc.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -14,14 +14,16 @@
 #include <common.h>
 #include <io.h>
 #include <mci.h>
+#include <linux/sizes.h>
+#ifdef CONFIG_ARCH_IMX
 #include <mach/atf.h>
 #include <mach/imx6-regs.h>
 #include <mach/imx8mq-regs.h>
 #include <mach/xload.h>
-#include <linux/sizes.h>
 #include <mach/imx-header.h>
-#include "../../../drivers/mci/sdhci.h"
-#include "../../../drivers/mci/imx-esdhc.h"
+#endif
+#include "sdhci.h"
+#include "imx-esdhc.h"
 
 #define SECTOR_SIZE 512
 
@@ -219,6 +221,7 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
 	return 0;
 }
 
+#ifdef CONFIG_ARCH_IMX
 static int
 esdhc_start_image(struct esdhc *esdhc, ptrdiff_t address, ptrdiff_t entry, u32 offset)
 {
@@ -380,4 +383,5 @@ int imx8_esdhc_start_image(int instance)
 
 	return esdhc_start_image(&esdhc, MX8MQ_DDR_CSD1_BASE_ADDR,
 				 MX8MQ_ATF_BL33_BASE_ADDR, SZ_32K);
-}
\ No newline at end of file
+}
+#endif
-- 
2.20.1


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[PATCH 2/5] esdhc-xload: move some register defines to header file

[Sascha Hauer]

To make them usable for the PBL driver aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc-pbl.c | 1 -
 drivers/mci/imx-esdhc.c     | 9 ---------
 drivers/mci/imx-esdhc.h     | 8 ++++++++
 3 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index fb40ecf654..bcb47afcef 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -29,7 +29,6 @@
 
 #define esdhc_read32(a)                    readl(a)
 #define esdhc_write32(a, v)                writel(v,a)
-#define IMX_SDHCI_MIXCTRL  0x48
 
 struct esdhc {
 	void __iomem *regs;
diff --git a/drivers/mci/imx-esdhc.c b/drivers/mci/imx-esdhc.c
index a9c5440758..cedfb3db42 100644
--- a/drivers/mci/imx-esdhc.c
+++ b/drivers/mci/imx-esdhc.c
@@ -83,15 +83,6 @@
 /* The IP supports HS400 mode */
 #define ESDHC_FLAG_HS400		BIT(9)
 
-
-#define IMX_SDHCI_WML		0x44
-#define IMX_SDHCI_MIXCTRL	0x48
-#define IMX_SDHCI_DLL_CTRL	0x60
-#define IMX_SDHCI_MIX_CTRL_FBCLK_SEL	(BIT(25))
-
-#define ESDHC_DMA_SYSCTL	0x40c /* Layerscape specific */
-#define ESDHC_SYSCTL_DMA_SNOOP  BIT(6)
-
 struct esdhc_soc_data {
 	u32 flags;
 	const char *clkidx;
diff --git a/drivers/mci/imx-esdhc.h b/drivers/mci/imx-esdhc.h
index 9003843abb..9b79346f90 100644
--- a/drivers/mci/imx-esdhc.h
+++ b/drivers/mci/imx-esdhc.h
@@ -58,6 +58,14 @@
 
 #define PIO_TIMEOUT		100000
 
+#define IMX_SDHCI_WML		0x44
+#define IMX_SDHCI_MIXCTRL	0x48
+#define IMX_SDHCI_DLL_CTRL	0x60
+#define IMX_SDHCI_MIX_CTRL_FBCLK_SEL	BIT(25)
+
+#define ESDHC_DMA_SYSCTL	0x40c /* Layerscape specific */
+#define ESDHC_SYSCTL_DMA_SNOOP 	BIT(6)
+
 struct fsl_esdhc_cfg {
 	u32	esdhc_base;
 	u32	no_snoop;
-- 
2.20.1


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[PATCH 3/5] esdhc-xload: Use static inline io wrappers

[Sascha Hauer]

We'll need big endian support for Layerscape, so put the io accessors
into static inline wrappers.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc-pbl.c | 60 ++++++++++++++++++++-----------------
 1 file changed, 33 insertions(+), 27 deletions(-)

diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index bcb47afcef..72df54d685 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -27,14 +27,21 @@
 
 #define SECTOR_SIZE 512
 
-#define esdhc_read32(a)                    readl(a)
-#define esdhc_write32(a, v)                writel(v,a)
-
 struct esdhc {
 	void __iomem *regs;
 	int is_mx6;
 };
 
+static uint32_t esdhc_read32(struct esdhc *esdhc, int reg)
+{
+	return readl(esdhc->regs + reg);
+}
+
+static void esdhc_write32(struct esdhc *esdhc, int reg, uint32_t val)
+{
+	writel(val, esdhc->regs + reg);
+}
+
 static void __udelay(int us)
 {
 	volatile int i;
@@ -66,7 +73,6 @@ static u32 esdhc_xfertyp(struct mci_cmd *cmd, struct mci_data *data)
 
 static int esdhc_do_data(struct esdhc *esdhc, struct mci_data *data)
 {
-	void __iomem *regs = esdhc->regs;
 	char *buffer;
 	u32 databuf;
 	u32 size;
@@ -78,12 +84,12 @@ static int esdhc_do_data(struct esdhc *esdhc, struct mci_data *data)
 
 	timeout = 1000000;
 	size = data->blocksize * data->blocks;
-	irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
+	irqstat = esdhc_read32(esdhc, SDHCI_INT_STATUS);
 
 	while (size) {
-		present = esdhc_read32(regs + SDHCI_PRESENT_STATE) & PRSSTAT_BREN;
+		present = esdhc_read32(esdhc, SDHCI_PRESENT_STATE) & PRSSTAT_BREN;
 		if (present) {
-			databuf = esdhc_read32(regs + SDHCI_BUFFER);
+			databuf = esdhc_read32(esdhc, SDHCI_BUFFER);
 			*((u32 *)buffer) = databuf;
 			buffer += 4;
 			size -= 4;
@@ -103,11 +109,10 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
 {
 	u32	xfertyp, mixctrl;
 	u32	irqstat;
-	void __iomem *regs = esdhc->regs;
 	int ret;
 	int timeout;
 
-	esdhc_write32(regs + SDHCI_INT_STATUS, -1);
+	esdhc_write32(esdhc, SDHCI_INT_STATUS, -1);
 
 	/* Wait at least 8 SD clock cycles before the next command */
 	__udelay(1);
@@ -119,36 +124,36 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
 			return -EINVAL;
 
 		/* Set up for a data transfer if we have one */
-		esdhc_write32(regs + SDHCI_DMA_ADDRESS, (u32)dest);
-		esdhc_write32(regs + SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | SECTOR_SIZE);
+		esdhc_write32(esdhc, SDHCI_DMA_ADDRESS, (u32)dest);
+		esdhc_write32(esdhc, SDHCI_BLOCK_SIZE__BLOCK_COUNT, data->blocks << 16 | SECTOR_SIZE);
 	}
 
 	/* Figure out the transfer arguments */
 	xfertyp = esdhc_xfertyp(cmd, data);
 
 	/* Send the command */
-	esdhc_write32(regs + SDHCI_ARGUMENT, cmd->cmdarg);
+	esdhc_write32(esdhc, SDHCI_ARGUMENT, cmd->cmdarg);
 
 	if (esdhc->is_mx6) {
 		/* write lower-half of xfertyp to mixctrl */
 		mixctrl = xfertyp & 0xFFFF;
 		/* Keep the bits 22-25 of the register as is */
-		mixctrl |= (esdhc_read32(regs + IMX_SDHCI_MIXCTRL) & (0xF << 22));
-		esdhc_write32(regs + IMX_SDHCI_MIXCTRL, mixctrl);
+		mixctrl |= (esdhc_read32(esdhc, IMX_SDHCI_MIXCTRL) & (0xF << 22));
+		esdhc_write32(esdhc, IMX_SDHCI_MIXCTRL, mixctrl);
 	}
 
-	esdhc_write32(regs + SDHCI_TRANSFER_MODE__COMMAND, xfertyp);
+	esdhc_write32(esdhc, SDHCI_TRANSFER_MODE__COMMAND, xfertyp);
 
 	/* Wait for the command to complete */
 	timeout = 10000;
-	while (!(esdhc_read32(regs + SDHCI_INT_STATUS) & IRQSTAT_CC)) {
+	while (!(esdhc_read32(esdhc, SDHCI_INT_STATUS) & IRQSTAT_CC)) {
 		__udelay(1);
 		if (!timeout--)
 			return -ETIMEDOUT;
 	}
 
-	irqstat = esdhc_read32(regs + SDHCI_INT_STATUS);
-	esdhc_write32(regs + SDHCI_INT_STATUS, irqstat);
+	irqstat = esdhc_read32(esdhc, SDHCI_INT_STATUS);
+	esdhc_write32(esdhc, SDHCI_INT_STATUS, irqstat);
 
 	if (irqstat & CMD_ERR)
 		return -EIO;
@@ -157,7 +162,7 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
 		return -ETIMEDOUT;
 
 	/* Copy the response to the response buffer */
-	cmd->response[0] = esdhc_read32(regs + SDHCI_RESPONSE_0);
+	cmd->response[0] = esdhc_read32(esdhc, SDHCI_RESPONSE_0);
 
 	/* Wait until all of the blocks are transferred */
 	if (data) {
@@ -166,11 +171,11 @@ esdhc_send_cmd(struct esdhc *esdhc, struct mci_cmd *cmd, struct mci_data *data)
 			return ret;
 	}
 
-	esdhc_write32(regs + SDHCI_INT_STATUS, -1);
+	esdhc_write32(esdhc, SDHCI_INT_STATUS, -1);
 
 	/* Wait for the bus to be idle */
 	timeout = 10000;
-	while (esdhc_read32(regs + SDHCI_PRESENT_STATE) &
+	while (esdhc_read32(esdhc, SDHCI_PRESENT_STATE) &
 			(PRSSTAT_CICHB | PRSSTAT_CIDHB | PRSSTAT_DLA)) {
 		__udelay(1);
 		if (!timeout--)
@@ -187,14 +192,15 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
 	u32 val;
 	int ret;
 
-	writel(IRQSTATEN_CC | IRQSTATEN_TC | IRQSTATEN_CINT | IRQSTATEN_CTOE |
-			IRQSTATEN_CCE | IRQSTATEN_CEBE | IRQSTATEN_CIE |
-			IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE |
-			IRQSTATEN_DINT, esdhc->regs + SDHCI_INT_ENABLE);
+	esdhc_write32(esdhc, SDHCI_INT_ENABLE,
+		      IRQSTATEN_CC | IRQSTATEN_TC | IRQSTATEN_CINT | IRQSTATEN_CTOE |
+		      IRQSTATEN_CCE | IRQSTATEN_CEBE | IRQSTATEN_CIE |
+		      IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE |
+		      IRQSTATEN_DINT);
 
-	val = readl(esdhc->regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
+	val = esdhc_read32(esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
 	val |= SYSCTL_HCKEN | SYSCTL_IPGEN;
-	writel(val, esdhc->regs + SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
+	esdhc_write32(esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
 
 	cmd.cmdidx = MMC_CMD_READ_MULTIPLE_BLOCK;
 	cmd.cmdarg = 0;
-- 
2.20.1


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[PATCH 4/5] esdhc-xload: Add bigendian support

[Sascha Hauer]

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc-pbl.c | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 72df54d685..33d78aad05 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -29,17 +29,24 @@
 
 struct esdhc {
 	void __iomem *regs;
-	int is_mx6;
+	bool is_mx6;
+	bool is_be;
 };
 
 static uint32_t esdhc_read32(struct esdhc *esdhc, int reg)
 {
-	return readl(esdhc->regs + reg);
+	if (esdhc->is_be)
+		return in_be32(esdhc->regs + reg);
+	else
+		return readl(esdhc->regs + reg);
 }
 
 static void esdhc_write32(struct esdhc *esdhc, int reg, uint32_t val)
 {
-	writel(val, esdhc->regs + reg);
+	if (esdhc->is_be)
+		out_be32(esdhc->regs + reg, val);
+	else
+		writel(val, esdhc->regs + reg);
 }
 
 static void __udelay(int us)
-- 
2.20.1


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[PATCH 5/5] esdhc-xload: check for PRSSTAT_BREN only after each block

[Sascha Hauer]

The BREN bit tells us a watermark level sized buffer is ready for read.
Instead of testing it before each FIFO read we must only check it once
and then read a watermark level sized buffer. This is at least necessary
on Layerscape, otherwise timeouts occur while reading the buffer.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/mci/imx-esdhc-pbl.c | 25 ++++++++++++++++---------
 1 file changed, 16 insertions(+), 9 deletions(-)

diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index 33d78aad05..f77530d310 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -84,28 +84,33 @@ static int esdhc_do_data(struct esdhc *esdhc, struct mci_data *data)
 	u32 databuf;
 	u32 size;
 	u32 irqstat;
-	u32 timeout;
 	u32 present;
 
 	buffer = data->dest;
 
-	timeout = 1000000;
 	size = data->blocksize * data->blocks;
 	irqstat = esdhc_read32(esdhc, SDHCI_INT_STATUS);
 
 	while (size) {
-		present = esdhc_read32(esdhc, SDHCI_PRESENT_STATE) & PRSSTAT_BREN;
-		if (present) {
+		int i;
+		int timeout = 1000000;
+
+		while (1) {
+			present = esdhc_read32(esdhc, SDHCI_PRESENT_STATE) & PRSSTAT_BREN;
+			if (present)
+				break;
+			if (!--timeout) {
+				pr_err("read time out\n");
+				return -ETIMEDOUT;
+			}
+		}
+
+		for (i = 0; i < SECTOR_SIZE / sizeof(uint32_t); i++) {
 			databuf = esdhc_read32(esdhc, SDHCI_BUFFER);
 			*((u32 *)buffer) = databuf;
 			buffer += 4;
 			size -= 4;
 		}
-
-		if (!timeout--) {
-			pr_err("read time out\n");
-			return -ETIMEDOUT;
-		}
 	}
 
 	return 0;
@@ -205,6 +210,8 @@ static int esdhc_read_blocks(struct esdhc *esdhc, void *dst, size_t len)
 		      IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE |
 		      IRQSTATEN_DINT);
 
+	esdhc_write32(esdhc, IMX_SDHCI_WML, 0x0);
+
 	val = esdhc_read32(esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
 	val |= SYSCTL_HCKEN | SYSCTL_IPGEN;
 	esdhc_write32(esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
-- 
2.20.1


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