[PATCH] ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()

[PATCH] ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()

[Andrey Smirnov]

There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3,
SCTLR will be in a state we expect it to be. Add code to reset it to a
known state, so we'd always start form clean slate. This is also
matches what we've been doing non 64-bit ARMs.

Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon
appear to have different mask ROM behaviour where it now leaves MMU
enabled if no valid boot source is found. Page table it sets up
doesn't include DDR range, so trying to bootstrap the device via
JTAG/OpenOCD results in an abort.

The value for SCTLR_ELx_FLAGS was taken from Linux kernel.

Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
 arch/arm/cpu/lowlevel_64.S    |  7 +++++++
 arch/arm/include/asm/system.h | 20 ++++++++++++++++++++
 2 files changed, 27 insertions(+)

diff --git a/arch/arm/cpu/lowlevel_64.S b/arch/arm/cpu/lowlevel_64.S
index af1cd8b5b..6a23132ed 100644
--- a/arch/arm/cpu/lowlevel_64.S
+++ b/arch/arm/cpu/lowlevel_64.S
@@ -12,6 +12,13 @@ ENTRY(arm_cpu_lowlevel_init)
 	orr	x0, x0, #(1 << 10)	/* 64-bit EL2 */
 	msr	scr_el3, x0
 	msr	cptr_el3, xzr
+
+	mrs	x0, sctlr_el3
+	ldr	x1, =SCTLR_ELx_FLAGS
+	bic	x0, x0, x1
+	msr	sctlr_el3, x0
+	isb
+
 	b	done
 
 2:
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index ef9cb98bf..a0180f2df 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -1,6 +1,26 @@
 #ifndef __ASM_ARM_SYSTEM_H
 #define __ASM_ARM_SYSTEM_H
 
+#include <linux/const.h>
+
+/* Common SCTLR_ELx flags. */
+#define SCTLR_ELx_DSSBS	(_BITUL(44))
+#define SCTLR_ELx_ENIA	(_BITUL(31))
+#define SCTLR_ELx_ENIB	(_BITUL(30))
+#define SCTLR_ELx_ENDA	(_BITUL(27))
+#define SCTLR_ELx_EE    (_BITUL(25))
+#define SCTLR_ELx_IESB	(_BITUL(21))
+#define SCTLR_ELx_WXN	(_BITUL(19))
+#define SCTLR_ELx_ENDB	(_BITUL(13))
+#define SCTLR_ELx_I	(_BITUL(12))
+#define SCTLR_ELx_SA	(_BITUL(3))
+#define SCTLR_ELx_C	(_BITUL(2))
+#define SCTLR_ELx_A	(_BITUL(1))
+#define SCTLR_ELx_M	(_BITUL(0))
+
+#define SCTLR_ELx_FLAGS	(SCTLR_ELx_M  | SCTLR_ELx_A | SCTLR_ELx_C | \
+			 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_IESB)
+
 #if __LINUX_ARM_ARCH__ >= 7
 #define isb() __asm__ __volatile__ ("isb" : : : "memory")
 #ifdef CONFIG_CPU_64v8
-- 
2.20.1


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Re: [PATCH] ARM: aarch64: lowlevel: Reset SCTLR_EL3 in arm_cpu_lowlevel_init()

[Sascha Hauer]

On Tue, Apr 23, 2019 at 11:32:48PM -0700, Andrey Smirnov wrote:
> There's no guarantee that when arm_cpu_lowlevel_init() runs at EL3,
> SCTLR will be in a state we expect it to be. Add code to reset it to a
> known state, so we'd always start form clean slate. This is also
> matches what we've been doing non 64-bit ARMs.
> 
> Real word motivation for this patch is i.MX8MQ whose rev 2.1 silicon
> appear to have different mask ROM behaviour where it now leaves MMU
> enabled if no valid boot source is found. Page table it sets up
> doesn't include DDR range, so trying to bootstrap the device via
> JTAG/OpenOCD results in an abort.
> 
> The value for SCTLR_ELx_FLAGS was taken from Linux kernel.
> 
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
> ---
>  arch/arm/cpu/lowlevel_64.S    |  7 +++++++
>  arch/arm/include/asm/system.h | 20 ++++++++++++++++++++
>  2 files changed, 27 insertions(+)

Applied, thanks

Sascha


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