From: Rouven Czerwinski <r.czerwinski@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>,
Rouven Czerwinski <r.czerwinski@pengutronix.de>
Subject: [PATCH v2] ARM: imx: disable IPU QoS setup for correct SoCs
Date: Tue, 30 Apr 2019 05:15:24 +0200 [thread overview]
Message-ID: <20190430031524.18810-1-r.czerwinski@pengutronix.de> (raw)
The condition was introduced in 4e6e8f73e9 ("ARM: imx6: don't
execute IPU QoS setup on MX6 SX/SL"), but instead it bails at
the Solo, not the SX and SL.
The original intent was most probably to add an exception for
the i.MX6 Solo as well, so everything else is skipped, including
the SX, SL and now the UL and ULL. Fix the code to reflect this.
On the SX, SL, UL, ULL, this now avoids writes to memory, which
isn't described in the datasheets. On the S, it now configures
the QoS settings.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
Signed-off-by: Rouven Czerwinski <r.czerwinski@pengutronix.de>
---
arch/arm/mach-imx/imx6.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 01b4274ed3..e898be9ab5 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -117,7 +117,7 @@ static void imx6_setup_ipu_qos(void)
uint32_t val;
if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
- !cpu_mx6_is_mx6dl() && cpu_mx6_is_mx6s())
+ !cpu_mx6_is_mx6dl() && !cpu_mx6_is_mx6s())
return;
val = readl(iomux + IOMUXC_GPR4);
--
2.21.0
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next reply other threads:[~2019-04-30 3:15 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-30 3:15 Rouven Czerwinski [this message]
2019-05-06 6:31 ` Sascha Hauer
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