* [PATCH 01/10] mci: imx-esdhc-pbl: ls1046a: Set better divider values
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
@ 2019-05-08 9:02 ` Sascha Hauer
2019-05-08 9:02 ` [PATCH 02/10] ARM: Layerscape: TQMLS1046a: Set cpo_sample value Sascha Hauer
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:02 UTC (permalink / raw)
To: Barebox List
MMC Frequency was set to something like 55MHz. This doesn't work for all
SD cards. Set to 25MHz which is supported by all SD cards.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/mci/imx-esdhc-pbl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mci/imx-esdhc-pbl.c b/drivers/mci/imx-esdhc-pbl.c
index f7f8c3348d..2bfe5c2f37 100644
--- a/drivers/mci/imx-esdhc-pbl.c
+++ b/drivers/mci/imx-esdhc-pbl.c
@@ -445,7 +445,7 @@ int ls1046a_esdhc_start_image(unsigned long r0, unsigned long r1, unsigned long
*/
val = esdhc_read32(&esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET);
val &= ~0x0000fff0;
- val |= (2 << 8) | (6 << 4);
+ val |= (8 << 8) | (3 << 4);
esdhc_write32(&esdhc, SDHCI_CLOCK_CONTROL__TIMEOUT_CONTROL__SOFTWARE_RESET, val);
esdhc_write32(&esdhc, ESDHC_DMA_SYSCTL, ESDHC_SYSCTL_DMA_SNOOP);
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 02/10] ARM: Layerscape: TQMLS1046a: Set cpo_sample value
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
2019-05-08 9:02 ` [PATCH 01/10] mci: imx-esdhc-pbl: ls1046a: Set better divider values Sascha Hauer
@ 2019-05-08 9:02 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 03/10] ddr: fsl: move fsl_ddr_set_memctl_regs prototype to include/ Sascha Hauer
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:02 UTC (permalink / raw)
To: Barebox List
Starting the board issues the warning:
WARN: pls set popts->cpo_sample = 0x48
So set the value to the desired value.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/lowlevel.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index 044d6a418d..fb3a3f3591 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -116,7 +116,7 @@ found:
DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
/* optimize cpo for erratum A-009942 */
- popts->cpo_sample = 0x61;
+ popts->cpo_sample = 0x48;
}
static struct dimm_params dimm_params[] = {
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 03/10] ddr: fsl: move fsl_ddr_set_memctl_regs prototype to include/
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
2019-05-08 9:02 ` [PATCH 01/10] mci: imx-esdhc-pbl: ls1046a: Set better divider values Sascha Hauer
2019-05-08 9:02 ` [PATCH 02/10] ARM: Layerscape: TQMLS1046a: Set cpo_sample value Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 04/10] ARM: Layerscape: TQMLS1046a: Use static DDR settings Sascha Hauer
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
fsl_ddr_set_memctl_regs() is not only used internally in the DDR
controller driver, but can also be called by the boards to configure
a static setting. Move the prototype to include/ where it can be
used by board code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/ddr/fsl/fsl_ddr.h | 2 --
include/soc/fsl/fsl_ddr_sdram.h | 1 +
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/ddr/fsl/fsl_ddr.h b/drivers/ddr/fsl/fsl_ddr.h
index ee6069d812..ab991a5bf4 100644
--- a/drivers/ddr/fsl/fsl_ddr.h
+++ b/drivers/ddr/fsl/fsl_ddr.h
@@ -227,8 +227,6 @@ unsigned int mclk_to_picos(struct fsl_ddr_controller *c, unsigned int mclk);
unsigned int get_memory_clk_period_ps(struct fsl_ddr_controller *c);
unsigned int picos_to_mclk(struct fsl_ddr_controller *c, unsigned int picos);
-void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step);
-
void erratum_a009942_check_cpo(void);
#endif
diff --git a/include/soc/fsl/fsl_ddr_sdram.h b/include/soc/fsl/fsl_ddr_sdram.h
index 07d0af96fc..80508ef5d5 100644
--- a/include/soc/fsl/fsl_ddr_sdram.h
+++ b/include/soc/fsl/fsl_ddr_sdram.h
@@ -540,6 +540,7 @@ struct fsl_ddr_info {
};
phys_size_t fsl_ddr_sdram(struct fsl_ddr_info *pinfo);
+void fsl_ddr_set_memctl_regs(struct fsl_ddr_controller *c, int step);
#ifdef CONFIG_SYS_FSL_DDR_LE
#define ddr_in32(a) in_le32(a)
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 04/10] ARM: Layerscape: TQMLS1046a: Use static DDR settings
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (2 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 03/10] ddr: fsl: move fsl_ddr_set_memctl_regs prototype to include/ Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 05/10] ARM: Layerscape: TQMLS1046a: Update device tree files from tq repository Sascha Hauer
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
TQ prefers static values in their U-Boot, so use these values in
barebox aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/lowlevel.c | 82 ++++++++++++++++++++++-----
1 file changed, 68 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boards/tqmls1046a/lowlevel.c b/arch/arm/boards/tqmls1046a/lowlevel.c
index fb3a3f3591..88744a8f9b 100644
--- a/arch/arm/boards/tqmls1046a/lowlevel.c
+++ b/arch/arm/boards/tqmls1046a/lowlevel.c
@@ -169,37 +169,91 @@ static struct fsl_ddr_controller ddrc[] = {
.erratum_A009942 = 1,
.chip_selects_per_ctrl = 4,
.board_options = ddr_board_options,
+ .fsl_ddr_config_reg = {
+ .cs[0].bnds = 0x0000007F,
+ .cs[0].config = 0x80010312,
+ .cs[0].config_2 = 0x00000000,
+ .cs[1].bnds = 0x00000000,
+ .cs[1].config = 0x00000000,
+ .cs[1].config_2 = 0x00000000,
+ .cs[2].bnds = 0x00000000,
+ .cs[2].config = 0x00000000,
+ .cs[2].config_2 = 0x00000000,
+ .cs[3].bnds = 0x00000000,
+ .cs[3].config = 0x00000000,
+ .cs[3].config_2 = 0x00000000,
+ .timing_cfg_3 = 0x020F1100,
+ .timing_cfg_0 = 0x77660008,
+ .timing_cfg_1 = 0xF1FCC265,
+ .timing_cfg_2 = 0x0059415E,
+ .ddr_sdram_cfg = 0x65000000,
+ .ddr_sdram_cfg_2 = 0x00401150,
+ .ddr_sdram_cfg_3 = 0x00000000,
+ .ddr_sdram_mode = 0x03010625,
+ .ddr_sdram_mode_2 = 0x00100200,
+ .ddr_sdram_mode_3 = 0x00010625,
+ .ddr_sdram_mode_4 = 0x00100200,
+ .ddr_sdram_mode_5 = 0x00010625,
+ .ddr_sdram_mode_6 = 0x00100200,
+ .ddr_sdram_mode_7 = 0x00010625,
+ .ddr_sdram_mode_8 = 0x00100200,
+ .ddr_sdram_mode_9 = 0x00000500,
+ .ddr_sdram_mode_10 = 0x04400000,
+ .ddr_sdram_mode_11 = 0x00000400,
+ .ddr_sdram_mode_12 = 0x04400000,
+ .ddr_sdram_mode_13 = 0x00000400,
+ .ddr_sdram_mode_14 = 0x04400000,
+ .ddr_sdram_mode_15 = 0x00000400,
+ .ddr_sdram_mode_16 = 0x04400000,
+ .ddr_sdram_interval = 0x0F3C0000,
+ .ddr_data_init = 0xDEADBEEF,
+ .ddr_sdram_clk_cntl = 0x02000000,
+ .ddr_init_addr = 0x00000000,
+ .ddr_init_ext_addr = 0x00000000,
+ .timing_cfg_4 = 0x00224002,
+ .timing_cfg_5 = 0x04401400,
+ .timing_cfg_6 = 0x00000000,
+ .timing_cfg_7 = 0x25500000,
+ .timing_cfg_8 = 0x03335A00,
+ .timing_cfg_9 = 0x00000000,
+ .ddr_zq_cntl = 0x8A090705,
+ .ddr_wrlvl_cntl = 0x86550609,
+ .ddr_wrlvl_cntl_2 = 0x09080806,
+ .ddr_wrlvl_cntl_3 = 0x06040409,
+ .ddr_sr_cntr = 0x00000000,
+ .ddr_sdram_rcw_1 = 0x00000000,
+ .ddr_sdram_rcw_2 = 0x00000000,
+ .ddr_sdram_rcw_3 = 0x00000000,
+ .ddr_cdr1 = 0x80080000,
+ .ddr_cdr2 = 0x000000C0,
+ .dq_map_0 = 0x00000000,
+ .dq_map_1 = 0x00000000,
+ .dq_map_2 = 0x00000000,
+ .dq_map_3 = 0x00000000,
+ .debug[28] = 0x00700046,
+ },
},
};
-static struct fsl_ddr_info ls1046a_info = {
- .num_ctrls = ARRAY_SIZE(ddrc),
- .c = ddrc,
-};
-
extern char __dtb_fsl_tqmls1046a_mbls10xxa_start[];
-static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize)
+static noinline __noreturn void tqmls1046a_r_entry(void)
{
unsigned long membase = LS1046A_DDR_SDRAM_BASE;
- if (get_pc() >= membase) {
- if (memsize + membase >= 0x100000000)
- memsize = 0x100000000 - membase;
-
+ if (get_pc() >= membase)
barebox_arm_entry(membase, 0x80000000,
__dtb_fsl_tqmls1046a_mbls10xxa_start);
- }
arm_cpu_lowlevel_init();
debug_ll_init();
ls1046a_init_lowlevel();
- memsize = fsl_ddr_sdram(&ls1046a_info);
+ fsl_ddr_set_memctl_regs(&ddrc[0], 0);
ls1046a_errata_post_ddr();
- ls1046a_esdhc_start_image(memsize, 0, 0);
+ ls1046a_esdhc_start_image(0, 0, 0);
pr_err("Booting failed\n");
@@ -213,5 +267,5 @@ __noreturn void tqmls1046a_entry(unsigned long r0, unsigned long r1, unsigned lo
relocate_to_current_adr();
setup_c();
- tqmls1046a_r_entry(r0);
+ tqmls1046a_r_entry();
}
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 05/10] ARM: Layerscape: TQMLS1046a: Update device tree files from tq repository
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (3 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 04/10] ARM: Layerscape: TQMLS1046a: Use static DDR settings Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 06/10] ARM: Layerscape: TQMLS1046a: Unify SD and eMMC images Sascha Hauer
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
Update TQMLS1046a device tree files from TQ repository as of rocko.TQMLS1046A.BSP.SW.0002
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts | 67 +++++++++++++++--------
arch/arm/dts/fsl-tqmls1046a.dtsi | 4 +-
2 files changed, 46 insertions(+), 25 deletions(-)
diff --git a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
index f21479eef8..d783d50baf 100644
--- a/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
+++ b/arch/arm/dts/fsl-tqmls1046a-mbls10xxa.dts
@@ -20,6 +20,12 @@
serial0 = &duart0;
serial1 = &duart1;
mmc0 = &esdhc;
+ qsgmii_s1_p1 = &qsgmii1_phy1;
+ qsgmii_s1_p2 = &qsgmii1_phy2;
+ qsgmii_s2_p1 = &qsgmii2_phy1;
+ qsgmii_s2_p2 = &qsgmii2_phy2;
+ qsgmii_s2_p3 = &qsgmii2_phy3;
+ qsgmii_s2_p4 = &qsgmii2_phy4;
};
chosen {
@@ -66,6 +72,14 @@
status = "okay";
};
+&esdhc {
+ mmc-hs200-1_8v;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+};
+
&i2c3 {
status = "okay";
@@ -132,43 +146,40 @@
&fman0 {
status = "okay";
- ethernet@e0000 {
- status = "disabled";
+ ethernet@e0000 { /* EMAC.1 */
+ phy-connection-type = "sgmii";
+
};
- ethernet@e2000 {
- phy-handle = <&qsgmii1_phy2>;
+ ethernet@e2000 { /* EMAC.2 */
phy-connection-type = "sgmii";
};
- ethernet@e4000 {
+ ethernet@e4000 { /* EMAC.3 */
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
phy-mode = "rgmii-id";
};
- ethernet@e6000 {
+ ethernet@e6000 { /* EMAC.4 */
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
phy-mode = "rgmii-id";
};
- ethernet@e8000 {
- status = "disabled";
+ ethernet@e8000 { /* EMAC.5 */
+ phy-connection-type = "sgmii";
};
- ethernet@ea000 {
- phy-handle = <&qsgmii2_phy2>;
+ ethernet@ea000 { /* EMAC.6 */
phy-connection-type = "sgmii";
};
- ethernet@f0000 {
- phy-handle = <&qsgmii1_phy1>;
+ ethernet@f0000 { /* EMAC.9 */
phy-connection-type = "sgmii";
};
- ethernet@f2000 {
- phy-handle = <&qsgmii2_phy1>;
+ ethernet@f2000 { /* EMAC.10 */
phy-connection-type = "sgmii";
};
@@ -212,6 +223,13 @@
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
};
+ rgmii_phy2: ethernet-phy@0c {
+ reg = <0x0c>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
+ };
+
qsgmii1_phy1: ethernet-phy@1c {
reg = <0x1c>;
};
@@ -219,15 +237,6 @@
qsgmii1_phy2: ethernet-phy@1d {
reg = <0x1d>;
};
- };
-
- mdio@fd000 {
- rgmii_phy2: ethernet-phy@0c {
- reg = <0x0c>;
- ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
- ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>;
- };
qsgmii2_phy1: ethernet-phy@00 {
reg = <0x00>;
@@ -236,5 +245,17 @@
qsgmii2_phy2: ethernet-phy@01 {
reg = <0x01>;
};
+
+ qsgmii2_phy3: ethernet-phy@02 {
+ reg = <0x02>;
+ };
+
+ qsgmii2_phy4: ethernet-phy@03 {
+ reg = <0x03>;
+ };
+ };
+
+ mdio@fd000 {
+ status = "disabled";
};
};
diff --git a/arch/arm/dts/fsl-tqmls1046a.dtsi b/arch/arm/dts/fsl-tqmls1046a.dtsi
index 4717e66857..0ea2612cbf 100644
--- a/arch/arm/dts/fsl-tqmls1046a.dtsi
+++ b/arch/arm/dts/fsl-tqmls1046a.dtsi
@@ -40,15 +40,15 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
- spi-max-frequency = <108000000>;
+ spi-max-frequency = <62500000>;
reg = <0>;
};
qflash1: mx66u51235f@1 {
#address-cells = <1>;
#size-cells = <1>;
- spi-max-frequency = <108000000>;
compatible = "jedec,spi-nor";
+ spi-max-frequency = <62500000>;
reg = <1>;
};
};
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 06/10] ARM: Layerscape: TQMLS1046a: Unify SD and eMMC images
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (4 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 05/10] ARM: Layerscape: TQMLS1046a: Update device tree files from tq repository Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 07/10] ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4 Sascha Hauer
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
TQ has unified SD and eMMC images in their U-Boot. Do the same in
barebox aswell.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
.../tqmls1046a_rcw_emmc_3333_5559.cfg | 84 -------------------
.../tqmls1046a_rcw_sd_3333_5559.cfg | 14 ++--
images/Makefile.layerscape | 7 +-
3 files changed, 8 insertions(+), 97 deletions(-)
delete mode 100644 arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg
deleted file mode 100644
index 6c72d001c3..0000000000
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg
+++ /dev/null
@@ -1,84 +0,0 @@
-# RCW values
-# 0: 1 - SYS_PLL_CFG : 0 [0x0 / 0b00]
-# 2: 6 - SYS_PLL_RAT : 6 [0x6 / 0b00110]
-# 8: 9 - MEM_PLL_CFG : 0 [0x0 / 0b00]
-# 10: 15 - MEM_PLL_RAT : 20 [0x14 / 0b010100]
-# 24: 25 - CGA_PLL1_CFG : 0 [0x0 / 0b00]
-# 26: 31 - CGA_PLL1_RAT : 16 [0x10 / 0b010000]
-# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
-# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
-# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
-# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
-# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
-# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
-# 168:169 - SRDS_PLL_PD_S1 : 0 [0x0 / 0b00]
-# 170:171 - SRDS_PLL_PD_S2 : 0 [0x0 / 0b00]
-# 176:177 - SRDS_DIV_PEX_S1 : 1 [0x1 / 0b01]
-# 178:179 - SRDS_DIV_PEX_S2 : 1 [0x1 / 0b01]
-# 186:187 - DDR_REFCLK_SEL : 0 [0x0 / 0b00]
-# 188:188 - SRDS_REFCLK_SEL_S1 : 0 [0x0 / 0b0]
-# 189:189 - SRDS_REFCLK_SEL_S2 : 0 [0x0 / 0b0]
-# 190:191 - DDR_FDBK_MULT : 2 [0x2 / 0b10]
-# 192:195 - PBI_SRC : 6 [0x6 / 0b0110]
-# 201:201 - BOOT_HO : 0 [0x0 / 0b0]
-# 202:202 - SB_EN : 0 [0x0 / 0b0]
-# 203:211 - IFC_MODE : 64 [0x40 / 0b001000000]
-# 224:226 - HWA_CGA_M1_CLK_SEL : 6 [0x6 / 0b110]
-# 230:231 - DRAM_LAT : 1 [0x1 / 0b01]
-# 232:232 - DDR_RATE : 0 [0x0 / 0b0]
-# 234:234 - DDR_RSV0 : 0 [0x0 / 0b0]
-# 242:242 - SYS_PLL_SPD : 0 [0x0 / 0b0]
-# 243:243 - MEM_PLL_SPD : 0 [0x0 / 0b0]
-# 244:244 - CGA_PLL1_SPD : 0 [0x0 / 0b0]
-# 245:245 - CGA_PLL2_SPD : 0 [0x0 / 0b0]
-# 264:266 - HOST_AGT_PEX : 0 [0x0 / 0b000]
-# 288:295 - GP_INFO1 : 0 [0x00 / 0b00000000]
-# 299:319 - GP_INFO2 : 0 [0x00000 / 0b000000000000000000000]
-# 354:356 - UART_EXT : 0 [0x0 / 0b000]
-# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
-# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
-# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
-# 369:369 - ASLEEP : 0 [0x0 / 0b0]
-# 370:370 - RTC : 0 [0x0 / 0b0]
-# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
-# 372:372 - IRQ_OUT : 1 [0x1 / 0b1]
-# 373:381 - IRQ_BASE : 0 [0x00 / 0b000000000]
-# 382:383 - SPI_BASE : 0 [0x0 / 0b00]
-# 384:386 - IFC_GRP_A_EXT : 1 [0x1 / 0b001]
-# 393:395 - IFC_GRP_D_EXT : 0 [0x0 / 0b000]
-# 396:398 - IFC_GRP_E1_EXT : 0 [0x0 / 0b000]
-# 399:401 - IFC_GRP_F_EXT : 1 [0x1 / 0b001]
-# 405:405 - IFC_GRP_E1_BASE : 0 [0x0 / 0b0]
-# 407:407 - IFC_GRP_D_BASE : 0 [0x0 / 0b0]
-# 412:413 - IFC_GRP_A_BASE : 0 [0x0 / 0b00]
-# 415:415 - IFC_A_22_24 : 0 [0x0 / 0b0]
-# 416:418 - EC1 : 0 [0x0 / 0b000]
-# 419:421 - EC2 : 0 [0x0 / 0b000]
-# 422:423 - LVDD_VSEL : 1 [0x1 / 0b01]
-# 424:424 - I2C_IPGCLK_SEL : 0 [0x0 / 0b0]
-# 425:425 - EM1 : 0 [0x0 / 0b0]
-# 426:426 - EM2 : 0 [0x0 / 0b0]
-# 427:427 - EMI2_DMODE : 1 [0x1 / 0b1]
-# 428:428 - EMI2_CMODE : 0 [0x0 / 0b0]
-# 429:429 - USB_DRVVBUS : 0 [0x0 / 0b0]
-# 430:430 - USB_PWRFAULT : 0 [0x0 / 0b0]
-# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01]
-# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10]
-# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1]
-# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00]
-# 441:443 - IIC2_BASE : 0 [0x0 / 0b000]
-# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0]
-# 445:447 - IIC2_EXT : 2 [0x2 / 0b010]
-# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000]
-# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001]
-
-
-#PBL preamble and RCW header
-aa55aa55 01ee0100
-# RCW
-0c140010 0e000000 00000000 00000000
-33335559 f0005002 60040000 c1000000
-00000000 00000000 00000000 00028800
-20004000 01103202 00000096 00000001
diff --git a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
index 4ef6d576ed..72ab1cd7d7 100644
--- a/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
+++ b/arch/arm/boards/tqmls1046a/tqmls1046a_rcw_sd_3333_5559.cfg
@@ -8,7 +8,7 @@
# 32: 33 - CGA_PLL2_CFG : 0 [0x0 / 0b00]
# 34: 39 - CGA_PLL2_RAT : 14 [0xe / 0b001110]
# 96: 99 - C1_PLL_SEL : 0 [0x0 / 0b0000]
-# 128:143 - SRDS_PRTCL_S1 : 13107 [0x3333 / 0b0011001100110011]
+# 128:143 - SRDS_PRTCL_S1 : 4403 [0x1133 / 0b0001000100110011]
# 144:159 - SRDS_PRTCL_S2 : 21849 [0x5559 / 0b0101010101011001]
# 160:161 - SRDS_PLL_REF_CLK_SEL_S1 : 3 [0x3 / 0b11]
# 162:163 - SRDS_PLL_REF_CLK_SEL_S2 : 3 [0x3 / 0b11]
@@ -39,7 +39,7 @@
# 357:359 - IRQ_EXT : 0 [0x0 / 0b000]
# 360:362 - SPI_EXT : 0 [0x0 / 0b000]
# 363:365 - SDHC_EXT : 0 [0x0 / 0b000]
-# 366:368 - UART_BASE : 5 [0x5 / 0b101]
+# 366:368 - UART_BASE : 6 [0x6 / 0b110]
# 369:369 - ASLEEP : 0 [0x0 / 0b0]
# 370:370 - RTC : 0 [0x0 / 0b0]
# 371:371 - SDHC_BASE : 0 [0x0 / 0b0]
@@ -67,10 +67,10 @@
# 433:434 - TVDD_VSEL : 1 [0x1 / 0b01]
# 435:436 - DVDD_VSEL : 2 [0x2 / 0b10]
# 438:438 - EMI1_DMODE : 1 [0x1 / 0b1]
-# 439:440 - EVDD_VSEL : 2 [0x2 / 0b10]
+# 439:440 - EVDD_VSEL : 0 [0x0 / 0b00]
# 441:443 - IIC2_BASE : 0 [0x0 / 0b000]
# 444:444 - EMI1_CMODE : 0 [0x0 / 0b0]
-# 445:447 - IIC2_EXT : 1 [0x1 / 0b001]
+# 445:447 - IIC2_EXT : 2 [0x2 / 0b010]
# 472:481 - SYSCLK_FREQ : 600 [0x258 / 0b1001011000]
# 509:511 - HWA_CGA_M2_CLK_SEL : 1 [0x1 / 0b001]
@@ -79,6 +79,6 @@
aa55aa55 01ee0100
# RCW
0c140010 0e000000 00000000 00000000
-33335559 f0005002 60040000 c1000000
-00000000 00000000 00000000 00028800
-20004000 01103301 00000096 00000001
+11335559 f0005002 60040000 c1000000
+00000000 00000000 00000000 00030800
+20004000 01103202 00000096 00000001
diff --git a/images/Makefile.layerscape b/images/Makefile.layerscape
index 47df3777f0..59f672791b 100644
--- a/images/Makefile.layerscape
+++ b/images/Makefile.layerscape
@@ -45,15 +45,10 @@ $(obj)/barebox-tqmls1046a-sd.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg
$(call if_changed,lspbl_image)
-$(obj)/barebox-tqmls1046a-emmc.image: $(obj)/start_tqmls1046a.pblb \
- $(board)/tqmls1046a/tqmls1046a_rcw_emmc_3333_5559.cfg \
- $(board)/tqmls1046a/tqmls1046a_pbi_sd.cfg
- $(call if_changed,lspbl_image)
-
$(obj)/barebox-tqmls1046a-qspi.image: $(obj)/start_tqmls1046a.pblb \
$(board)/tqmls1046a/tqmls1046a_rcw_qspi_3333_5559.cfg \
$(board)/tqmls1046a/tqmls1046a_pbi_qspi.cfg
$(call if_changed,lspbl_image)
-image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image barebox-tqmls1046a-emmc.image \
+image-$(CONFIG_MACH_TQMLS1046A) += barebox-tqmls1046a-sd.image \
barebox-tqmls1046a-qspi.image barebox-tqmls1046a-2nd.image
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 07/10] ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (5 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 06/10] ARM: Layerscape: TQMLS1046a: Unify SD and eMMC images Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 08/10] filetype: Detect Layerscape PBL images Sascha Hauer
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
With this the I2C mux on i2c4 works properly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/boards/tqmls1046a/board.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boards/tqmls1046a/board.c b/arch/arm/boards/tqmls1046a/board.c
index 5d6d5ad62c..4fc8e76d65 100644
--- a/arch/arm/boards/tqmls1046a/board.c
+++ b/arch/arm/boards/tqmls1046a/board.c
@@ -7,6 +7,7 @@
#include <linux/sizes.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
+#include <soc/fsl/immap_lsch2.h>
static int tqmls1046a_mem_init(void)
{
@@ -21,11 +22,16 @@ mem_initcall(tqmls1046a_mem_init);
static int tqmls1046a_postcore_init(void)
{
+ struct ccsr_scfg *scfg = IOMEM(LSCH2_SCFG_ADDR);
+
if (!of_machine_is_compatible("tqc,tqmls1046a"))
return 0;
defaultenv_append_directory(defaultenv_tqmls1046a);
+ /* Configure iomux for i2c4 */
+ out_be32(&scfg->rcwpmuxcr0, 0x3300);
+
return 0;
}
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 08/10] filetype: Detect Layerscape PBL images
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (6 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 07/10] ARM: Layerscape: TQMLS1046a: Fix pinmux setup for i2c4 Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 11:02 ` Roland Hieber
2019-05-08 9:03 ` [PATCH 09/10] net: fsl-fman: Sync rx buffers for device initially Sascha Hauer
2019-05-08 9:03 ` [PATCH 10/10] ARM: Layerscape: defconfig: Enable more features Sascha Hauer
9 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
The Layerscape SoCs have their own boot image format. Add filetype
detection for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/filetype.c | 4 ++++
include/filetype.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/common/filetype.c b/common/filetype.c
index fb029a7739..f8ae214446 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -75,6 +75,7 @@ static const struct filetype_str filetype_str[] = {
[filetype_elf] = { "ELF", "elf" },
[filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
[filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
+ [filetype_layerscape_image] = { "Layerscape image", "layerscape PBL" },
};
const char *file_type_to_string(enum filetype f)
@@ -329,6 +330,9 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
if (is_sparse_image(_buf))
return filetype_android_sparse;
+ if (buf[0] == 0x55aa55aa && buf[1] == 0x0001ee01)
+ return filetype_layerscape_image;
+
if (bufsize < 64)
return filetype_unknown;
diff --git a/include/filetype.h b/include/filetype.h
index 395053dd59..cdb39fad38 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -45,6 +45,7 @@ enum filetype {
filetype_elf,
filetype_imx_image_v1,
filetype_imx_image_v2,
+ filetype_layerscape_image,
filetype_max,
};
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 08/10] filetype: Detect Layerscape PBL images
2019-05-08 9:03 ` [PATCH 08/10] filetype: Detect Layerscape PBL images Sascha Hauer
@ 2019-05-08 11:02 ` Roland Hieber
2019-05-09 9:50 ` Sascha Hauer
0 siblings, 1 reply; 14+ messages in thread
From: Roland Hieber @ 2019-05-08 11:02 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
Hi Sascha,
On Wed, May 08, 2019 at 11:03:05AM +0200, Sascha Hauer wrote:
> The Layerscape SoCs have their own boot image format. Add filetype
> detection for it.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> common/filetype.c | 4 ++++
> include/filetype.h | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/common/filetype.c b/common/filetype.c
> index fb029a7739..f8ae214446 100644
> --- a/common/filetype.c
> +++ b/common/filetype.c
> @@ -75,6 +75,7 @@ static const struct filetype_str filetype_str[] = {
> [filetype_elf] = { "ELF", "elf" },
> [filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
> [filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
> + [filetype_layerscape_image] = { "Layerscape image", "layerscape PBL" },
The comment above that array says for the "shortname" member:
const char *shortname; /* short string without spaces for shell scripts */
So I would recommend to "layerscape-pbl" instead.
- Roland
> };
>
> const char *file_type_to_string(enum filetype f)
> @@ -329,6 +330,9 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
> if (is_sparse_image(_buf))
> return filetype_android_sparse;
>
> + if (buf[0] == 0x55aa55aa && buf[1] == 0x0001ee01)
> + return filetype_layerscape_image;
> +
> if (bufsize < 64)
> return filetype_unknown;
>
> diff --git a/include/filetype.h b/include/filetype.h
> index 395053dd59..cdb39fad38 100644
> --- a/include/filetype.h
> +++ b/include/filetype.h
> @@ -45,6 +45,7 @@ enum filetype {
> filetype_elf,
> filetype_imx_image_v1,
> filetype_imx_image_v2,
> + filetype_layerscape_image,
> filetype_max,
> };
>
> --
> 2.20.1
>
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 08/10] filetype: Detect Layerscape PBL images
2019-05-08 11:02 ` Roland Hieber
@ 2019-05-09 9:50 ` Sascha Hauer
2019-05-09 12:31 ` Roland Hieber
0 siblings, 1 reply; 14+ messages in thread
From: Sascha Hauer @ 2019-05-09 9:50 UTC (permalink / raw)
To: Roland Hieber; +Cc: Barebox List
On Wed, May 08, 2019 at 01:02:54PM +0200, Roland Hieber wrote:
> Hi Sascha,
>
> On Wed, May 08, 2019 at 11:03:05AM +0200, Sascha Hauer wrote:
> > The Layerscape SoCs have their own boot image format. Add filetype
> > detection for it.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> > common/filetype.c | 4 ++++
> > include/filetype.h | 1 +
> > 2 files changed, 5 insertions(+)
> >
> > diff --git a/common/filetype.c b/common/filetype.c
> > index fb029a7739..f8ae214446 100644
> > --- a/common/filetype.c
> > +++ b/common/filetype.c
> > @@ -75,6 +75,7 @@ static const struct filetype_str filetype_str[] = {
> > [filetype_elf] = { "ELF", "elf" },
> > [filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
> > [filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
> > + [filetype_layerscape_image] = { "Layerscape image", "layerscape PBL" },
>
> The comment above that array says for the "shortname" member:
>
> const char *shortname; /* short string without spaces for shell scripts */
>
> So I would recommend to "layerscape-pbl" instead.
I should know that as I have written the comment :-/
Here is a v2 that also detects the QSPI image which have an endianess
swapped header.
Sascha
------------------------8<-----------------------------
From 0aafb86e38c5e436fee409f2b94b145e22c4a8be Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Fri, 3 May 2019 13:10:53 +0200
Subject: [PATCH] filetype: Detect Layerscape PBL images
The Layerscape SoCs have their own boot image format. Add filetype
detection for it.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
common/filetype.c | 7 +++++++
include/filetype.h | 2 ++
2 files changed, 9 insertions(+)
diff --git a/common/filetype.c b/common/filetype.c
index fb029a7739..e2d707b156 100644
--- a/common/filetype.c
+++ b/common/filetype.c
@@ -75,6 +75,8 @@ static const struct filetype_str filetype_str[] = {
[filetype_elf] = { "ELF", "elf" },
[filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
[filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
+ [filetype_layerscape_image] = { "Layerscape image", "layerscape-PBL" },
+ [filetype_layerscape_qspi_image] = { "Layerscape QSPI image", "layerscape-qspi-PBL" },
};
const char *file_type_to_string(enum filetype f)
@@ -329,6 +331,11 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
if (is_sparse_image(_buf))
return filetype_android_sparse;
+ if (buf[0] == 0x55aa55aa && buf[1] == 0x0001ee01)
+ return filetype_layerscape_image;
+ if (buf[0] == 0x01ee0100 && buf[1] == 0xaa55aa55)
+ return filetype_layerscape_qspi_image;
+
if (bufsize < 64)
return filetype_unknown;
diff --git a/include/filetype.h b/include/filetype.h
index 395053dd59..dcb331a6c9 100644
--- a/include/filetype.h
+++ b/include/filetype.h
@@ -45,6 +45,8 @@ enum filetype {
filetype_elf,
filetype_imx_image_v1,
filetype_imx_image_v2,
+ filetype_layerscape_image,
+ filetype_layerscape_qspi_image,
filetype_max,
};
--
2.20.1
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 08/10] filetype: Detect Layerscape PBL images
2019-05-09 9:50 ` Sascha Hauer
@ 2019-05-09 12:31 ` Roland Hieber
0 siblings, 0 replies; 14+ messages in thread
From: Roland Hieber @ 2019-05-09 12:31 UTC (permalink / raw)
To: Sascha Hauer; +Cc: Barebox List
On Thu, May 09, 2019 at 11:50:08AM +0200, Sascha Hauer wrote:
> On Wed, May 08, 2019 at 01:02:54PM +0200, Roland Hieber wrote:
> > Hi Sascha,
> >
> > On Wed, May 08, 2019 at 11:03:05AM +0200, Sascha Hauer wrote:
> > > The Layerscape SoCs have their own boot image format. Add filetype
> > > detection for it.
> > >
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > > common/filetype.c | 4 ++++
> > > include/filetype.h | 1 +
> > > 2 files changed, 5 insertions(+)
> > >
> > > diff --git a/common/filetype.c b/common/filetype.c
> > > index fb029a7739..f8ae214446 100644
> > > --- a/common/filetype.c
> > > +++ b/common/filetype.c
> > > @@ -75,6 +75,7 @@ static const struct filetype_str filetype_str[] = {
> > > [filetype_elf] = { "ELF", "elf" },
> > > [filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
> > > [filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
> > > + [filetype_layerscape_image] = { "Layerscape image", "layerscape PBL" },
> >
> > The comment above that array says for the "shortname" member:
> >
> > const char *shortname; /* short string without spaces for shell scripts */
> >
> > So I would recommend to "layerscape-pbl" instead.
>
> I should know that as I have written the comment :-/
>
> Here is a v2 that also detects the QSPI image which have an endianess
> swapped header.
Yep, LGTM now :)
- Roland
>
> Sascha
>
> ------------------------8<-----------------------------
>
> From 0aafb86e38c5e436fee409f2b94b145e22c4a8be Mon Sep 17 00:00:00 2001
> From: Sascha Hauer <s.hauer@pengutronix.de>
> Date: Fri, 3 May 2019 13:10:53 +0200
> Subject: [PATCH] filetype: Detect Layerscape PBL images
>
> The Layerscape SoCs have their own boot image format. Add filetype
> detection for it.
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
> common/filetype.c | 7 +++++++
> include/filetype.h | 2 ++
> 2 files changed, 9 insertions(+)
>
> diff --git a/common/filetype.c b/common/filetype.c
> index fb029a7739..e2d707b156 100644
> --- a/common/filetype.c
> +++ b/common/filetype.c
> @@ -75,6 +75,8 @@ static const struct filetype_str filetype_str[] = {
> [filetype_elf] = { "ELF", "elf" },
> [filetype_imx_image_v1] = { "i.MX image (v1)", "imx-image-v1" },
> [filetype_imx_image_v2] = { "i.MX image (v2)", "imx-image-v2" },
> + [filetype_layerscape_image] = { "Layerscape image", "layerscape-PBL" },
> + [filetype_layerscape_qspi_image] = { "Layerscape QSPI image", "layerscape-qspi-PBL" },
> };
>
> const char *file_type_to_string(enum filetype f)
> @@ -329,6 +331,11 @@ enum filetype file_detect_type(const void *_buf, size_t bufsize)
> if (is_sparse_image(_buf))
> return filetype_android_sparse;
>
> + if (buf[0] == 0x55aa55aa && buf[1] == 0x0001ee01)
> + return filetype_layerscape_image;
> + if (buf[0] == 0x01ee0100 && buf[1] == 0xaa55aa55)
> + return filetype_layerscape_qspi_image;
> +
> if (bufsize < 64)
> return filetype_unknown;
>
> diff --git a/include/filetype.h b/include/filetype.h
> index 395053dd59..dcb331a6c9 100644
> --- a/include/filetype.h
> +++ b/include/filetype.h
> @@ -45,6 +45,8 @@ enum filetype {
> filetype_elf,
> filetype_imx_image_v1,
> filetype_imx_image_v2,
> + filetype_layerscape_image,
> + filetype_layerscape_qspi_image,
> filetype_max,
> };
>
> --
> 2.20.1
>
> --
> Pengutronix e.K. | |
> Industrial Linux Solutions | http://www.pengutronix.de/ |
> Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
> Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
>
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
>
--
Roland Hieber | r.hieber@pengutronix.de |
Pengutronix e.K. | https://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim | Phone: +49-5121-206917-5086 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 09/10] net: fsl-fman: Sync rx buffers for device initially
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (7 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 08/10] filetype: Detect Layerscape PBL images Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
2019-05-08 9:03 ` [PATCH 10/10] ARM: Layerscape: defconfig: Enable more features Sascha Hauer
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
The rx buffers must be given to the device initially to work properly.
Otherwise the first packets are corrupted.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/net/fsl-fman.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fsl-fman.c b/drivers/net/fsl-fman.c
index 1a11ca4926..4e6bb2ecfd 100644
--- a/drivers/net/fsl-fman.c
+++ b/drivers/net/fsl-fman.c
@@ -640,6 +640,8 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
i * MAX_RXBUF_LEN));
buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
i * MAX_RXBUF_LEN));
+ dma_sync_single_for_device((unsigned long)rx_buf_pool + i * MAX_RXBUF_LEN,
+ MAX_RXBUF_LEN, DMA_FROM_DEVICE);
muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
out_be32(&rxbd->buf_ptr_lo, buf_lo);
rxbd++;
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 10/10] ARM: Layerscape: defconfig: Enable more features
2019-05-08 9:02 [PATCH 00/10] Layerscape patches Sascha Hauer
` (8 preceding siblings ...)
2019-05-08 9:03 ` [PATCH 09/10] net: fsl-fman: Sync rx buffers for device initially Sascha Hauer
@ 2019-05-08 9:03 ` Sascha Hauer
9 siblings, 0 replies; 14+ messages in thread
From: Sascha Hauer @ 2019-05-08 9:03 UTC (permalink / raw)
To: Barebox List
The TQMLS1046a has an i2c mux and a i2c gpio expander. Add support for
it and also disable early debugging as these are for a single board
only.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/configs/layerscape_defconfig | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/layerscape_defconfig b/arch/arm/configs/layerscape_defconfig
index dadbcc214c..b81f375415 100644
--- a/arch/arm/configs/layerscape_defconfig
+++ b/arch/arm/configs/layerscape_defconfig
@@ -22,7 +22,6 @@ CONFIG_PBL_CONSOLE=y
CONFIG_PARTITION_DISK_EFI=y
CONFIG_DEFAULT_ENVIRONMENT_GENERIC_NEW=y
CONFIG_RESET_SOURCE=y
-CONFIG_DEBUG_LL=y
CONFIG_CMD_DMESG=y
CONFIG_LONGHELP=y
CONFIG_CMD_IOMEM=y
@@ -85,8 +84,13 @@ CONFIG_DRIVER_NET_FSL_FMAN=y
CONFIG_DP83867_PHY=y
CONFIG_REALTEK_PHY=y
CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_DRIVER_SPI_FSL_QUADSPI=y
CONFIG_I2C=y
CONFIG_I2C_IMX=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_MTD=y
+CONFIG_MTD_M25P80=y
CONFIG_MCI=y
CONFIG_MCI_MMC_BOOT_PARTITIONS=y
CONFIG_MCI_IMX_ESDHC=y
@@ -94,10 +98,12 @@ CONFIG_LED=y
CONFIG_LED_GPIO=y
CONFIG_LED_GPIO_OF=y
CONFIG_LED_TRIGGERS=y
+CONFIG_LED_PCA955X=y
CONFIG_EEPROM_AT25=y
CONFIG_EEPROM_AT24=y
CONFIG_WATCHDOG=y
CONFIG_WATCHDOG_IMX=y
+CONFIG_GPIO_PCA953X=y
CONFIG_NVMEM=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED=y
--
2.20.1
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^ permalink raw reply [flat|nested] 14+ messages in thread