* [PATCH 1/4] ARM: socfpga: fix xload on arria10
@ 2019-08-19 10:00 Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 2/4] ARM: Arria10: achilles: fix offsets in node names Steffen Trumtrar
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2019-08-19 10:00 UTC (permalink / raw)
To: Barebox List
Since the commit
5a1a5ed2537d7d12f851f3778707681d6c08d6e8
ARM: images: use piggydata
the loading mechanism in the arria10 xload is neither functional nor needed.
Now, barebox has/can be loaded like a normal image, so the filesize, that is
written to the barebox header, can be evaluated.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/mach-socfpga/arria10-xload.c | 65 ++++++---------------------
images/Makefile.socfpga | 2 +-
2 files changed, 14 insertions(+), 53 deletions(-)
diff --git a/arch/arm/mach-socfpga/arria10-xload.c b/arch/arm/mach-socfpga/arria10-xload.c
index 3622a3cd9cf4..047f61246cbf 100644
--- a/arch/arm/mach-socfpga/arria10-xload.c
+++ b/arch/arm/mach-socfpga/arria10-xload.c
@@ -386,70 +386,31 @@ int arria10_load_fpga(int offset, int bitstream_size)
return 0;
}
-static int image_size(void)
-{
- uint32_t *image_end = (void *)__image_end;
- uint32_t payload_len;
- uint32_t pbl_len;
- uint32_t arria10_header_len;
- uint32_t sizep;
- uint32_t arria10_crc;
-
- /* arria10 header is 512 byte */
- arria10_header_len = 512;
- /* pbl is appended with 4 byte CRC for boot rom */
- arria10_crc = 4;
-
- /* The length of the PBL image */
- pbl_len = __image_end - _text;
-
- sizep = 4;
-
- /* The length of the payload is appended directly behind the PBL */
- payload_len = *(image_end);
-
- return pbl_len + arria10_header_len + sizep + arria10_crc + payload_len;
-}
-
void arria10_start_image(int offset)
{
void *buf = (void *)0x0;
- void *in_buf = (void *)SZ_1M;
uint32_t start;
- int size = 0;
- int ret;
+ unsigned int size;
+ int ret;
void __noreturn (*bb)(void);
- uint32_t pbl_len = __image_end - _text;
- uint32_t *image_end = (void *)__image_end;
- uint32_t arria10_header_len;
- uint32_t sizep;
- uint32_t arria10_crc;
-
- size = image_size();
start = bootloader.first_sec + offset / SECTOR_SIZE;
- ret = arria10_read_blocks(buf, start, ALIGN(size, SECTOR_SIZE));
- if (ret) {
- puts_ll("Loading image failed\n");
+ ret = arria10_read_blocks(buf, start, ALIGN(ARM_HEAD_SIZE, SECTOR_SIZE));
+ if (ret)
hang();
- }
-
- /* arria10 header is 512 byte */
- arria10_header_len = 512;
- sizep = 4;
- /* copy PBL */
- memcpy(in_buf, buf, pbl_len + sizep + arria10_header_len);
-
- /* pbl is appended with 4 byte CRC for boot rom */
- arria10_crc = 4;
+ if (is_barebox_arm_head(buf))
+ size = *((unsigned int *)buf + ARM_HEAD_SIZE_OFFSET /
+ sizeof(unsigned int));
+ else
+ hang();
- /* copy payload, skip the Arria10 CRC */
- memcpy(in_buf + pbl_len + sizep + arria10_header_len,
- buf + pbl_len + sizep + arria10_header_len + arria10_crc, *(image_end));
+ ret = arria10_read_blocks(buf, start, ALIGN(size, SECTOR_SIZE));
+ if (ret)
+ hang();
- bb = in_buf;
+ bb = buf;
bb();
diff --git a/images/Makefile.socfpga b/images/Makefile.socfpga
index 6b346a5f8414..b36e2a5033d3 100644
--- a/images/Makefile.socfpga
+++ b/images/Makefile.socfpga
@@ -4,7 +4,7 @@
# %.socfpgaimg - convert into socfpga image
# ----------------------------------------------------------------
-SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += -v1
+SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += -v1 -b
SOCFPGA_IMAGE_ARGS-$(CONFIG_ARCH_SOCFPGA_CYCLONE5) += -v0
quiet_cmd_socfpga_image = SOCFPGA-IMG $@
--
2.20.1
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/4] ARM: Arria10: achilles: fix offsets in node names
2019-08-19 10:00 [PATCH 1/4] ARM: socfpga: fix xload on arria10 Steffen Trumtrar
@ 2019-08-19 10:00 ` Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 3/4] ARM: Arria10: achilles: add named partitions Steffen Trumtrar
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2019-08-19 10:00 UTC (permalink / raw)
To: Barebox List
The node names do not match the actual reg values.
Fix this up.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/dts/socfpga_arria10_achilles.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
index e94a3219992f..585ac20e1e0a 100644
--- a/arch/arm/dts/socfpga_arria10_achilles.dts
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -226,12 +226,12 @@
compatible = "fixed-partitions";
#size-cells = <1>;
#address-cells = <1>;
- environment_mmc: partition@178000 {
+ environment_mmc: partition@300000 {
label = "environment";
reg = <0x300000 0x8000>;
};
- state_mmc: partition@180000 {
+ state_mmc: partition@400000 {
label = "state";
reg = <0x400000 0x8000>;
};
--
2.20.1
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/4] ARM: Arria10: achilles: add named partitions
2019-08-19 10:00 [PATCH 1/4] ARM: socfpga: fix xload on arria10 Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 2/4] ARM: Arria10: achilles: fix offsets in node names Steffen Trumtrar
@ 2019-08-19 10:00 ` Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 4/4] ARM: achilles: add bbu handler Steffen Trumtrar
2019-08-21 6:45 ` [PATCH 1/4] ARM: socfpga: fix xload on arria10 Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2019-08-19 10:00 UTC (permalink / raw)
To: Barebox List
Add labels for the barebox1/2 and bitstream1/2 partitions.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/dts/socfpga_arria10_achilles.dts | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria10_achilles.dts b/arch/arm/dts/socfpga_arria10_achilles.dts
index 585ac20e1e0a..4c6460fb60aa 100644
--- a/arch/arm/dts/socfpga_arria10_achilles.dts
+++ b/arch/arm/dts/socfpga_arria10_achilles.dts
@@ -226,6 +226,27 @@
compatible = "fixed-partitions";
#size-cells = <1>;
#address-cells = <1>;
+
+ barebox1_xload: partition@100000 {
+ label = "barebox1-xload";
+ reg = <0x100000 0x40000>;
+ };
+
+ barebox2_xload: partition@140000 {
+ label = "barebox2-xload";
+ reg = <0x140000 0x40000>;
+ };
+
+ barebox1: partition@200000 {
+ label = "barebox1";
+ reg = <0x200000 0x80000>;
+ };
+
+ barebox2: partition@280000 {
+ label = "barebox2";
+ reg = <0x280000 0x80000>;
+ };
+
environment_mmc: partition@300000 {
label = "environment";
reg = <0x300000 0x8000>;
@@ -235,6 +256,17 @@
label = "state";
reg = <0x400000 0x8000>;
};
+
+ bitstream1: partition@700000 {
+ label = "bitstream1";
+ reg = <0x700000 0x2000000>;
+ };
+
+ bitstream2: partition@2700000 {
+ label = "bitstream2";
+ reg = <0x2700000 0x2000000>;
+ };
+
};
};
--
2.20.1
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^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 4/4] ARM: achilles: add bbu handler
2019-08-19 10:00 [PATCH 1/4] ARM: socfpga: fix xload on arria10 Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 2/4] ARM: Arria10: achilles: fix offsets in node names Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 3/4] ARM: Arria10: achilles: add named partitions Steffen Trumtrar
@ 2019-08-19 10:00 ` Steffen Trumtrar
2019-08-21 6:45 ` [PATCH 1/4] ARM: socfpga: fix xload on arria10 Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Steffen Trumtrar @ 2019-08-19 10:00 UTC (permalink / raw)
To: Barebox List
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
---
arch/arm/boards/reflex-achilles/board.c | 26 +++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/boards/reflex-achilles/board.c b/arch/arm/boards/reflex-achilles/board.c
index 29011ba5784e..2b8186e19f40 100644
--- a/arch/arm/boards/reflex-achilles/board.c
+++ b/arch/arm/boards/reflex-achilles/board.c
@@ -6,6 +6,8 @@
static int achilles_init(void)
{
int pbl_index = 0;
+ uint32_t flag_barebox1 = 0;
+ uint32_t flag_barebox2 = 0;
if (!of_machine_is_compatible("reflex,achilles"))
return 0;
@@ -14,6 +16,30 @@ static int achilles_init(void)
pr_debug("Current barebox instance %d\n", pbl_index);
+ switch (pbl_index) {
+ case 0:
+ flag_barebox1 |= BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ case 1:
+ flag_barebox2 |= BBU_HANDLER_FLAG_DEFAULT;
+ break;
+ };
+
+ bbu_register_std_file_update("emmc-barebox1-xload", flag_barebox1,
+ "/dev/disk0.barebox1-xload",
+ filetype_socfpga_xload);
+
+ bbu_register_std_file_update("emmc-barebox1", 0,
+ "/dev/disk0.barebox1",
+ filetype_arm_barebox);
+
+ bbu_register_std_file_update("emmc-barebox2-xload", flag_barebox2,
+ "/dev/disk0.barebox2-xload",
+ filetype_socfpga_xload);
+
+ bbu_register_std_file_update("emmc-barebox2", 0,
+ "/dev/disk0.barebox2",
+ filetype_arm_barebox);
return 0;
}
postcore_initcall(achilles_init);
--
2.20.1
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH 1/4] ARM: socfpga: fix xload on arria10
2019-08-19 10:00 [PATCH 1/4] ARM: socfpga: fix xload on arria10 Steffen Trumtrar
` (2 preceding siblings ...)
2019-08-19 10:00 ` [PATCH 4/4] ARM: achilles: add bbu handler Steffen Trumtrar
@ 2019-08-21 6:45 ` Sascha Hauer
3 siblings, 0 replies; 5+ messages in thread
From: Sascha Hauer @ 2019-08-21 6:45 UTC (permalink / raw)
To: Steffen Trumtrar; +Cc: Barebox List
On Mon, Aug 19, 2019 at 12:00:46PM +0200, Steffen Trumtrar wrote:
> Since the commit
> 5a1a5ed2537d7d12f851f3778707681d6c08d6e8
> ARM: images: use piggydata
>
> the loading mechanism in the arria10 xload is neither functional nor needed.
> Now, barebox has/can be loaded like a normal image, so the filesize, that is
> written to the barebox header, can be evaluated.
>
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
> arch/arm/mach-socfpga/arria10-xload.c | 65 ++++++---------------------
> images/Makefile.socfpga | 2 +-
> 2 files changed, 14 insertions(+), 53 deletions(-)
Applied, thanks
Sascha
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2019-08-19 10:00 [PATCH 1/4] ARM: socfpga: fix xload on arria10 Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 2/4] ARM: Arria10: achilles: fix offsets in node names Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 3/4] ARM: Arria10: achilles: add named partitions Steffen Trumtrar
2019-08-19 10:00 ` [PATCH 4/4] ARM: achilles: add bbu handler Steffen Trumtrar
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