From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 1/6] ARM: omap: am35xx_emif4: Fix bit polling
Date: Wed, 28 Aug 2019 12:23:57 +0200 [thread overview]
Message-ID: <20190828102402.18332-2-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20190828102402.18332-1-s.hauer@pengutronix.de>
((x & (1 << 10)) == 0x1) can never be true as the compiler mourns about.
Fix this to actually do what the comment says: Wait till bit 10 is
cleared. Looking at the corresponding U-Boot code also suggests that
this is the right thing to do.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
arch/arm/mach-omap/am35xx_emif4.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c
index 38fc0f02d2..678a338fd6 100644
--- a/arch/arm/mach-omap/am35xx_emif4.c
+++ b/arch/arm/mach-omap/am35xx_emif4.c
@@ -37,7 +37,7 @@ void am35xx_emif4_init(void)
writel(regval, &emif4_base->sdram_iodft_tlgc);
/* Wait till that bit clears*/
- while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1);
+ while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10));
/* Re-verify the DDR PHY status*/
while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0);
--
2.23.0
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next prev parent reply other threads:[~2019-08-28 10:24 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-28 10:23 [PATCH 0/6] OMAP updates Sascha Hauer
2019-08-28 10:23 ` Sascha Hauer [this message]
2019-08-28 10:23 ` [PATCH 2/6] mtd: nand: gpmc: Add support for ELM Sascha Hauer
2019-08-28 10:23 ` [PATCH 3/6] mtd: nand: gpmc: Add BCH16 support Sascha Hauer
2019-08-28 10:24 ` [PATCH 4/6] net: cpsw: Make phy its own driver Sascha Hauer
2019-08-28 10:24 ` [PATCH 5/6] mtd: peb: Add function to write file Sascha Hauer
2019-08-28 10:24 ` [PATCH 6/6] ARM: OMAP: bbu: Add an all-in-one NAND update handler Sascha Hauer
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