From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by bombadil.infradead.org with esmtps (Exim 4.92 #3 (Red Hat Linux)) id 1i2v7W-0002jI-Js for barebox@lists.infradead.org; Wed, 28 Aug 2019 10:24:08 +0000 From: Sascha Hauer Date: Wed, 28 Aug 2019 12:23:57 +0200 Message-Id: <20190828102402.18332-2-s.hauer@pengutronix.de> In-Reply-To: <20190828102402.18332-1-s.hauer@pengutronix.de> References: <20190828102402.18332-1-s.hauer@pengutronix.de> MIME-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "barebox" Errors-To: barebox-bounces+u.kleine-koenig=pengutronix.de@lists.infradead.org Subject: [PATCH 1/6] ARM: omap: am35xx_emif4: Fix bit polling To: Barebox List ((x & (1 << 10)) == 0x1) can never be true as the compiler mourns about. Fix this to actually do what the comment says: Wait till bit 10 is cleared. Looking at the corresponding U-Boot code also suggests that this is the right thing to do. Signed-off-by: Sascha Hauer --- arch/arm/mach-omap/am35xx_emif4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-omap/am35xx_emif4.c b/arch/arm/mach-omap/am35xx_emif4.c index 38fc0f02d2..678a338fd6 100644 --- a/arch/arm/mach-omap/am35xx_emif4.c +++ b/arch/arm/mach-omap/am35xx_emif4.c @@ -37,7 +37,7 @@ void am35xx_emif4_init(void) writel(regval, &emif4_base->sdram_iodft_tlgc); /* Wait till that bit clears*/ - while ((readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)) == 0x1); + while (readl(&emif4_base->sdram_iodft_tlgc) & (1 << 10)); /* Re-verify the DDR PHY status*/ while ((readl(&emif4_base->sdram_sts) & (1 << 2)) == 0x0); -- 2.23.0 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox