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From: Ahmad Fatoum <a.fatoum@pengutronix.de>
To: barebox@lists.infradead.org
Cc: Ahmad Fatoum <a.fatoum@pengutronix.de>
Subject: [PATCH] ARM: cache-armv7: remove superfluous instruction
Date: Tue,  8 Oct 2019 16:46:28 +0200	[thread overview]
Message-ID: <20191008144628.7991-1-a.fatoum@pengutronix.de> (raw)

There are two tst r11, #0xf with nothing in between them that changes
r11. This a left over from the kernel code that checks for VMSA twice,
once to check if the page table should be setup and once to more to
flush the TLB. We do the setup in the caller already, so the tst serves
no useful purpose. Delete one.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/cpu/cache-armv7.S | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm/cpu/cache-armv7.S b/arch/arm/cpu/cache-armv7.S
index 6a8aff8bb12c..43ec9021330e 100644
--- a/arch/arm/cpu/cache-armv7.S
+++ b/arch/arm/cpu/cache-armv7.S
@@ -7,7 +7,6 @@ ENTRY(v7_mmu_cache_on)
 		mov	r12, lr
 #ifdef CONFIG_MMU
 		mrc	p15, 0, r11, c0, c1, 4	@ read ID_MMFR0
-		tst	r11, #0xf		@ VMSA
 		mov	r0, #0
 		dsb				@ drain write buffer
 		tst	r11, #0xf		@ VMSA
-- 
2.23.0


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             reply	other threads:[~2019-10-08 14:46 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-08 14:46 Ahmad Fatoum [this message]
2019-10-14 10:27 ` Sascha Hauer

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