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* [PATCH 1/4] mfd: add basic Super I/O chip helpers
@ 2019-10-11 16:27 Ahmad Fatoum
  2019-10-11 16:27 ` [PATCH 2/4] mfd: superio: add Fintek MFD driver Ahmad Fatoum
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2019-10-11 16:27 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Super I/O chips are ICs common to x86 that are used for interfacing
to low-bandwidth peripherals. They often contain serial ports, watchdog
timers and hardware monitoring units.

They are usually addressable via one of two I/O port pairs, either
0x2e-0x2f or 0x4e-0x4f, but they don't typically respond to reads from
their range unless a device-specific 'password' has been poked in.
After this is done, they are read and written in the same manner however.

On Linux, these devices aren't subject to any device/driver model.
Each driver for some function (e.g. watchdog or GPIO) duplicates the
device probe in the module_init and board-specific configuration
is handled via module parameters.

Lets do it a bit fancier in barebox and add a helper to register chips
and a regmap for the control and configuration registers as well as a
helper to register child devices for each function contained within the
Super I/O chip.
Board-specific configuration, e.g. which pin to use as a watchdog reset,
can then be realized using barebox device-specific parameters.

The regmap will be more of a debugging aid, however.
For ease of porting from Linux, it's expected that access to the
I/O ports won't happen via the regmap. For this reason, the new
<superio.h> header offers functions to read/write these chips' registers
as well.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/mfd/Kconfig   |  3 ++
 drivers/mfd/Makefile  |  1 +
 drivers/mfd/superio.c | 98 +++++++++++++++++++++++++++++++++++++++++++
 include/superio.h     | 64 ++++++++++++++++++++++++++++
 4 files changed, 166 insertions(+)
 create mode 100644 drivers/mfd/superio.c
 create mode 100644 include/superio.h

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 7d924cfca1eb..bd6f14a59f56 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -67,4 +67,7 @@ config MFD_STPMIC1
 	help
 	  Select this to support communication with the STPMIC1.
 
+config MFD_SUPERIO
+	bool
+
 endmenu
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 16a74abd77f3..690788eefb44 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -12,3 +12,4 @@ obj-$(CONFIG_MFD_TWL4030)	+= twl4030.o
 obj-$(CONFIG_MFD_TWL6030)	+= twl6030.o
 obj-$(CONFIG_RAVE_SP_CORE)	+= rave-sp.o
 obj-$(CONFIG_MFD_STPMIC1)	+= stpmic1.o
+obj-$(CONFIG_MFD_SUPERIO)	+= superio.o
diff --git a/drivers/mfd/superio.c b/drivers/mfd/superio.c
new file mode 100644
index 000000000000..0f08d56cb357
--- /dev/null
+++ b/drivers/mfd/superio.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#define pr_fmt(fmt) "superio: " fmt
+
+#include <common.h>
+#include <superio.h>
+#include <regmap.h>
+
+struct device_d *superio_func_add(struct superio_chip *siochip, const char *name)
+{
+	struct device_d *dev;
+	int ret;
+
+	dev = device_alloc(name, DEVICE_ID_DYNAMIC);
+	dev->parent = siochip->dev;
+
+
+	ret = platform_device_register(dev);
+	if (ret)
+		return NULL;
+
+	return dev;
+}
+EXPORT_SYMBOL(superio_func_add)
+
+static int superio_reg_read(void *ctx, unsigned int reg, unsigned int *val)
+{
+	struct superio_chip *siochip = ctx;
+
+	siochip->enter(siochip->sioaddr);
+
+	*val = superio_inb(siochip->sioaddr, reg);
+
+	siochip->exit(siochip->sioaddr);
+
+	return 0;
+}
+
+static int superio_reg_write(void *ctx, unsigned int reg, unsigned int val)
+{
+	struct superio_chip *siochip = ctx;
+
+	siochip->enter(siochip->sioaddr);
+
+	superio_outb(siochip->sioaddr, reg, val);
+
+	siochip->exit(siochip->sioaddr);
+
+	return 0;
+}
+
+static struct regmap_bus superio_regmap_bus = {
+	.reg_write = superio_reg_write,
+	.reg_read = superio_reg_read,
+};
+
+static struct regmap_config superio_regmap_config = {
+	.reg_bits = 8,
+	.val_bits = 8,
+	.reg_stride = 1,
+	.max_register = 0xff,
+};
+
+void superio_chip_add(struct superio_chip *siochip)
+{
+	struct regmap *regmap;
+	char *chipname;
+	char str[5];
+	int ret;
+
+	chipname = xasprintf("superio-%04x:%04x@%02x",
+			     siochip->vid, siochip->devid, siochip->sioaddr);
+	siochip->dev = add_generic_device(chipname, DEVICE_ID_SINGLE, NULL,
+					  siochip->sioaddr, 2, IORESOURCE_IO,
+					  NULL);
+
+	siochip->dev->priv = siochip;
+
+	sprintf(str, "%04x", siochip->vid);
+	dev_add_param_fixed(siochip->dev, "vendor", str);
+	sprintf(str, "%04x", siochip->devid);
+	dev_add_param_fixed(siochip->dev, "device", str);
+
+	regmap = regmap_init(siochip->dev, &superio_regmap_bus, siochip,
+			     &superio_regmap_config);
+	if (IS_ERR(regmap))
+		pr_warn("creating %s regmap failed: %s\n",
+			chipname, strerror(-PTR_ERR(regmap)));
+
+	ret = regmap_register_cdev(regmap, chipname);
+	if (ret)
+		pr_warn("registering %s regmap cdev failed: %s\n",
+			chipname, strerror(-ret));
+}
+EXPORT_SYMBOL(superio_chip_add)
diff --git a/include/superio.h b/include/superio.h
new file mode 100644
index 000000000000..12bff58b6b1b
--- /dev/null
+++ b/include/superio.h
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#ifndef _SUPERIO_H_
+#define _SUPERIO_H_
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <driver.h>
+#include <linux/types.h>
+
+#define SIO_REG_DEVID		0x20	/* Device ID (2 bytes) */
+#define SIO_REG_DEVREV		0x22	/* Device revision */
+#define SIO_REG_MANID		0x23	/* Vendor ID (2 bytes) */
+
+static inline u8 superio_inb(u16 base, u8 reg)
+{
+	outb(reg, base);
+	return inb(base + 1);
+}
+
+static inline u16 superio_inw(u16 base, u8 reg)
+{
+	u16 val;
+	val  = superio_inb(base, reg) << 8;
+	val |= superio_inb(base, reg + 1);
+	return val;
+}
+
+static inline void superio_outb(u16 base, u8 reg, u8 val)
+{
+	outb(reg, base);
+	outb(val, base + 1);
+}
+
+static inline void superio_set_bit(u16 base, u8 reg, unsigned bit)
+{
+	unsigned long val = superio_inb(base, reg);
+	__set_bit(bit, &val);
+	superio_outb(base, reg, val);
+}
+
+static inline void superio_clear_bit(u16 base, u8 reg, unsigned bit)
+{
+	unsigned long val = superio_inb(base, reg);
+	__clear_bit(bit, &val);
+	superio_outb(base, reg, val);
+}
+
+struct superio_chip {
+	struct device_d *dev;
+	u16 vid;
+	u16 devid;
+	u16 sioaddr;
+	void (*enter)(u16 sioaddr);
+	void (*exit)(u16 sioaddr);
+};
+
+void superio_chip_add(struct superio_chip *chip);
+struct device_d *superio_func_add(struct superio_chip *chip, const char *name);
+
+#endif
-- 
2.23.0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 2/4] mfd: superio: add Fintek MFD driver
  2019-10-11 16:27 [PATCH 1/4] mfd: add basic Super I/O chip helpers Ahmad Fatoum
@ 2019-10-11 16:27 ` Ahmad Fatoum
  2019-10-11 16:27 ` [PATCH 3/4] watchdog: add support for Fintek F718xx and, F818xx Super I/O Ahmad Fatoum
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2019-10-11 16:27 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

Super I/O chips require a password to unlock access to the I/O ports.
Add a driver that pokes the password and registers the appropriate GPIO
and Watchdog devices as well as a regmap reflecting the Super I/O chip.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/mfd/Kconfig          |   6 ++
 drivers/mfd/Makefile         |   1 +
 drivers/mfd/fintek-superio.c | 122 +++++++++++++++++++++++++++++++++++
 3 files changed, 129 insertions(+)
 create mode 100644 drivers/mfd/fintek-superio.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index bd6f14a59f56..e2c74a575da4 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -70,4 +70,10 @@ config MFD_STPMIC1
 config MFD_SUPERIO
 	bool
 
+config FINTEK_SUPERIO
+       bool "Fintek Super I/O chip"
+       select MFD_SUPERIO
+       help
+         Select this to probe for IO-port connected Fintek Super I/O chips.
+
 endmenu
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 690788eefb44..59b401dd2ea0 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_MFD_TWL6030)	+= twl6030.o
 obj-$(CONFIG_RAVE_SP_CORE)	+= rave-sp.o
 obj-$(CONFIG_MFD_STPMIC1)	+= stpmic1.o
 obj-$(CONFIG_MFD_SUPERIO)	+= superio.o
+obj-$(CONFIG_FINTEK_SUPERIO)	+= fintek-superio.o
diff --git a/drivers/mfd/fintek-superio.c b/drivers/mfd/fintek-superio.c
new file mode 100644
index 000000000000..60785bce279f
--- /dev/null
+++ b/drivers/mfd/fintek-superio.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#define pr_fmt(fmt) "fintek-superio: " fmt
+
+#include <superio.h>
+#include <init.h>
+#include <asm/io.h>
+#include <common.h>
+
+#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
+#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */
+
+#define SIO_REG_LDSEL		0x07	/* Logical device select */
+
+#define SIO_FINTEK_ID		0x1934	/* Manufacturers ID */
+
+#define SIO_F71808_ID		0x0901
+#define SIO_F71858_ID		0x0507
+#define SIO_F71862_ID		0x0601
+#define SIO_F71868_ID		0x1106
+#define SIO_F71869_ID		0x0814
+#define SIO_F71869A_ID		0x1007
+#define SIO_F71882_ID		0x0541
+#define SIO_F71889_ID		0x0723
+#define SIO_F71889A_ID		0x1005
+#define SIO_F81865_ID		0x0704
+#define SIO_F81866_ID		0x1010
+
+static void superio_enter(u16 sioaddr)
+{
+	/* according to the datasheet the key must be sent twice! */
+	outb(SIO_UNLOCK_KEY, sioaddr);
+	outb(SIO_UNLOCK_KEY, sioaddr);
+}
+
+static void superio_exit(u16 sioaddr)
+{
+	outb(SIO_LOCK_KEY, sioaddr);
+}
+
+static void fintek_superio_find(u16 sioaddr)
+{
+	struct superio_chip *chip;
+	u16 vid;
+
+	superio_enter(sioaddr);
+
+	vid = superio_inw(sioaddr, SIO_REG_MANID);
+	if (vid != SIO_FINTEK_ID) {
+		pr_debug("Not a Fintek device (port=0x%02x, vid=0x%04x)\n",
+			 sioaddr, vid);
+		return;
+	}
+
+	chip = xzalloc(sizeof(*chip));
+
+	chip->devid = superio_inw(sioaddr, SIO_REG_DEVID);
+	chip->vid = vid;
+	chip->sioaddr = sioaddr;
+	chip->enter = superio_enter;
+	chip->exit = superio_exit;
+
+	superio_chip_add(chip);
+
+	switch (chip->devid) {
+	case SIO_F71808_ID:
+		superio_func_add(chip, "f71808fg_wdt");
+		break;
+	case SIO_F71862_ID:
+		superio_func_add(chip, "f71862fg_wdt");
+		break;
+	case SIO_F71868_ID:
+		superio_func_add(chip, "f71868_wdt");
+		break;
+	case SIO_F71869_ID:
+		superio_func_add(chip, "f71869_wdt");
+		superio_func_add(chip, "gpio-f71869");
+		break;
+	case SIO_F71869A_ID:
+		superio_func_add(chip, "f71869_wdt");
+		superio_func_add(chip, "gpio-f71869a");
+		break;
+	case SIO_F71882_ID:
+		superio_func_add(chip, "f71882fg_wdt");
+		superio_func_add(chip, "gpio-f71882fg");
+		break;
+	case SIO_F71889_ID:
+		superio_func_add(chip, "f71889fg_wdt");
+		superio_func_add(chip, "gpio-f71889f");
+		break;
+	case SIO_F71889A_ID:
+		superio_func_add(chip, "f71889fg_wdt");
+		superio_func_add(chip, "gpio-f71889a");
+		break;
+	case SIO_F71858_ID:
+		/* Confirmed (by datasheet) not to have a watchdog. */
+		break;
+	case SIO_F81865_ID:
+		superio_func_add(chip, "f81865_wdt");
+		break;
+	case SIO_F81866_ID:
+		superio_func_add(chip, "f81866_wdt");
+		superio_func_add(chip, "gpio-f81866");
+		break;
+	default:
+		pr_info("Unrecognized Fintek device: 0x%04x\n", chip->devid);
+	}
+
+	superio_exit(sioaddr);
+}
+
+static int fintek_superio_detect(void)
+{
+	fintek_superio_find(0x2e);
+	fintek_superio_find(0x4e);
+
+	return 0;
+}
+coredevice_initcall(fintek_superio_detect);
-- 
2.23.0


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 3/4] watchdog: add support for Fintek F718xx and, F818xx Super I/O
  2019-10-11 16:27 [PATCH 1/4] mfd: add basic Super I/O chip helpers Ahmad Fatoum
  2019-10-11 16:27 ` [PATCH 2/4] mfd: superio: add Fintek MFD driver Ahmad Fatoum
@ 2019-10-11 16:27 ` Ahmad Fatoum
  2019-10-14 12:39   ` Sascha Hauer
  2019-10-11 16:27 ` [PATCH 4/4] mfd: superio: add base SMSC MFD driver Ahmad Fatoum
  2019-10-14 13:18 ` [PATCH 1/4] mfd: add basic Super I/O chip helpers Sascha Hauer
  3 siblings, 1 reply; 7+ messages in thread
From: Ahmad Fatoum @ 2019-10-11 16:27 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

This is an adaptation of the Linux v5.3 f71808e_wdt driver for the watchdog
component of the Fintek Super I/O chips.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/watchdog/Kconfig       |  10 +
 drivers/watchdog/Makefile      |   1 +
 drivers/watchdog/f71808e_wdt.c | 379 +++++++++++++++++++++++++++++++++
 3 files changed, 390 insertions(+)
 create mode 100644 drivers/watchdog/f71808e_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index fbaab896d460..b1c2a39b6629 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -90,10 +90,20 @@ config STM32_IWDG_WATCHDOG
 	  Enable to support configuration of the STM32's on-SoC IWDG watchdog.
 	  Once started by the user, the IWDG can't be disabled.
 
+
 config STPMIC1_WATCHDOG
 	bool "STPMIC1 Watchdog"
 	depends on MFD_STPMIC1
 	help
 	  Enable to support configuration of the stpmic1's built-in watchdog.
 
+config F71808E_WDT
+	bool "Fintek F718xx, F818xx Super I/O Watchdog"
+	depends on X86
+	select FINTEK_SUPERIO
+	help
+	  This is the driver for the hardware watchdog on the Fintek F71808E,
+	  F71862FG, F71868, F71869, F71882FG, F71889FG, F81865 and F81866
+	  Super I/O controllers.
+
 endif
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 1fbd780885cb..63efc2a87ec4 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -13,3 +13,4 @@ obj-$(CONFIG_ARCH_BCM283X) += bcm2835_wdt.o
 obj-$(CONFIG_RAVE_SP_WATCHDOG) += rave-sp-wdt.o
 obj-$(CONFIG_STM32_IWDG_WATCHDOG) += stm32_iwdg.o
 obj-$(CONFIG_STPMIC1_WATCHDOG) += stpmic1_wdt.o
+obj-$(CONFIG_F71808E_WDT) += f71808e_wdt.o
diff --git a/drivers/watchdog/f71808e_wdt.c b/drivers/watchdog/f71808e_wdt.c
new file mode 100644
index 000000000000..4f881a1d02bc
--- /dev/null
+++ b/drivers/watchdog/f71808e_wdt.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/***************************************************************************
+ *   Copyright (C) 2006 by Hans Edgington <hans@edgington.nl>              *
+ *   Copyright (C) 2007-2009 Hans de Goede <hdegoede@redhat.com>           *
+ *   Copyright (C) 2010 Giel van Schijndel <me@mortis.eu>                  *
+ *   Copyright (C) 2019 Ahmad Fatoum <a.fatoum@pengutronix.de>             *
+ *                                                                         *
+ ***************************************************************************/
+
+#define pr_fmt(fmt) "f71808e_wdt: " fmt
+
+#include <init.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <driver.h>
+#include <watchdog.h>
+#include <printk.h>
+#include <reset_source.h>
+#include <superio.h>
+#include <common.h>
+
+#define SIO_F71808FG_LD_WDT	0x07	/* Watchdog timer logical device */
+#define SIO_UNLOCK_KEY		0x87	/* Key to enable Super-I/O */
+#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */
+
+#define SIO_REG_LDSEL		0x07	/* Logical device select */
+#define SIO_REG_DEVREV		0x22	/* Device revision */
+#define SIO_REG_ROM_ADDR_SEL	0x27	/* ROM address select */
+#define SIO_F81866_REG_PORT_SEL	0x27	/* F81866 Multi-Function Register */
+#define SIO_REG_MFUNCT1		0x29	/* Multi function select 1 */
+#define SIO_REG_MFUNCT2		0x2a	/* Multi function select 2 */
+#define SIO_REG_MFUNCT3		0x2b	/* Multi function select 3 */
+#define SIO_F81866_REG_GPIO1	0x2c	/* F81866 GPIO1 Enable Register */
+#define SIO_REG_ENABLE		0x30	/* Logical device enable */
+#define SIO_REG_ADDR		0x60	/* Logical device address (2 bytes) */
+
+#define F71808FG_REG_WDO_CONF		0xf0
+#define F71808FG_REG_WDT_CONF		0xf5
+#define F71808FG_REG_WD_TIME		0xf6
+
+#define F71808FG_FLAG_WDOUT_EN		7
+
+#define F71808FG_FLAG_WDTMOUT_STS	6
+#define F71808FG_FLAG_WD_EN		5
+#define F71808FG_FLAG_WD_PULSE		4
+#define F71808FG_FLAG_WD_UNIT		3
+
+#define F81865_REG_WDO_CONF		0xfa
+#define F81865_FLAG_WDOUT_EN		0
+
+/* Default values */
+#define WATCHDOG_MAX_TIMEOUT	(60 * 255)
+
+enum pulse_width {
+	PULSE_WIDTH_LEVEL, PULSE_WIDTH_1MS,
+	PULSE_WIDTH_LOW, PULSE_WIDTH_MID, PULSE_WIDTH_HIGH
+};
+
+const char *pulse_width_names[] = { "level", "1", "25", "125", "5000" };
+const char *pulse_width_names_f71868[] = { "level", "1", "30", "150", "6000" };
+
+enum wdtrst_pin {
+	WDTRST_PIN_56, WDTRST_PIN_63,
+};
+
+const char *f71862fg_pin_names[] = { "56", "63" };
+
+enum chips { f71808fg, f71858fg, f71862fg, f71868, f71869, f71882fg, f71889fg,
+	     f81865, f81866};
+
+struct f71808e_wdt;
+
+struct f71808e_variant_data {
+	enum chips	type;
+	void (*pinconf)(struct f71808e_wdt *wd);
+};
+
+struct f71808e_wdt {
+	struct watchdog wdd;
+	u16		sioaddr;
+	const struct f71808e_variant_data *variant;
+	unsigned int	timeout;
+	u8		timer_val;	/* content for the wd_time register */
+	char		minutes_mode;
+	int		pulse_width;
+	int		f71862fg_pin;
+};
+
+static inline struct f71808e_wdt *to_f71808e_wdt(struct watchdog *wdd)
+{
+	return container_of(wdd, struct f71808e_wdt, wdd);
+}
+
+static inline bool has_f81865_wdo_conf(struct f71808e_wdt *wd)
+{
+	return wd->variant->type == f81865 || wd->variant->type == f81866;
+}
+
+static inline void superio_enter(u16 base)
+{
+	/* according to the datasheet the key must be sent twice! */
+	outb(SIO_UNLOCK_KEY, base);
+	outb(SIO_UNLOCK_KEY, base);
+}
+
+static inline void superio_select(u16 base, int ld)
+{
+	outb(SIO_REG_LDSEL, base);
+	outb(ld, base + 1);
+}
+
+static inline void superio_exit(u16 base)
+{
+	outb(SIO_LOCK_KEY, base);
+}
+
+static void f71808e_wdt_keepalive(struct f71808e_wdt *wd)
+{
+	superio_enter(wd->sioaddr);
+
+	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
+
+	if (wd->minutes_mode)
+		/* select minutes for timer units */
+		superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
+				F71808FG_FLAG_WD_UNIT);
+	else
+		/* select seconds for timer units */
+		superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
+				F71808FG_FLAG_WD_UNIT);
+
+	/* Set timer value */
+	superio_outb(wd->sioaddr, F71808FG_REG_WD_TIME,
+		     wd->timer_val);
+
+	superio_exit(wd->sioaddr);
+}
+
+static void f71808e_wdt_start(struct f71808e_wdt *wd)
+{
+	/* Make sure we don't die as soon as the watchdog is enabled below */
+	f71808e_wdt_keepalive(wd);
+
+	superio_enter(wd->sioaddr);
+
+	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
+
+	/* Watchdog pin configuration */
+	wd->variant->pinconf(wd);
+
+	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
+	superio_set_bit(wd->sioaddr, SIO_REG_ENABLE, 0);
+
+	if (has_f81865_wdo_conf(wd))
+		superio_set_bit(wd->sioaddr, F81865_REG_WDO_CONF,
+				F81865_FLAG_WDOUT_EN);
+	else
+		superio_set_bit(wd->sioaddr, F71808FG_REG_WDO_CONF,
+				F71808FG_FLAG_WDOUT_EN);
+
+	superio_set_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
+			F71808FG_FLAG_WD_EN);
+
+	if (wd->pulse_width > 0) {
+		/* Select "pulse" output mode with given duration */
+		u8 wdt_conf = superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF);
+
+		/* Set WD_PSWIDTH bits (1:0) */
+		wdt_conf = (wdt_conf & 0xfc) | (wd->pulse_width & 0x03);
+		/* Set WD_PULSE to "pulse" mode */
+		wdt_conf |= BIT(F71808FG_FLAG_WD_PULSE);
+
+		superio_outb(wd->sioaddr, F71808FG_REG_WDT_CONF, wdt_conf);
+	} else {
+		/* Select "level" output mode */
+		superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
+				  F71808FG_FLAG_WD_PULSE);
+	}
+
+	superio_exit(wd->sioaddr);
+}
+
+static void f71808e_wdt_stop(struct f71808e_wdt *wd)
+{
+	superio_enter(wd->sioaddr);
+
+	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
+
+	superio_clear_bit(wd->sioaddr, F71808FG_REG_WDT_CONF,
+			  F71808FG_FLAG_WD_EN);
+
+	superio_exit(wd->sioaddr);
+}
+
+static int f71808e_wdt_set_timeout(struct watchdog *wdd, unsigned int new_timeout)
+{
+	struct f71808e_wdt *wd = to_f71808e_wdt(wdd);
+
+	if (!new_timeout) {
+		f71808e_wdt_stop(wd);
+		return 0;
+	}
+
+	if (wd->timeout != new_timeout) {
+		if (new_timeout > 0xff) {
+			wd->timer_val = DIV_ROUND_UP(new_timeout, 60);
+			wd->minutes_mode = true;
+		} else {
+			wd->timer_val = new_timeout;
+			wd->minutes_mode = false;
+		}
+
+		f71808e_wdt_start(wd);
+		wd->timeout = new_timeout;
+	}
+
+	f71808e_wdt_keepalive(wd);
+	return 0;
+}
+
+static int f71808e_wdt_init(struct f71808e_wdt *wd, struct device_d *dev)
+{
+	struct watchdog *wdd = &wd->wdd;
+	const char * const *names = pulse_width_names;
+	int wdt_conf;
+	int ret;
+
+	superio_enter(wd->sioaddr);
+
+	superio_select(wd->sioaddr, SIO_F71808FG_LD_WDT);
+
+	wdt_conf = superio_inb(wd->sioaddr, F71808FG_REG_WDT_CONF);
+
+	superio_exit(wd->sioaddr);
+
+	if (wd->variant->type == f71868)
+		names = pulse_width_names_f71868;
+
+	wd->pulse_width = PULSE_WIDTH_MID; /* either 125ms or 150ms */
+
+	dev_add_param_enum(dev, "pulse_width_ms", NULL, NULL,
+			   &wd->pulse_width, names,
+			   ARRAY_SIZE(pulse_width_names),
+			   wd);
+
+	if (wd->variant->type == f71862fg) {
+		wd->f71862fg_pin = WDTRST_PIN_63;
+
+		dev_add_param_enum(dev, "wdtrst_pin", NULL, NULL,
+				   &wd->f71862fg_pin, f71862fg_pin_names,
+				   ARRAY_SIZE(f71862fg_pin_names),
+				   wd);
+	}
+
+	wdd->hwdev		= dev;
+	wdd->set_timeout	= &f71808e_wdt_set_timeout;
+	wdd->timeout_max	= WATCHDOG_MAX_TIMEOUT;
+
+	if (wdt_conf & BIT(F71808FG_FLAG_WDTMOUT_STS))
+		reset_source_set_priority(RESET_WDG,
+					  RESET_SOURCE_DEFAULT_PRIORITY);
+
+	dev_info(dev, "reset reason: %s\n", reset_source_name());
+
+	ret = watchdog_register(wdd);
+	if (ret)
+		return ret;
+
+	superio_enter(wd->sioaddr);
+	dev_info(dev, "revision %d probed.\n",
+		 superio_inb(wd->sioaddr, SIO_REG_DEVREV));
+	superio_exit(wd->sioaddr);
+
+	return 0;
+}
+
+static void f71808fg_pinconf(struct f71808e_wdt *wd)
+{
+	/* Set pin 21 to GPIO23/WDTRST#, then to WDTRST# */
+	superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT2, 3);
+	superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 3);
+}
+static void f71862fg_pinconf(struct f71808e_wdt *wd)
+{
+	u16 ioaddr = wd->sioaddr;
+
+	if (wd->f71862fg_pin == WDTRST_PIN_63) {
+		/* SPI must be disabled first to use this pin! */
+		superio_clear_bit(ioaddr, SIO_REG_ROM_ADDR_SEL, 6);
+		superio_set_bit(ioaddr, SIO_REG_MFUNCT3, 4);
+	} else if (wd->f71862fg_pin == WDTRST_PIN_56) {
+		superio_set_bit(ioaddr, SIO_REG_MFUNCT1, 1);
+	}
+}
+static void f71868_pinconf(struct f71808e_wdt *wd)
+{
+	/* GPIO14 --> WDTRST# */
+	superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT1, 4);
+}
+static void f71882fg_pinconf(struct f71808e_wdt *wd)
+{
+	/* Set pin 56 to WDTRST# */
+	superio_set_bit(wd->sioaddr, SIO_REG_MFUNCT1, 1);
+}
+static void f71889fg_pinconf(struct f71808e_wdt *wd)
+{
+	/* set pin 40 to WDTRST# */
+	superio_outb(wd->sioaddr, SIO_REG_MFUNCT3,
+		superio_inb(wd->sioaddr, SIO_REG_MFUNCT3) & 0xcf);
+}
+static void f81865_pinconf(struct f71808e_wdt *wd)
+{
+	/* Set pin 70 to WDTRST# */
+	superio_clear_bit(wd->sioaddr, SIO_REG_MFUNCT3, 5);
+}
+static void f81866_pinconf(struct f71808e_wdt *wd)
+{
+	/*
+	 * GPIO1 Control Register when 27h BIT3:2 = 01 & BIT0 = 0.
+	 * The PIN 70(GPIO15/WDTRST) is controlled by 2Ch:
+	 *     BIT5: 0 -> WDTRST#
+	 *           1 -> GPIO15
+	 */
+	u8 tmp = superio_inb(wd->sioaddr, SIO_F81866_REG_PORT_SEL);
+	tmp &= ~(BIT(3) | BIT(0));
+	tmp |= BIT(2);
+	superio_outb(wd->sioaddr, SIO_F81866_REG_PORT_SEL, tmp);
+
+	superio_clear_bit(wd->sioaddr, SIO_F81866_REG_GPIO1, 5);
+}
+
+static struct f71808e_variant_data f71808fg_data = { .type = f71808fg, .pinconf = f71808fg_pinconf };
+static struct f71808e_variant_data f71862fg_data = { .type = f71862fg, .pinconf = f71862fg_pinconf };
+static struct f71808e_variant_data f71868_data = { .type = f71868, .pinconf = f71868_pinconf };
+static struct f71808e_variant_data f71869_data = { .type = f71869, .pinconf = f71868_pinconf };
+static struct f71808e_variant_data f71882fg_data = { .type = f71882fg, .pinconf = f71882fg_pinconf };
+static struct f71808e_variant_data f71889fg_data = { .type = f71889fg, .pinconf = f71889fg_pinconf };
+static struct f71808e_variant_data f81865_data = { .type = f81865, .pinconf = f81865_pinconf };
+static struct f71808e_variant_data f81866_data = { .type = f81866, .pinconf = f81866_pinconf };
+
+static struct platform_device_id f71808e_wdt_ids[] = {
+	{ .name = "f71808fg_wdt", .driver_data = (unsigned long)&f71808fg_data },
+	{ .name = "f71862fg_wdt", .driver_data = (unsigned long)&f71862fg_data },
+	{ .name = "f71868_wdt", .driver_data = (unsigned long)&f71868_data },
+	{ .name = "f71869_wdt", .driver_data = (unsigned long)&f71869_data },
+	{ .name = "f71882fg_wdt", .driver_data = (unsigned long)&f71882fg_data },
+	{ .name = "f71889fg_wdt", .driver_data = (unsigned long)&f71889fg_data },
+	{ .name = "f81865_wdt", .driver_data = (unsigned long)&f81865_data },
+	{ .name = "f81866_wdt", .driver_data = (unsigned long)&f81866_data },
+	{ /* sentinel */ },
+};
+
+static int f71808e_probe(struct device_d *dev)
+{
+	struct f71808e_wdt *wd;
+	struct resource *res;
+	int ret;
+
+	wd = xzalloc(sizeof(*wd));
+
+	ret = dev_get_drvdata(dev, (const void **)&wd->variant);
+	if (ret)
+		return ret;
+
+	res = dev_get_resource(dev->parent, IORESOURCE_IO, 0);
+	if (IS_ERR(res))
+		return PTR_ERR(res);
+	wd->sioaddr = res->start;
+
+	return f71808e_wdt_init(wd, dev);
+}
+
+static struct driver_d f71808e_wdt_driver = {
+	.probe	= f71808e_probe,
+	.name	= "f71808e_wdt",
+	.id_table = f71808e_wdt_ids,
+};
+
+device_platform_driver(f71808e_wdt_driver);
-- 
2.23.0


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH 4/4] mfd: superio: add base SMSC MFD driver
  2019-10-11 16:27 [PATCH 1/4] mfd: add basic Super I/O chip helpers Ahmad Fatoum
  2019-10-11 16:27 ` [PATCH 2/4] mfd: superio: add Fintek MFD driver Ahmad Fatoum
  2019-10-11 16:27 ` [PATCH 3/4] watchdog: add support for Fintek F718xx and, F818xx Super I/O Ahmad Fatoum
@ 2019-10-11 16:27 ` Ahmad Fatoum
  2019-10-14 13:18 ` [PATCH 1/4] mfd: add basic Super I/O chip helpers Sascha Hauer
  3 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2019-10-11 16:27 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

From: Ahmad Fatoum <ahmad@a3f.at>

The SMSC FDC37C93xAPM is the Super I/O chip on the Dell Latitude 7490.
This adds device detection for it and its siblings, so device drivers
can be written against it or init scripts can use its regmap interface.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 drivers/mfd/Kconfig        |   6 ++
 drivers/mfd/Makefile       |   1 +
 drivers/mfd/smsc-superio.c | 115 +++++++++++++++++++++++++++++++++++++
 3 files changed, 122 insertions(+)
 create mode 100644 drivers/mfd/smsc-superio.c

diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index e2c74a575da4..f4cc71ef0ec8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -76,4 +76,10 @@ config FINTEK_SUPERIO
        help
          Select this to probe for IO-port connected Fintek Super I/O chips.
 
+config SMSC_SUPERIO
+       bool "SMSC Super I/O chip"
+       select MFD_SUPERIO
+       help
+         Select this to probe for IO-port connected SMSC Super I/O chips.
+
 endmenu
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 59b401dd2ea0..0c24493e3d86 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -14,3 +14,4 @@ obj-$(CONFIG_RAVE_SP_CORE)	+= rave-sp.o
 obj-$(CONFIG_MFD_STPMIC1)	+= stpmic1.o
 obj-$(CONFIG_MFD_SUPERIO)	+= superio.o
 obj-$(CONFIG_FINTEK_SUPERIO)	+= fintek-superio.o
+obj-$(CONFIG_SMSC_SUPERIO)	+= smsc-superio.o
diff --git a/drivers/mfd/smsc-superio.c b/drivers/mfd/smsc-superio.c
new file mode 100644
index 000000000000..349c878cefe0
--- /dev/null
+++ b/drivers/mfd/smsc-superio.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#define pr_fmt(fmt) "smsc-superio: " fmt
+
+#include <superio.h>
+#include <init.h>
+#include <asm/io.h>
+#include <common.h>
+
+#define SIO_UNLOCK_KEY		0x55	/* Key to enable Super-I/O */
+#define SIO_LOCK_KEY		0xAA	/* Key to disable Super-I/O */
+
+#define SMSC_ID			0x10b8  /* Standard Microsystems Corp PCI ID */
+
+static void superio_enter(u16 sioaddr)
+{
+	outb(SIO_UNLOCK_KEY, sioaddr);
+	mdelay(1);
+	outb(SIO_UNLOCK_KEY, sioaddr);
+}
+
+static void superio_exit(u16 sioaddr)
+{
+	outb(SIO_LOCK_KEY, sioaddr);
+}
+
+static void smsc_superio_find(u16 sioaddr, u16 id_reg)
+{
+	struct superio_chip *chip;
+	u16 devid;
+
+	superio_enter(sioaddr);
+
+	devid = superio_inw(sioaddr, id_reg);
+	switch(devid >> 8) {
+	case 0x02:
+	case 0x03:
+	case 0x07:
+	case 0x09:
+	case 0x0a:
+	case 0x0b:
+	case 0x0e:
+	case 0x14:
+	case 0x30:
+	case 0x40:
+	case 0x42:
+	case 0x43:
+	case 0x44:
+	case 0x46:
+	case 0x47:
+	case 0x4c:
+	case 0x4d:
+	case 0x51:
+	case 0x52:
+	case 0x54:
+	case 0x56:
+	case 0x57:
+	case 0x59:
+	case 0x5d:
+	case 0x5f:
+	case 0x60:
+	case 0x62:
+	case 0x67:
+	case 0x6b:
+	case 0x6e:
+	case 0x6f:
+	case 0x74:
+	case 0x76:
+	case 0x77:
+	case 0x78:
+	case 0x79:
+	case 0x7a:
+	case 0x7c:
+	case 0x7d:
+	case 0x7f:
+	case 0x81:
+	case 0x83:
+	case 0x85:
+	case 0x86:
+	case 0x89:
+	case 0x8c:
+	case 0x90:
+		break;
+	default:
+		pr_debug("Not a SMSC device (port=0x%02x, devid=0x%04x)\n",
+			 sioaddr, devid);
+		return;
+	}
+
+	chip = xzalloc(sizeof(*chip));
+
+	chip->devid = devid;
+	chip->vid = SMSC_ID;
+	chip->sioaddr = sioaddr;
+	chip->enter = superio_enter;
+	chip->exit = superio_exit;
+
+	superio_chip_add(chip);
+
+	superio_exit(sioaddr);
+}
+
+static int smsc_superio_detect(void)
+{
+	u16 ports[] = { 0x2e, 0x4e, 0x162e, 0x164e, 0x3f0, 0x370 };
+
+	for (int i = 0; i < ARRAY_SIZE(ports); i++)
+		smsc_superio_find(ports[i], SIO_REG_DEVID);
+
+	return 0;
+}
+coredevice_initcall(smsc_superio_detect);
-- 
2.23.0


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 3/4] watchdog: add support for Fintek F718xx and, F818xx Super I/O
  2019-10-11 16:27 ` [PATCH 3/4] watchdog: add support for Fintek F718xx and, F818xx Super I/O Ahmad Fatoum
@ 2019-10-14 12:39   ` Sascha Hauer
  2019-10-14 12:47     ` [PATCH] fixup! " Ahmad Fatoum
  0 siblings, 1 reply; 7+ messages in thread
From: Sascha Hauer @ 2019-10-14 12:39 UTC (permalink / raw)
  To: Ahmad Fatoum; +Cc: barebox

On Fri, Oct 11, 2019 at 06:27:52PM +0200, Ahmad Fatoum wrote:
> This is an adaptation of the Linux v5.3 f71808e_wdt driver for the watchdog
> component of the Fintek Super I/O chips.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  drivers/watchdog/Kconfig       |  10 +
>  drivers/watchdog/Makefile      |   1 +
>  drivers/watchdog/f71808e_wdt.c | 379 +++++++++++++++++++++++++++++++++
>  3 files changed, 390 insertions(+)
>  create mode 100644 drivers/watchdog/f71808e_wdt.c
> 
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index fbaab896d460..b1c2a39b6629 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -90,10 +90,20 @@ config STM32_IWDG_WATCHDOG
>  	  Enable to support configuration of the STM32's on-SoC IWDG watchdog.
>  	  Once started by the user, the IWDG can't be disabled.
>  
> +

Please drop this hunk.

>  config STPMIC1_WATCHDOG
>  	bool "STPMIC1 Watchdog"
>  	depends on MFD_STPMIC1
>  	help
>  	  Enable to support configuration of the stpmic1's built-in watchdog.
>  
> +config F71808E_WDT
> +	bool "Fintek F718xx, F818xx Super I/O Watchdog"
> +	depends on X86
> +	select FINTEK_SUPERIO

I prefer a "depends on" here.

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH] fixup! watchdog: add support for Fintek F718xx and, F818xx Super I/O
  2019-10-14 12:39   ` Sascha Hauer
@ 2019-10-14 12:47     ` Ahmad Fatoum
  0 siblings, 0 replies; 7+ messages in thread
From: Ahmad Fatoum @ 2019-10-14 12:47 UTC (permalink / raw)
  To: barebox; +Cc: Ahmad Fatoum

 Remove unrelated hunk, replace select with depends like suggested by
 Sascha.

---
 drivers/watchdog/Kconfig | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index b1c2a39b6629..45dd41a2a2f3 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -90,7 +90,6 @@ config STM32_IWDG_WATCHDOG
 	  Enable to support configuration of the STM32's on-SoC IWDG watchdog.
 	  Once started by the user, the IWDG can't be disabled.
 
-
 config STPMIC1_WATCHDOG
 	bool "STPMIC1 Watchdog"
 	depends on MFD_STPMIC1
@@ -100,7 +99,7 @@ config STPMIC1_WATCHDOG
 config F71808E_WDT
 	bool "Fintek F718xx, F818xx Super I/O Watchdog"
 	depends on X86
-	select FINTEK_SUPERIO
+	depends on FINTEK_SUPERIO
 	help
 	  This is the driver for the hardware watchdog on the Fintek F71808E,
 	  F71862FG, F71868, F71869, F71882FG, F71889FG, F81865 and F81866
-- 
2.23.0


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^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH 1/4] mfd: add basic Super I/O chip helpers
  2019-10-11 16:27 [PATCH 1/4] mfd: add basic Super I/O chip helpers Ahmad Fatoum
                   ` (2 preceding siblings ...)
  2019-10-11 16:27 ` [PATCH 4/4] mfd: superio: add base SMSC MFD driver Ahmad Fatoum
@ 2019-10-14 13:18 ` Sascha Hauer
  3 siblings, 0 replies; 7+ messages in thread
From: Sascha Hauer @ 2019-10-14 13:18 UTC (permalink / raw)
  To: Ahmad Fatoum; +Cc: barebox

On Fri, Oct 11, 2019 at 06:27:50PM +0200, Ahmad Fatoum wrote:
> Super I/O chips are ICs common to x86 that are used for interfacing
> to low-bandwidth peripherals. They often contain serial ports, watchdog
> timers and hardware monitoring units.
> 
> They are usually addressable via one of two I/O port pairs, either
> 0x2e-0x2f or 0x4e-0x4f, but they don't typically respond to reads from
> their range unless a device-specific 'password' has been poked in.
> After this is done, they are read and written in the same manner however.
> 
> On Linux, these devices aren't subject to any device/driver model.
> Each driver for some function (e.g. watchdog or GPIO) duplicates the
> device probe in the module_init and board-specific configuration
> is handled via module parameters.
> 
> Lets do it a bit fancier in barebox and add a helper to register chips
> and a regmap for the control and configuration registers as well as a
> helper to register child devices for each function contained within the
> Super I/O chip.
> Board-specific configuration, e.g. which pin to use as a watchdog reset,
> can then be realized using barebox device-specific parameters.
> 
> The regmap will be more of a debugging aid, however.
> For ease of porting from Linux, it's expected that access to the
> I/O ports won't happen via the regmap. For this reason, the new
> <superio.h> header offers functions to read/write these chips' registers
> as well.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---

Applied, thanks

Sascha


-- 
Pengutronix e.K.                           |                             |
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Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2019-10-14 13:18 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-11 16:27 [PATCH 1/4] mfd: add basic Super I/O chip helpers Ahmad Fatoum
2019-10-11 16:27 ` [PATCH 2/4] mfd: superio: add Fintek MFD driver Ahmad Fatoum
2019-10-11 16:27 ` [PATCH 3/4] watchdog: add support for Fintek F718xx and, F818xx Super I/O Ahmad Fatoum
2019-10-14 12:39   ` Sascha Hauer
2019-10-14 12:47     ` [PATCH] fixup! " Ahmad Fatoum
2019-10-11 16:27 ` [PATCH 4/4] mfd: superio: add base SMSC MFD driver Ahmad Fatoum
2019-10-14 13:18 ` [PATCH 1/4] mfd: add basic Super I/O chip helpers Sascha Hauer

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