[PATCH v2 1/8] pinctrl: stm32: fix debug print of uninitialized variable

[PATCH v2 1/8] pinctrl: stm32: fix debug print of uninitialized variable

[Ahmad Fatoum]

mode and alt are printed with the dev_dbg before they are initialized.
Remedy this by moving the dev_dbg after them.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/pinctrl/pinctrl-stm32.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-stm32.c b/drivers/pinctrl/pinctrl-stm32.c
index 7f04cea50b75..ab121998a37f 100644
--- a/drivers/pinctrl/pinctrl-stm32.c
+++ b/drivers/pinctrl/pinctrl-stm32.c
@@ -157,13 +157,13 @@ static int stm32_pinctrl_set_state(struct pinctrl_device *pdev, struct device_no
 			if (offset < 0)
 				return -ENODEV;
 
+			mode = stm32_gpio_get_mode(func);
+			alt = stm32_gpio_get_alt(func);
+
 			dev_dbg(pdev->dev, "configuring port %s pin %u with:\n\t"
 				"fn %u, mode %u, alt %u\n",
 				bank->name, offset, func, mode, alt);
 
-			mode = stm32_gpio_get_mode(func);
-			alt = stm32_gpio_get_alt(func);
-
 			clk_enable(bank->clk);
 
 			__stm32_pmx_set_mode(bank->base, offset, mode, alt);
-- 
2.23.0


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[PATCH v2 2/8] pinctrl: demote dev_info on successful probes to dev_dbg

[Ahmad Fatoum]

The SoC's pin controller is virtually always built and probed, so
there's is little information to gain from the fact it was successfully
probed. Have the success message show up as debug message to reduce probe
clutter like this:

	NOTICE: stm32-pinctrl soc:pin-controller@50002000.of: pinctrl/gpio driver registered
	NOTICE: stm32-pinctrl soc:pin-controller-z@54004000.of: pinctrl/gpio driver registered

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/pinctrl/pinctrl-at91-pio4.c | 4 ++--
 drivers/pinctrl/pinctrl-bcm2835.c   | 2 +-
 drivers/pinctrl/pinctrl-stm32.c     | 2 +-
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-at91-pio4.c b/drivers/pinctrl/pinctrl-at91-pio4.c
index 9bc259f84cca..b527114f1ba0 100644
--- a/drivers/pinctrl/pinctrl-at91-pio4.c
+++ b/drivers/pinctrl/pinctrl-at91-pio4.c
@@ -260,7 +260,7 @@ static int pinctrl_at91_pio4_gpiochip_add(struct device_d *dev,
 		return ret;
 	}
 
-	dev_info(dev, "gpio driver registered\n");
+	dev_dbg(dev, "gpio driver registered\n");
 
 	return 0;
 }
@@ -290,7 +290,7 @@ static int pinctrl_at91_pio4_probe(struct device_d *dev)
 	if (ret)
 		return ret;
 
-	dev_info(dev, "pinctrl driver registered\n");
+	dev_dbg(dev, "pinctrl driver registered\n");
 
 	if (of_get_property(np, "gpio-controller", NULL))
 		return pinctrl_at91_pio4_gpiochip_add(dev, pinctrl);
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 5fd5740e8184..b8e9b60372e3 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -171,7 +171,7 @@ static int bcm2835_gpio_probe(struct device_d *dev)
 		goto err;
 	}
 
-	dev_info(dev, "probed gpiochip%d with base %d\n", dev->id, bcmgpio->chip.base);
+	dev_dbg(dev, "probed gpiochip%d with base %d\n", dev->id, bcmgpio->chip.base);
 
 	if (IS_ENABLED(CONFIG_PINCTRL)) {
 		ret = pinctrl_register(&bcmgpio->pctl);
diff --git a/drivers/pinctrl/pinctrl-stm32.c b/drivers/pinctrl/pinctrl-stm32.c
index ab121998a37f..c199d74846e8 100644
--- a/drivers/pinctrl/pinctrl-stm32.c
+++ b/drivers/pinctrl/pinctrl-stm32.c
@@ -401,7 +401,7 @@ static int stm32_pinctrl_probe(struct device_d *dev)
 		}
 	}
 
-	dev_info(dev, "pinctrl/gpio driver registered\n");
+	dev_dbg(dev, "pinctrl/gpio driver registered\n");
 
 	return 0;
 }
-- 
2.23.0


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[PATCH v2 3/8] pinctrl: stm32: parse pinctrl nodes without subnodes as well

[Ahmad Fatoum]

The bindings allow the pinmux node to occur directly in the node under
the pin controller as well. Check for this and support both types of
pinctrl specification.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 drivers/pinctrl/pinctrl-stm32.c | 180 ++++++++++++++++++--------------
 1 file changed, 99 insertions(+), 81 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-stm32.c b/drivers/pinctrl/pinctrl-stm32.c
index c199d74846e8..cdaed510c564 100644
--- a/drivers/pinctrl/pinctrl-stm32.c
+++ b/drivers/pinctrl/pinctrl-stm32.c
@@ -87,110 +87,128 @@ static inline u32 stm32_gpio_get_alt(u32 function)
 	return 0;
 }
 
-static int stm32_pinctrl_set_state(struct pinctrl_device *pdev, struct device_node *group)
+static int __stm32_pinctrl_set_state(struct device_d *dev, struct device_node *pins)
 {
-	struct stm32_pinctrl *pinctrl = to_stm32_pinctrl(pdev);
-	struct device_node *pins;
 	int ret;
 
-	ret = hwspinlock_lock_timeout(&pinctrl->hws, 10);
-	if (ret == -ETIMEDOUT) {
-		dev_err(pdev->dev, "hw spinlock timeout\n");
-		return ret;
+	int num_pins = 0, i;
+	u32 slew_rate;
+	bool adjust_slew_rate = false;
+	enum stm32_pin_bias bias = -1;
+	enum stm32_pin_out_type out_type = -1;
+	enum { PIN_INPUT, PIN_OUTPUT_LOW, PIN_OUTPUT_HIGH } dir = -1;
+
+	of_get_property(pins, "pinmux", &num_pins);
+	num_pins /= sizeof(__be32);
+	if (!num_pins) {
+		dev_err(dev, "Invalid pinmux property in %s\n",
+			pins->full_name);
+		return -EINVAL;
 	}
 
-	for_each_child_of_node(group, pins) {
-		int num_pins = 0, i;
-		u32 slew_rate;
-		bool adjust_slew_rate = false;
-		enum stm32_pin_bias bias = -1;
-		enum stm32_pin_out_type out_type = -1;
-		enum { PIN_INPUT, PIN_OUTPUT_LOW, PIN_OUTPUT_HIGH } dir = -1;
-
-		of_get_property(pins, "pinmux", &num_pins);
-		num_pins /= sizeof(__be32);
-		if (!num_pins) {
-			dev_err(pdev->dev, "Invalid pinmux property in %s\n",
-				pins->full_name);
-			return -EINVAL;
-		}
-
-		ret = of_property_read_u32(pins, "slew-rate", &slew_rate);
-		if (!ret)
-			adjust_slew_rate = true;
-
-		if (of_get_property(pins, "bias-disable", NULL))
-			bias = STM32_PIN_NO_BIAS;
-		else if (of_get_property(pins, "bias-pull-up", NULL))
-			bias = STM32_PIN_PULL_UP;
-		else if (of_get_property(pins, "bias-pull-down", NULL))
-			bias = STM32_PIN_PULL_DOWN;
+	ret = of_property_read_u32(pins, "slew-rate", &slew_rate);
+	if (!ret)
+		adjust_slew_rate = true;
+
+	if (of_get_property(pins, "bias-disable", NULL))
+		bias = STM32_PIN_NO_BIAS;
+	else if (of_get_property(pins, "bias-pull-up", NULL))
+		bias = STM32_PIN_PULL_UP;
+	else if (of_get_property(pins, "bias-pull-down", NULL))
+		bias = STM32_PIN_PULL_DOWN;
+
+	if (of_get_property(pins, "drive-push-pull", NULL))
+		out_type = STM32_PIN_OUT_PUSHPULL;
+	else if (of_get_property(pins, "drive-open-drain", NULL))
+		out_type = STM32_PIN_OUT_OPENDRAIN;
+
+	if (of_get_property(pins, "input-enable", NULL))
+		dir = PIN_INPUT;
+	else if (of_get_property(pins, "output-low", NULL))
+		dir = PIN_OUTPUT_LOW;
+	else if (of_get_property(pins, "output-high", NULL))
+		dir = PIN_OUTPUT_HIGH;
+
+	dev_dbg(dev, "%s: multiplexing %d pins\n", pins->full_name, num_pins);
+
+	for (i = 0; i < num_pins; i++) {
+		struct stm32_gpio_bank *bank = NULL;
+		u32 pinfunc, mode, alt;
+		unsigned func;
+		int offset;
+
+		ret = of_property_read_u32_index(pins, "pinmux",
+				i, &pinfunc);
+		if (ret)
+			return ret;
 
-		if (of_get_property(pins, "drive-push-pull", NULL))
-			out_type = STM32_PIN_OUT_PUSHPULL;
-		else if (of_get_property(pins, "drive-open-drain", NULL))
-			out_type = STM32_PIN_OUT_OPENDRAIN;
+		func = STM32_GET_PIN_FUNC(pinfunc);
+		offset = stm32_gpio_pin(STM32_GET_PIN_NO(pinfunc), &bank);
+		if (offset < 0)
+			return -ENODEV;
 
-		if (of_get_property(pins, "input-enable", NULL))
-			dir = PIN_INPUT;
-		else if (of_get_property(pins, "output-low", NULL))
-			dir = PIN_OUTPUT_LOW;
-		else if (of_get_property(pins, "output-high", NULL))
-			dir = PIN_OUTPUT_HIGH;
+		mode = stm32_gpio_get_mode(func);
+		alt = stm32_gpio_get_alt(func);
 
-		dev_dbg(pdev->dev, "%s: multiplexing %d pins\n",
-			pins->full_name, num_pins);
+		dev_dbg(dev, "configuring port %s pin %u with:\n\t"
+			"fn %u, mode %u, alt %u\n",
+			bank->name, offset, func, mode, alt);
 
-		for (i = 0; i < num_pins; i++) {
-			struct stm32_gpio_bank *bank = NULL;
-			u32 pinfunc, mode, alt;
-			unsigned func;
-			int offset;
+		clk_enable(bank->clk);
 
-			ret = of_property_read_u32_index(pins, "pinmux",
-					i, &pinfunc);
-			if (ret)
-				return ret;
+		__stm32_pmx_set_mode(bank->base, offset, mode, alt);
 
-			func = STM32_GET_PIN_FUNC(pinfunc);
-			offset = stm32_gpio_pin(STM32_GET_PIN_NO(pinfunc), &bank);
-			if (offset < 0)
-				return -ENODEV;
+		if (adjust_slew_rate)
+			__stm32_pmx_set_speed(bank->base, offset, slew_rate);
 
-			mode = stm32_gpio_get_mode(func);
-			alt = stm32_gpio_get_alt(func);
+		if (bias != -1)
+			__stm32_pmx_set_bias(bank->base, offset, bias);
 
-			dev_dbg(pdev->dev, "configuring port %s pin %u with:\n\t"
-				"fn %u, mode %u, alt %u\n",
-				bank->name, offset, func, mode, alt);
+		if (out_type != -1)
+			__stm32_pmx_set_output_type(bank->base, offset, out_type);
 
-			clk_enable(bank->clk);
+		if (dir == PIN_INPUT)
+			__stm32_pmx_gpio_input(bank->base, offset);
+		else if (dir == PIN_OUTPUT_LOW)
+			__stm32_pmx_gpio_output(bank->base, offset, 0);
+		else if (dir == PIN_OUTPUT_HIGH)
+			__stm32_pmx_gpio_output(bank->base, offset, 1);
 
-			__stm32_pmx_set_mode(bank->base, offset, mode, alt);
+		clk_disable(bank->clk);
+	}
 
-			if (adjust_slew_rate)
-				__stm32_pmx_set_speed(bank->base, offset, slew_rate);
+	return 0;
+}
 
-			if (bias != -1)
-				__stm32_pmx_set_bias(bank->base, offset, bias);
+static int stm32_pinctrl_set_state(struct pinctrl_device *pdev, struct device_node *np)
+{
+	struct stm32_pinctrl *pinctrl = to_stm32_pinctrl(pdev);
+	struct device_d *dev = pdev->dev;
+	struct device_node *pins;
+	void *prop;
+	int ret;
 
-			if (out_type != -1)
-				__stm32_pmx_set_output_type(bank->base, offset, out_type);
+	ret = hwspinlock_lock_timeout(&pinctrl->hws, 10);
+	if (ret == -ETIMEDOUT) {
+		dev_err(dev, "hw spinlock timeout\n");
+		return ret;
+	}
 
-			if (dir == PIN_INPUT)
-				__stm32_pmx_gpio_input(bank->base, offset);
-			else if (dir == PIN_OUTPUT_LOW)
-				__stm32_pmx_gpio_output(bank->base, offset, 0);
-			else if (dir == PIN_OUTPUT_HIGH)
-				__stm32_pmx_gpio_output(bank->base, offset, 1);
+	prop = of_find_property(np, "pinmux", NULL);
+	if (prop) {
+		ret = __stm32_pinctrl_set_state(dev, np);
+		goto out;
+	}
 
-			clk_disable(bank->clk);
-		}
+	for_each_child_of_node(np, pins) {
+		ret = __stm32_pinctrl_set_state(dev, pins);
+		if (ret)
+			goto out;
 	}
 
+out:
 	hwspinlock_unlock(&pinctrl->hws);
-
-	return 0;
+	return ret;
 }
 
 /* GPIO functions */
-- 
2.23.0


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[PATCH v2 4/8] ARM: sm: document SMC/PSCI related options

[Ahmad Fatoum]

At least to me, the difference between these options were confusing at
first. Clear this up.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/Kconfig | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 725ea12a8c57..d4947cef5c98 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -427,10 +427,14 @@ config ARM_SEMIHOSTING
 
 config ARM_SMCCC
 	bool
+	help
+	  This option enables barebox to invoke ARM secure monitor calls.
 
 config ARM_SECURE_MONITOR
 	select ARM_SMCCC
 	bool
+	help
+	  This option enables barebox to service ARM secure monitor calls.
 
 config ARM_PSCI_OF
 	bool
@@ -442,7 +446,7 @@ config ARM_PSCI
 	select ARM_PSCI_OF
 	help
 	  PSCI is used for controlling secondary CPU cores on some systems. Say
-	  yes here if you have one of these.
+	  yes here if you want barebox to service PSCI calls on such systems.
 
 config ARM_PSCI_DEBUG
 	bool "Enable PSCI debugging"
-- 
2.23.0


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[PATCH v2 5/8] ARM: stm32mp: select ARM_SMCCC always

[Ahmad Fatoum]

ARM_SMCCC compiles in the code for issuing ARM secure monitor calls.
We need those on the STM32MP, because barebox runs in non-secure mode
and does some operations like reading the BSEC OTP through SMCs.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d4947cef5c98..f82844a83a5e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -201,6 +201,7 @@ config ARCH_STM32MP
 	select GPIOLIB
 	select ARCH_HAS_RESET_CONTROLLER
 	select ARM_AMBA
+	select ARM_SMCCC
 
 config ARCH_VERSATILE
 	bool "ARM Versatile boards (ARM926EJ-S)"
-- 
2.23.0


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[PATCH v2 6/8] nvmem: add read support for STM32MP1 bsec OTP

[Ahmad Fatoum]

The bsec on the STM32MP157C provides a 380 byte OTP. Add initial support
for reading and writing the shadow copy of the fuses. Direct fuse
access is not yet supported.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/dts/stm32mp157c.dtsi             |   4 +
 arch/arm/mach-stm32mp/include/mach/bsec.h |  41 ++++
 arch/arm/mach-stm32mp/include/mach/smc.h  |  28 +++
 drivers/nvmem/Kconfig                     |   8 +
 drivers/nvmem/Makefile                    |   5 +-
 drivers/nvmem/bsec.c                      | 221 ++++++++++++++++++++++
 6 files changed, 306 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-stm32mp/include/mach/bsec.h
 create mode 100644 arch/arm/mach-stm32mp/include/mach/smc.h
 create mode 100644 drivers/nvmem/bsec.c

diff --git a/arch/arm/dts/stm32mp157c.dtsi b/arch/arm/dts/stm32mp157c.dtsi
index 8d9c84a04785..771139c28af0 100644
--- a/arch/arm/dts/stm32mp157c.dtsi
+++ b/arch/arm/dts/stm32mp157c.dtsi
@@ -20,3 +20,7 @@
 		gpio25 = &gpioz;
 	};
 };
+
+&bsec {
+	barebox,provide-mac-address = <&ethernet0 0x39>;
+};
diff --git a/arch/arm/mach-stm32mp/include/mach/bsec.h b/arch/arm/mach-stm32mp/include/mach/bsec.h
new file mode 100644
index 000000000000..559faaa2bac3
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/bsec.h
@@ -0,0 +1,41 @@
+#ifndef __MACH_STM32_BSEC_H__
+#define __MACH_STM32_BSEC_H__
+
+#include <mach/smc.h>
+
+/* Return status */
+enum bsec_smc {
+	BSEC_SMC_OK		= 0,
+	BSEC_SMC_ERROR		= -1,
+	BSEC_SMC_DISTURBED	= -2,
+	BSEC_SMC_INVALID_PARAM	= -3,
+	BSEC_SMC_PROG_FAIL	= -4,
+	BSEC_SMC_LOCK_FAIL	= -5,
+	BSEC_SMC_WRITE_FAIL	= -6,
+	BSEC_SMC_SHADOW_FAIL	= -7,
+	BSEC_SMC_TIMEOUT	= -8,
+};
+
+/* Service for BSEC */
+enum bsec_field {
+	BSEC_SMC_READ_SHADOW	= 1,
+	BSEC_SMC_PROG_OTP	= 2,
+	BSEC_SMC_WRITE_SHADOW	= 3,
+	BSEC_SMC_READ_OTP	= 4,
+	BSEC_SMC_READ_ALL	= 5,
+	BSEC_SMC_WRITE_ALL	= 6,
+};
+
+static inline enum bsec_smc bsec_read_field(enum bsec_field field, unsigned *val)
+{
+	return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_READ_SHADOW,
+			   field, 0, val);
+}
+
+static inline enum bsec_smc bsec_write_field(enum bsec_field field, unsigned val)
+{
+	return stm32mp_smc(STM32_SMC_BSEC, BSEC_SMC_WRITE_SHADOW,
+			   field, val, NULL);
+}
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/smc.h b/arch/arm/mach-stm32mp/include/mach/smc.h
new file mode 100644
index 000000000000..6b8e62bd5302
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/smc.h
@@ -0,0 +1,28 @@
+#ifndef __MACH_STM32_SMC_H__
+#define __MACH_STM32_SMC_H__
+
+#include <linux/arm-smccc.h>
+
+/* Secure Service access from Non-secure */
+#define STM32_SMC_RCC                   0x82001000
+#define STM32_SMC_PWR                   0x82001001
+#define STM32_SMC_RTC                   0x82001002
+#define STM32_SMC_BSEC                  0x82001003
+
+/* Register access service use for RCC/RTC/PWR */
+#define STM32_SMC_REG_WRITE             0x1
+#define STM32_SMC_REG_SET               0x2
+#define STM32_SMC_REG_CLEAR             0x3
+
+static inline int stm32mp_smc(u32 svc, u8 op, u32 data1, u32 data2, u32 *val)
+{
+        struct arm_smccc_res res;
+
+        arm_smccc_smc(svc, op, data1, data2, 0, 0, 0, 0, &res);
+        if (val)
+                *val = res.a1;
+
+        return (int)res.a0;
+}
+
+#endif
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index c28a6d4e43c8..968342b281ad 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -51,4 +51,12 @@ config EEPROM_93XX46
 	  supports both read and write commands and also the command to
 	  erase the whole EEPROM.
 
+config STM32_BSEC
+	tristate "STM32 Boot and security and OTP control"
+	depends on ARCH_STM32MP
+	depends on OFDEVICE
+	help
+	  This adds support for the STM32 OTP controller. Reads and writes
+	  to will go to the shadow RAM, not the OTP fuses themselvers.
+
 endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index abf9dae429e2..7101c5aca44c 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -16,4 +16,7 @@ obj-$(CONFIG_RAVE_SP_EEPROM)	+= nvmem-rave-sp-eeprom.o
 nvmem-rave-sp-eeprom-y		:= rave-sp-eeprom.o
 
 obj-$(CONFIG_EEPROM_93XX46)	+= nvmem_eeprom_93xx46.o
-nvmem_eeprom_93xx46-y		:= eeprom_93xx46.o
\ No newline at end of file
+nvmem_eeprom_93xx46-y		:= eeprom_93xx46.o
+
+obj-$(CONFIG_STM32_BSEC)	+= nvmem_bsec.o
+nvmem_bsec-y			:= bsec.o
diff --git a/drivers/nvmem/bsec.c b/drivers/nvmem/bsec.c
new file mode 100644
index 000000000000..8235d468d16d
--- /dev/null
+++ b/drivers/nvmem/bsec.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#include <common.h>
+#include <driver.h>
+#include <malloc.h>
+#include <xfuncs.h>
+#include <errno.h>
+#include <init.h>
+#include <net.h>
+#include <io.h>
+#include <of.h>
+#include <regmap.h>
+#include <mach/bsec.h>
+#include <machine_id.h>
+#include <linux/nvmem-provider.h>
+
+#define BSEC_OTP_SERIAL	13
+
+struct bsec_priv {
+	struct regmap *map;
+	u32 svc_id;
+	struct device_d dev;
+	struct regmap_config map_config;
+	struct nvmem_config config;
+};
+
+struct stm32_bsec_data {
+	unsigned long svc_id;
+	int num_regs;
+};
+
+static int bsec_smc(struct bsec_priv *priv, u8 op, enum bsec_field field,
+		    unsigned data2, unsigned *val)
+{
+	enum bsec_smc ret = stm32mp_smc(priv->svc_id, op, field / 4, data2, val);
+	switch(ret)
+	{
+	case BSEC_SMC_OK:
+		return 0;
+	case BSEC_SMC_ERROR:
+	case BSEC_SMC_DISTURBED:
+	case BSEC_SMC_PROG_FAIL:
+	case BSEC_SMC_LOCK_FAIL:
+	case BSEC_SMC_WRITE_FAIL:
+	case BSEC_SMC_SHADOW_FAIL:
+		return -EIO;
+	case BSEC_SMC_INVALID_PARAM:
+		return -EINVAL;
+	case BSEC_SMC_TIMEOUT:
+		return -ETIMEDOUT;
+	}
+
+	return -ENXIO;
+}
+
+static int st32_bsec_read_shadow(void *ctx, unsigned reg, unsigned *val)
+{
+	return bsec_smc(ctx, BSEC_SMC_READ_SHADOW, reg, 0, val);
+}
+
+static int stm32_bsec_reg_write_shadow(void *ctx, unsigned reg, unsigned val)
+{
+	return bsec_smc(ctx, BSEC_SMC_WRITE_SHADOW, reg, val, NULL);
+}
+
+static struct regmap_bus stm32_bsec_regmap_bus = {
+	.reg_write = stm32_bsec_reg_write_shadow,
+	.reg_read = st32_bsec_read_shadow,
+};
+
+static int stm32_bsec_write(struct device_d *dev, int offset,
+			    const void *val, int bytes)
+{
+	struct bsec_priv *priv = dev->parent->priv;
+
+	return regmap_bulk_write(priv->map, offset, val, bytes);
+}
+
+static int stm32_bsec_read(struct device_d *dev, int offset,
+			   void *val, int bytes)
+{
+	struct bsec_priv *priv = dev->parent->priv;
+
+	return regmap_bulk_read(priv->map, offset, val, bytes);
+}
+
+static const struct nvmem_bus stm32_bsec_nvmem_bus = {
+	.write = stm32_bsec_write,
+	.read  = stm32_bsec_read,
+};
+
+static void stm32_bsec_set_unique_machine_id(struct regmap *map)
+{
+	u32 unique_id[3];
+	int ret;
+
+	ret = regmap_bulk_read(map, BSEC_OTP_SERIAL * 4,
+			       unique_id, sizeof(unique_id));
+	if (ret)
+		return;
+
+	machine_id_set_hashable(unique_id, sizeof(unique_id));
+}
+
+static int stm32_bsec_read_mac(struct regmap *map, int offset, u8 *mac)
+{
+	u8 res[8];
+	int ret;
+
+	ret = regmap_bulk_read(map, offset * 4, res, 8);
+	if (ret)
+		return ret;
+
+	memcpy(mac, res, ETH_ALEN);
+	return 0;
+}
+
+static void stm32_bsec_init_dt(struct bsec_priv *priv)
+{
+	struct device_node *node = priv->dev.parent->device_node;
+	struct device_node *rnode;
+	u32 phandle, offset;
+	char mac[ETH_ALEN];
+	const __be32 *prop;
+
+	int len;
+	int ret;
+
+	if (!node)
+		return;
+
+	prop = of_get_property(node, "barebox,provide-mac-address", &len);
+	if (!prop)
+		return;
+
+	if (len != 2 * sizeof(__be32))
+		return;
+
+	phandle = be32_to_cpup(prop++);
+
+	rnode = of_find_node_by_phandle(phandle);
+	offset = be32_to_cpup(prop++);
+
+	ret = stm32_bsec_read_mac(priv->map, offset, mac);
+	if (ret) {
+		dev_warn(&priv->dev, "error setting MAC address: %s\n",
+			 strerror(-ret));
+		return;
+	}
+
+	of_eth_register_ethaddr(rnode, mac);
+}
+
+static int stm32_bsec_probe(struct device_d *dev)
+{
+	struct bsec_priv *priv;
+	int ret = 0;
+	const struct stm32_bsec_data *data;
+	struct nvmem_device *nvmem;
+
+	ret = dev_get_drvdata(dev, (const void **)&data);
+	if (ret)
+		return ret;
+
+	priv = xzalloc(sizeof(*priv));
+
+	priv->svc_id = data->svc_id;
+
+	dev_set_name(&priv->dev, "bsec");
+	priv->dev.parent = dev;
+	register_device(&priv->dev);
+
+	priv->map_config.reg_bits = 32;
+	priv->map_config.val_bits = 32;
+	priv->map_config.reg_stride = 4;
+	priv->map_config.max_register = data->num_regs;
+
+	priv->map = regmap_init(dev, &stm32_bsec_regmap_bus, priv, &priv->map_config);
+	if (IS_ERR(priv->map))
+		return PTR_ERR(priv->map);
+
+	priv->config.name = "stm32-bsec";
+	priv->config.dev = dev;
+	priv->config.stride = 4;
+	priv->config.word_size = 4;
+	priv->config.size = data->num_regs;
+	priv->config.bus = &stm32_bsec_nvmem_bus;
+	dev->priv = priv;
+
+	nvmem = nvmem_register(&priv->config);
+	if (IS_ERR(nvmem))
+		return PTR_ERR(nvmem);
+
+	if (IS_ENABLED(CONFIG_MACHINE_ID))
+		stm32_bsec_set_unique_machine_id(priv->map);
+
+	stm32_bsec_init_dt(priv);
+
+	return 0;
+}
+
+static struct stm32_bsec_data stm32mp15_bsec_data = {
+	.num_regs = 95 * 4,
+	.svc_id = STM32_SMC_BSEC,
+};
+
+static __maybe_unused struct of_device_id stm32_bsec_dt_ids[] = {
+	{ .compatible = "st,stm32mp15-bsec", .data = &stm32mp15_bsec_data },
+	{ /* sentinel */ }
+};
+
+static struct driver_d stm32_bsec_driver = {
+	.name	= "stm32_bsec",
+	.probe	= stm32_bsec_probe,
+	.of_compatible = DRV_OF_COMPAT(stm32_bsec_dt_ids),
+};
+postcore_platform_driver(stm32_bsec_driver);
-- 
2.23.0


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[PATCH v2 7/8] ARM: stm32mp: dk2: add barebox SD-Card update handler

[Ahmad Fatoum]

Now with the SD/MMC controller supported, lets add a bbu handler, so we
can use it to update the second stage boot loader partition.

While doing this, I noticed that making use of the bus-width = <4>
property in the device tree now makes mmc usage fail when reading the
environment:

  ERROR: error SDMMC_STA_DCRCFAIL (0x81042) for cmd 18
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
  WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
  WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
  WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12

We'll want to fix this eventually, but for now force the bus width to 1
and print a notice to the console that we've done so. This is not
enough, however because it then fails at loading the kernel from MMC:

  ERROR: Time out on waiting for SDMMC_STA. cmd 18
  ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x804) for cmd 12
  WARNING: stm32_sdmmc2_send_cmd: cmd 18 failed, retrying ...

Fixing the max frequency at 208 MHz fixes this. So do that and print a
notice for it as well.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/boards/stm32mp157c-dk2/board.c  | 14 ++++++++++++++
 arch/arm/dts/stm32mp157a-dk1.dtsi        |  4 ++++
 arch/arm/mach-stm32mp/include/mach/bbu.h | 14 ++++++++++++++
 drivers/mci/stm32_sdmmc2.c               | 15 +++++++++++++--
 4 files changed, 45 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-stm32mp/include/mach/bbu.h

diff --git a/arch/arm/boards/stm32mp157c-dk2/board.c b/arch/arm/boards/stm32mp157c-dk2/board.c
index 9cb861af85d8..5bc88781c7ba 100644
--- a/arch/arm/boards/stm32mp157c-dk2/board.c
+++ b/arch/arm/boards/stm32mp157c-dk2/board.c
@@ -4,6 +4,7 @@
 #include <init.h>
 #include <asm/memory.h>
 #include <mach/stm32.h>
+#include <mach/bbu.h>
 
 static int dk2_mem_init(void)
 {
@@ -15,3 +16,16 @@ static int dk2_mem_init(void)
 	return 0;
 }
 mem_initcall(dk2_mem_init);
+
+static int dk2_postcore_init(void)
+{
+	if (!of_machine_is_compatible("st,stm32mp157c-dk2"))
+		return 0;
+
+	stm32mp_bbu_mmc_register_handler("sd", "/dev/mmc0.ssbl",
+					 BBU_HANDLER_FLAG_DEFAULT);
+
+	return 0;
+}
+
+postcore_initcall(dk2_postcore_init);
diff --git a/arch/arm/dts/stm32mp157a-dk1.dtsi b/arch/arm/dts/stm32mp157a-dk1.dtsi
index 7f3b6fcf55ae..05a39d32e2fa 100644
--- a/arch/arm/dts/stm32mp157a-dk1.dtsi
+++ b/arch/arm/dts/stm32mp157a-dk1.dtsi
@@ -8,6 +8,10 @@
 #include <dt-bindings/gpio/gpio.h>
 
 / {
+	aliases {
+		mmc0 = &sdmmc1;
+	};
+
 	chosen {
 		environment {
 			compatible = "barebox,environment";
diff --git a/arch/arm/mach-stm32mp/include/mach/bbu.h b/arch/arm/mach-stm32mp/include/mach/bbu.h
new file mode 100644
index 000000000000..8b9504400e9e
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/bbu.h
@@ -0,0 +1,14 @@
+#ifndef MACH_STM32MP_BBU_H_
+#define MACH_STM32MP_BBU_H_
+
+#include <bbu.h>
+
+static inline int stm32mp_bbu_mmc_register_handler(const char *name,
+						   const char *devicefile,
+						   unsigned long flags)
+{
+	return bbu_register_std_file_update(name, flags, devicefile,
+					    filetype_stm32_image_v1);
+}
+
+#endif /* MACH_STM32MP_BBU_H_ */
diff --git a/drivers/mci/stm32_sdmmc2.c b/drivers/mci/stm32_sdmmc2.c
index 7346c8a3f5d6..3f0fff1258c0 100644
--- a/drivers/mci/stm32_sdmmc2.c
+++ b/drivers/mci/stm32_sdmmc2.c
@@ -627,11 +627,22 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
 	if (IS_ERR(priv->reset_ctl))
 		priv->reset_ctl = NULL;
 
+	mci_of_parse(&priv->mci);
+
 	mci->f_min = 400000;
-	/* f_max is taken from kernel v5.3 variant_stm32_sdmmc */
-	mci->f_max = 208000000;
 	mci->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
 
+	if (mci->f_max != 208000000) {
+		/* f_max is taken from kernel v5.3 variant_stm32_sdmmc */
+		dev_notice(dev, "Fixing max-frequency to 208 MHz due to driver limitation\n");
+		mci->f_max = 208000000;
+	}
+
+	if (mci->host_caps & (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA)) {
+		dev_notice(dev, "Fixing bus-width to 1 due to driver limitation\n");
+		mci->host_caps &= ~(MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
+	}
+
 	return mci_register(&priv->mci);
 
 priv_free:
-- 
2.23.0


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[PATCH v2 8/8] ARM: stm32mp: implement SoC and boot source identification

[Ahmad Fatoum]

The BSEC OTP holds information about SoC type and package.
The Tamp registers hold information from the BootROM about boot
source. Add support for both.

Additionally, the tamp registers can also hold a request from the
operating system about what mode to enter after boot, e.g.
boot-into-recovery. A global function is exported for this, but
unused so far.

Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
 arch/arm/mach-stm32mp/Makefile                |   3 +-
 .../mach-stm32mp/include/mach/bootsource.h    |  33 +++
 arch/arm/mach-stm32mp/include/mach/revision.h |  32 +++
 arch/arm/mach-stm32mp/init.c                  | 260 ++++++++++++++++++
 4 files changed, 327 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/mach-stm32mp/include/mach/bootsource.h
 create mode 100644 arch/arm/mach-stm32mp/include/mach/revision.h
 create mode 100644 arch/arm/mach-stm32mp/init.c

diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile
index 204cad608f56..6f495288923a 100644
--- a/arch/arm/mach-stm32mp/Makefile
+++ b/arch/arm/mach-stm32mp/Makefile
@@ -1 +1,2 @@
-obj-$(CONFIG_BOOTM) := stm32image.o
+obj-y := init.o
+obj-$(CONFIG_BOOTM) += stm32image.o
diff --git a/arch/arm/mach-stm32mp/include/mach/bootsource.h b/arch/arm/mach-stm32mp/include/mach/bootsource.h
new file mode 100644
index 000000000000..1b6f562ac301
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/bootsource.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __MACH_STM32_BOOTSOURCE_H__
+#define __MACH_STM32_BOOTSOURCE_H__
+
+enum stm32mp_boot_device {
+	STM32MP_BOOT_FLASH_SD		= 0x10, /* .. 0x13 */
+	STM32MP_BOOT_FLASH_EMMC		= 0x20, /* .. 0x23 */
+	STM32MP_BOOT_FLASH_NAND		= 0x30,
+	STM32MP_BOOT_FLASH_NAND_FMC	= 0x31,
+	STM32MP_BOOT_FLASH_NOR		= 0x40,
+	STM32MP_BOOT_FLASH_NOR_QSPI	= 0x41,
+	STM32MP_BOOT_SERIAL_UART	= 0x50, /* .. 0x58 */
+	STM32MP_BOOT_SERIAL_USB		= 0x60,
+	STM32MP_BOOT_SERIAL_USB_OTG	= 0x62,
+};
+
+enum stm32mp_forced_boot_mode {
+	STM32MP_BOOT_NORMAL	= 0x00,
+	STM32MP_BOOT_FASTBOOT	= 0x01,
+	STM32MP_BOOT_RECOVERY	= 0x02,
+	STM32MP_BOOT_STM32PROG	= 0x03,
+	STM32MP_BOOT_UMS_MMC0	= 0x10,
+	STM32MP_BOOT_UMS_MMC1	= 0x11,
+	STM32MP_BOOT_UMS_MMC2	= 0x12,
+};
+
+enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void);
+
+#endif
diff --git a/arch/arm/mach-stm32mp/include/mach/revision.h b/arch/arm/mach-stm32mp/include/mach/revision.h
new file mode 100644
index 000000000000..387201421de7
--- /dev/null
+++ b/arch/arm/mach-stm32mp/include/mach/revision.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
+/*
+ * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
+ */
+
+#ifndef __MACH_CPUTYPE_H__
+#define __MACH_CPUTYPE_H__
+
+/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0)*/
+#define CPU_STM32MP157Cxx	0x05000000
+#define CPU_STM32MP157Axx	0x05000001
+#define CPU_STM32MP153Cxx	0x05000024
+#define CPU_STM32MP153Axx	0x05000025
+#define CPU_STM32MP151Cxx	0x0500002E
+#define CPU_STM32MP151Axx	0x0500002F
+
+/* silicon revisions */
+#define CPU_REV_A	0x1000
+#define CPU_REV_B	0x2000
+
+int stm32mp_silicon_revision(void);
+int stm32mp_cputype(void);
+int stm32mp_package(void);
+
+#define cpu_is_stm32mp157c() (stm32mp_cputype() == CPU_STM32MP157Cxx)
+#define cpu_is_stm32mp157a() (stm32mp_cputype() == CPU_STM32MP157Axx)
+#define cpu_is_stm32mp153c() (stm32mp_cputype() == CPU_STM32MP153Cxx)
+#define cpu_is_stm32mp153a() (stm32mp_cputype() == CPU_STM32MP153Axx)
+#define cpu_is_stm32mp151c() (stm32mp_cputype() == CPU_STM32MP151Cxx)
+#define cpu_is_stm32mp151a() (stm32mp_cputype() == CPU_STM32MP151Axx)
+
+#endif /* __MACH_CPUTYPE_H__ */
diff --git a/arch/arm/mach-stm32mp/init.c b/arch/arm/mach-stm32mp/init.c
new file mode 100644
index 000000000000..7bad989a609b
--- /dev/null
+++ b/arch/arm/mach-stm32mp/init.c
@@ -0,0 +1,260 @@
+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
+/*
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2019 Ahmad Fatoum, Pengutronix
+ */
+
+#define pr_fmt(fmt) "stm32mp-init: " fmt
+
+#include <common.h>
+#include <init.h>
+#include <mach/stm32.h>
+#include <mach/bsec.h>
+#include <mach/revision.h>
+#include <mach/bootsource.h>
+#include <bootsource.h>
+
+/* DBGMCU register */
+#define DBGMCU_IDC		(STM32_DBGMCU_BASE + 0x00)
+#define DBGMCU_APB4FZ1		(STM32_DBGMCU_BASE + 0x2C)
+#define DBGMCU_APB4FZ1_IWDG2	BIT(2)
+#define DBGMCU_IDC_DEV_ID_MASK	GENMASK(11, 0)
+#define DBGMCU_IDC_DEV_ID_SHIFT	0
+#define DBGMCU_IDC_REV_ID_MASK	GENMASK(31, 16)
+#define DBGMCU_IDC_REV_ID_SHIFT	16
+
+#define RCC_DBGCFGR		(STM32_RCC_BASE + 0x080C)
+#define RCC_DBGCFGR_DBGCKEN	BIT(8)
+
+/* BSEC OTP index */
+#define BSEC_OTP_RPN	1
+#define BSEC_OTP_PKG	16
+
+/* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
+#define RPN_SHIFT	0
+#define RPN_MASK	GENMASK(7, 0)
+
+/* Package = bit 27:29 of OTP16
+ * - 100: LBGA448  (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
+ * - 011: LBGA354  (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
+ * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
+ * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
+ * - others: Reserved
+ */
+#define PKG_SHIFT	27
+#define PKG_MASK	GENMASK(2, 0)
+
+#define PKG_AA_LBGA448	4
+#define PKG_AB_LBGA354	3
+#define PKG_AC_TFBGA361	2
+#define PKG_AD_TFBGA257	1
+
+/*
+ * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
+ * - boot device = bit 8:4
+ * - boot instance = bit 3:0
+ */
+#define BOOT_TYPE_MASK		0xF0
+#define BOOT_TYPE_SHIFT		4
+#define BOOT_INSTANCE_MASK	0x0F
+#define BOOT_INSTANCE_SHIFT	0
+
+/* TAMP registers */
+#define TAMP_BACKUP_REGISTER(x)         (STM32_TAMP_BASE + 0x100 + 4 * x)
+/* secure access */
+#define TAMP_BACKUP_MAGIC_NUMBER        TAMP_BACKUP_REGISTER(4)
+#define TAMP_BACKUP_BRANCH_ADDRESS      TAMP_BACKUP_REGISTER(5)
+/* non secure access */
+#define TAMP_BOOT_CONTEXT               TAMP_BACKUP_REGISTER(20)
+#define TAMP_BOOTCOUNT                  TAMP_BACKUP_REGISTER(21)
+
+#define TAMP_BOOT_MODE_MASK             GENMASK(15, 8)
+#define TAMP_BOOT_MODE_SHIFT            8
+#define TAMP_BOOT_DEVICE_MASK           GENMASK(7, 4)
+#define TAMP_BOOT_INSTANCE_MASK         GENMASK(3, 0)
+#define TAMP_BOOT_FORCED_MASK           GENMASK(7, 0)
+#define TAMP_BOOT_DEBUG_ON              BIT(16)
+
+
+static enum stm32mp_forced_boot_mode __stm32mp_forced_boot_mode;
+enum stm32mp_forced_boot_mode st32mp_get_forced_boot_mode(void)
+{
+	return __stm32mp_forced_boot_mode;
+}
+
+static void setup_boot_mode(void)
+{
+	u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
+	u32 boot_mode =
+		(boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
+	int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
+	enum bootsource src = BOOTSOURCE_UNKNOWN;
+
+	switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
+	case STM32MP_BOOT_SERIAL_UART:
+		src = BOOTSOURCE_SERIAL;
+		break;
+	case STM32MP_BOOT_SERIAL_USB:
+		src = BOOTSOURCE_USB;
+		break;
+	case STM32MP_BOOT_FLASH_SD:
+	case STM32MP_BOOT_FLASH_EMMC:
+		src = BOOTSOURCE_MMC;
+		break;
+	case STM32MP_BOOT_FLASH_NAND:
+		src = BOOTSOURCE_NAND;
+		break;
+	case STM32MP_BOOT_FLASH_NOR:
+		instance = 0;
+		src = BOOTSOURCE_NOR;
+		break;
+	case STM32MP_BOOT_FLASH_NOR_QSPI:
+		instance--;
+		src = BOOTSOURCE_SPI_NOR;
+		break;
+	default:
+		pr_debug("unexpected boot mode\n");
+		break;
+	}
+
+	__stm32mp_forced_boot_mode = boot_ctx & TAMP_BOOT_FORCED_MASK;
+
+	pr_debug("[boot_ctx=0x%x] => mode=0x%x, instance=%d forced=0x%x\n",
+		 boot_ctx, boot_mode, instance, __stm32mp_forced_boot_mode);
+
+	bootsource_set(src);
+	bootsource_set_instance(instance);
+
+	/* clear TAMP for next reboot */
+	clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK,
+			STM32MP_BOOT_NORMAL);
+}
+
+static int __stm32mp_cputype;
+int stm32mp_cputype(void)
+{
+	return __stm32mp_cputype;
+}
+
+static int __stm32mp_silicon_revision;
+int stm32mp_silicon_revision(void)
+{
+	return __stm32mp_silicon_revision;
+}
+
+static int __stm32mp_package;
+int stm32mp_package(void)
+{
+	return __stm32mp_package;
+}
+
+static inline u32 read_idc(void)
+{
+	setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
+	return readl(IOMEM(DBGMCU_IDC));
+}
+
+/* Get Device Part Number (RPN) from OTP */
+static u32 get_cpu_rpn(u32 *rpn)
+{
+	int ret = bsec_read_field(BSEC_OTP_RPN, rpn);
+	if (ret)
+		return ret;
+
+	*rpn = (*rpn >> RPN_SHIFT) & RPN_MASK;
+	return 0;
+}
+
+static u32 get_cpu_revision(void)
+{
+	return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
+}
+
+static u32 get_cpu_type(u32 *type)
+{
+	u32 id;
+	int ret = get_cpu_rpn(type);
+	if (ret)
+		return ret;
+
+	id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
+	*type |= id << 16;
+	return 0;
+}
+
+static int get_cpu_package(u32 *pkg)
+{
+	int ret = bsec_read_field(BSEC_OTP_PKG, pkg);
+	if (ret)
+		return ret;
+
+	*pkg = (*pkg >> PKG_SHIFT) & PKG_MASK;
+	return 0;
+}
+
+static int setup_cpu_type(void)
+{
+	const char *cputypestr;
+	const char *cpupkgstr;
+
+	get_cpu_type(&__stm32mp_cputype);
+	switch (__stm32mp_cputype) {
+	case CPU_STM32MP157Cxx:
+		cputypestr = "157C";
+		break;
+	case CPU_STM32MP157Axx:
+		cputypestr = "157A";
+		break;
+	case CPU_STM32MP153Cxx:
+		cputypestr = "153C";
+		break;
+	case CPU_STM32MP153Axx:
+		cputypestr = "153A";
+		break;
+	case CPU_STM32MP151Cxx:
+		cputypestr = "151C";
+		break;
+	case CPU_STM32MP151Axx:
+		cputypestr = "151A";
+		break;
+	default:
+		cputypestr = "????";
+		break;
+	}
+
+	get_cpu_package(&__stm32mp_package );
+	switch (__stm32mp_package) {
+	case PKG_AA_LBGA448:
+		cpupkgstr = "AA";
+		break;
+	case PKG_AB_LBGA354:
+		cpupkgstr = "AB";
+		break;
+	case PKG_AC_TFBGA361:
+		cpupkgstr = "AC";
+		break;
+	case PKG_AD_TFBGA257:
+		cpupkgstr = "AD";
+		break;
+	default:
+		cpupkgstr = "??";
+		break;
+	}
+
+	__stm32mp_silicon_revision = get_cpu_revision();
+
+	pr_debug("cputype = 0x%x, package = 0x%x, revision = 0x%x\n",
+		 __stm32mp_cputype, __stm32mp_package, __stm32mp_silicon_revision);
+	pr_info("detected STM32MP%s%s Rev.%c\n", cputypestr, cpupkgstr,
+		(__stm32mp_silicon_revision >> 12) + 'A' - 1);
+	return 0;
+}
+
+static int stm32mp_init(void)
+{
+	setup_cpu_type();
+	setup_boot_mode();
+
+	return 0;
+}
+postcore_initcall(stm32mp_init);
-- 
2.23.0


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Re: [PATCH v2 7/8] ARM: stm32mp: dk2: add barebox SD-Card update handler

[Sascha Hauer]

On Mon, Oct 28, 2019 at 12:18:31AM +0100, Ahmad Fatoum wrote:
> Now with the SD/MMC controller supported, lets add a bbu handler, so we
> can use it to update the second stage boot loader partition.
> 
> While doing this, I noticed that making use of the bus-width = <4>
> property in the device tree now makes mmc usage fail when reading the
> environment:
> 
>   ERROR: error SDMMC_STA_DCRCFAIL (0x81042) for cmd 18
>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
>   WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
>   WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
>   WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12

Could you make this an extra patch?

> 
> We'll want to fix this eventually, but for now force the bus width to 1
> and print a notice to the console that we've done so. This is not
> enough, however because it then fails at loading the kernel from MMC:
> 
>   ERROR: Time out on waiting for SDMMC_STA. cmd 18
>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x804) for cmd 12
>   WARNING: stm32_sdmmc2_send_cmd: cmd 18 failed, retrying ...
> 
> Fixing the max frequency at 208 MHz fixes this. So do that and print a
> notice for it as well.
> 
> @@ -627,11 +627,22 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
>  	if (IS_ERR(priv->reset_ctl))
>  		priv->reset_ctl = NULL;
>  
> +	mci_of_parse(&priv->mci);
> +
>  	mci->f_min = 400000;
> -	/* f_max is taken from kernel v5.3 variant_stm32_sdmmc */
> -	mci->f_max = 208000000;
>  	mci->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
>  
> +	if (mci->f_max != 208000000) {
> +		/* f_max is taken from kernel v5.3 variant_stm32_sdmmc */
> +		dev_notice(dev, "Fixing max-frequency to 208 MHz due to driver limitation\n");
> +		mci->f_max = 208000000;
> +	}

f_max previously was hardcoded to 208MHz. It still is now, so this can't
fix anything.
Looking at the device tree we have max-frequency = <120000000>, so you
probably mean that it doesn't work with the 120MHz specified here,
right? If it doesn't work with a lower frequency it really looks fishy.

Could you have another look what is going on here?

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH v2 1/8] pinctrl: stm32: fix debug print of uninitialized variable

[Sascha Hauer]

On Mon, Oct 28, 2019 at 12:18:25AM +0100, Ahmad Fatoum wrote:
> mode and alt are printed with the dev_dbg before they are initialized.
> Remedy this by moving the dev_dbg after them.
> 
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
>  drivers/pinctrl/pinctrl-stm32.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)

Applied all except 7/8, thanks

Sascha


-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH v2 7/8] ARM: stm32mp: dk2: add barebox SD-Card update handler

[Ahmad Fatoum]

On 10/28/19 12:31 PM, Sascha Hauer wrote:
> On Mon, Oct 28, 2019 at 12:18:31AM +0100, Ahmad Fatoum wrote:
>> Now with the SD/MMC controller supported, lets add a bbu handler, so we
>> can use it to update the second stage boot loader partition.
>>
>> While doing this, I noticed that making use of the bus-width = <4>
>> property in the device tree now makes mmc usage fail when reading the
>> environment:
>>
>>   ERROR: error SDMMC_STA_DCRCFAIL (0x81042) for cmd 18
>>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
>>   WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
>>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
>>   WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
>>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
>>   WARNING: stm32_sdmmc2_send_cmd: cmd 12 failed, retrying ...
>>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x4) for cmd 12
> 
> Could you make this an extra patch?

Can do.

> 
>>
>> We'll want to fix this eventually, but for now force the bus width to 1
>> and print a notice to the console that we've done so. This is not
>> enough, however because it then fails at loading the kernel from MMC:
>>
>>   ERROR: Time out on waiting for SDMMC_STA. cmd 18
>>   ERROR: stm32_sdmmc2_end_cmd: error SDMMC_STA_CTIMEOUT (0x804) for cmd 12
>>   WARNING: stm32_sdmmc2_send_cmd: cmd 18 failed, retrying ...
>>
>> Fixing the max frequency at 208 MHz fixes this. So do that and print a
>> notice for it as well.
>>
>> @@ -627,11 +627,22 @@ static int stm32_sdmmc2_probe(struct amba_device *adev,
>>  	if (IS_ERR(priv->reset_ctl))
>>  		priv->reset_ctl = NULL;
>>  
>> +	mci_of_parse(&priv->mci);
>> +
>>  	mci->f_min = 400000;
>> -	/* f_max is taken from kernel v5.3 variant_stm32_sdmmc */
>> -	mci->f_max = 208000000;
>>  	mci->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
>>  
>> +	if (mci->f_max != 208000000) {
>> +		/* f_max is taken from kernel v5.3 variant_stm32_sdmmc */
>> +		dev_notice(dev, "Fixing max-frequency to 208 MHz due to driver limitation\n");
>> +		mci->f_max = 208000000;
>> +	}
> 
> f_max previously was hardcoded to 208MHz. It still is now, so this can't
> fix anything.
> Looking at the device tree we have max-frequency = <120000000>, so you
> probably mean that it doesn't work with the 120MHz specified here,
> right? If it doesn't work with a lower frequency it really looks fishy.

Exactly.

> 
> Could you have another look what is going on here?

I intend to, but not sure if it'll be before the cut-off for v2019.12.0.
I'd like for that release to have full STM32MP support.

I'll send a v2. 

> 
> Sascha
> 
> 

-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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