* [PATCH] serial: cadence: fix serial_flush
@ 2019-11-01 19:54 Lucas Stach
2019-11-04 8:58 ` Sascha Hauer
0 siblings, 1 reply; 2+ messages in thread
From: Lucas Stach @ 2019-11-01 19:54 UTC (permalink / raw)
To: barebox
The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so
flushing must wait until the bit is set instead of being unset.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
---
drivers/serial/serial_cadence.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/serial/serial_cadence.c b/drivers/serial/serial_cadence.c
index 0501c400b129..6454888e3c5b 100644
--- a/drivers/serial/serial_cadence.c
+++ b/drivers/serial/serial_cadence.c
@@ -199,7 +199,7 @@ static void cadence_serial_flush(struct console_device *cdev)
struct cadence_serial_priv, cdev);
while ((readl(priv->regs + CADENCE_UART_CHANNEL_STS) &
- CADENCE_STS_TEMPTY) != 0)
+ CADENCE_STS_TEMPTY) == 0)
;
}
--
2.23.0
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* Re: [PATCH] serial: cadence: fix serial_flush
2019-11-01 19:54 [PATCH] serial: cadence: fix serial_flush Lucas Stach
@ 2019-11-04 8:58 ` Sascha Hauer
0 siblings, 0 replies; 2+ messages in thread
From: Sascha Hauer @ 2019-11-04 8:58 UTC (permalink / raw)
To: Lucas Stach; +Cc: barebox
On Fri, Nov 01, 2019 at 08:54:29PM +0100, Lucas Stach wrote:
> The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so
> flushing must wait until the bit is set instead of being unset.
>
> Signed-off-by: Lucas Stach <dev@lynxeye.de>
> ---
> drivers/serial/serial_cadence.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks
Sascha
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