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From: Sascha Hauer <s.hauer@pengutronix.de>
To: Barebox List <barebox@lists.infradead.org>
Subject: [PATCH 02/12] PCI: dwc: Make use of IS_ALIGNED()
Date: Wed, 27 Nov 2019 12:20:41 +0100	[thread overview]
Message-ID: <20191127112051.9427-3-s.hauer@pengutronix.de> (raw)
In-Reply-To: <20191127112051.9427-1-s.hauer@pengutronix.de>

Port of Linux commit 4f8bbd2f8e7c4f3112506bf7362aed3a5495d51b

    Make the intent a bit more clear as well as get rid of explicit
    arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to
    "size". No functional change intended.

    Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
    Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Acked-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
    Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
    Cc: Bjorn Helgaas <bhelgaas@google.com>
    Cc: Fabio Estevam <fabio.estevam@nxp.com>
    Cc: Chris Healy <cphealy@gmail.com>
    Cc: Lucas Stach <l.stach@pengutronix.de>
    Cc: Leonard Crestez <leonard.crestez@nxp.com>
    Cc: "A.s. Dong" <aisheng.dong@nxp.com>
    Cc: Richard Zhu <hongxing.zhu@nxp.com>
    Cc: linux-imx@nxp.com
    Cc: linux-arm-kernel@lists.infradead.org
    Cc: linux-kernel@vger.kernel.org
    Cc: linux-pci@vger.kernel.org

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/pci/pcie-designware.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/pcie-designware.c b/drivers/pci/pcie-designware.c
index 4fe99b1ffb..5747704cd5 100644
--- a/drivers/pci/pcie-designware.c
+++ b/drivers/pci/pcie-designware.c
@@ -29,7 +29,7 @@
 
 int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 {
-	if ((uintptr_t)addr & (size - 1)) {
+	if (!IS_ALIGNED((uintptr_t)addr, size)) {
 		*val = 0;
 		return PCIBIOS_BAD_REGISTER_NUMBER;
 	}
@@ -50,7 +50,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val)
 
 int dw_pcie_write(void __iomem *addr, int size, u32 val)
 {
-	if ((uintptr_t)addr & (size - 1))
+	if (!IS_ALIGNED((uintptr_t)addr, size))
 		return PCIBIOS_BAD_REGISTER_NUMBER;
 
 	if (size == 4)
-- 
2.24.0


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  parent reply	other threads:[~2019-11-27 11:20 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-27 11:20 [PATCH 00/12] Designware PCIe updates and Layerscape support Sascha Hauer
2019-11-27 11:20 ` [PATCH 01/12] PCI: dwc: Don't hard-code DBI/ATU offset Sascha Hauer
2019-11-27 11:20 ` Sascha Hauer [this message]
2019-11-27 11:20 ` [PATCH 03/12] PCI: dwc: Add dw_pcie_disable_atu() Sascha Hauer
2019-11-27 11:20 ` [PATCH 04/12] PCI: dwc: Make use of BIT() in constant definitions Sascha Hauer
2019-11-27 11:20 ` [PATCH 05/12] PCI: dwc: Enable iATU unroll for endpoint too Sascha Hauer
2019-11-27 11:20 ` [PATCH 06/12] PCI: dwc: Fix ATU identification for designware version >= 4.80 Sascha Hauer
2019-11-27 11:20 ` [PATCH 07/12] PCI: dwc: imx6: Share PHY debug register definitions Sascha Hauer
2019-11-27 11:20 ` [PATCH 08/12] PCI: dwc: Cleanup DBI,ATU read and write APIs Sascha Hauer
2019-11-27 11:20 ` [PATCH 09/12] PCI: dwc: rename readl/writel_dbi ops to read/write_dbi Sascha Hauer
2019-11-27 11:20 ` [PATCH 10/12] PCI: dwc: Sync register definitions with Linux-5.4 Sascha Hauer
2019-11-27 11:20 ` [PATCH 11/12] PCI: dwc: Return directly when num-lanes is not found Sascha Hauer
2019-11-27 11:20 ` [PATCH 12/12] PCI: Add layerscape PCIe driver Sascha Hauer

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