[PATCH 0/6] Layerscape ls1046ardb update

[PATCH 0/6] Layerscape ls1046ardb update

[Sascha Hauer]

Some updates for the Layerscape ls1046ardb board.

Sascha Hauer (6):
  ARM Layerscape: ls1046ardb: Fix SD partitions
  ARM Layerscape: ls1046ardb: Add barebox update handler
  ARM Layerscape: ls1046ardb: Fix SPI NOR flash compatibles
  ARM Layerscape: ls1046ardb: Enable PCIe support
  ARM Layerscape: ls1046ardb: Fix EEPROM nodes
  ARM Layerscape: ls1046ardb: read nxid eeprom

 arch/arm/boards/ls1046ardb/board.c | 107 +++++++++++++++++++++++++++++
 arch/arm/dts/fsl-ls1046a-rdb.dts   |  46 ++++++++++++-
 2 files changed, 151 insertions(+), 2 deletions(-)

-- 
2.24.0


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[PATCH 1/6] ARM Layerscape: ls1046ardb: Fix SD partitions

[Sascha Hauer]

barebox and its environment should be in the first MiB of the SD card.
With this we won't overwrite any partitions from the partition table.
While at it add a barebox partition for a future update handler.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/fsl-ls1046a-rdb.dts | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 842d684588..9a2794c910 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -23,9 +23,14 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
-	environment_sd: partition@200000 {
+	partition@1000 {
+		label = "barebox";
+		reg = <0x1000 0xdf000>;
+	};
+
+	environment_sd: partition@e0000 {
 		label = "barebox-environment";
-		reg = <0x200000 0x20000>;
+		reg = <0xe0000 0x20000>;
 	};
 };
 
-- 
2.24.0


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[PATCH 2/6] ARM Layerscape: ls1046ardb: Add barebox update handler

[Sascha Hauer]

Add a barebox update handler for easy barebox update.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/ls1046ardb/board.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
index 0846df9fad..606f65ce9d 100644
--- a/arch/arm/boards/ls1046ardb/board.c
+++ b/arch/arm/boards/ls1046ardb/board.c
@@ -2,6 +2,7 @@
 
 #include <common.h>
 #include <init.h>
+#include <bbu.h>
 #include <envfs.h>
 #include <asm/memory.h>
 #include <linux/sizes.h>
@@ -9,6 +10,7 @@
 #include <linux/clkdev.h>
 #include <asm/system.h>
 #include <mach/layerscape.h>
+#include <mach/bbu.h>
 
 static int rdb_mem_init(void)
 {
@@ -35,6 +37,9 @@ static int rdb_postcore_init(void)
 
 	defaultenv_append_directory(defaultenv_ls1046ardb);
 
+	ls1046a_bbu_mmc_register_handler("sd", "/dev/mmc0.barebox",
+					 BBU_HANDLER_FLAG_DEFAULT);
+
 	return 0;
 }
 
-- 
2.24.0


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[PATCH 3/6] ARM Layerscape: ls1046ardb: Fix SPI NOR flash compatibles

[Sascha Hauer]

The upstream dts file has a "spansion,m25p80" as compatible string
for the SPI NOR flashes. This doesn't match the real chip which
identifies itself as "s25fl512s". The driver warns about this. Change
the compatible to "jedec,spi-nor" to avoid such issues.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/fsl-ls1046a-rdb.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 9a2794c910..3586e08b04 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -114,6 +114,14 @@
 	};
 };
 
+&qflash0 {
+	compatible = "jedec,spi-nor";
+};
+
+&qflash1 {
+	compatible = "jedec,spi-nor";
+};
+
 &usb0 {
 	dr_mode = "host";
 };
-- 
2.24.0


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[PATCH 4/6] ARM Layerscape: ls1046ardb: Enable PCIe support

[Sascha Hauer]

Enable the PCIe nodes on the ls1046ardb board. U-Boot registers the PCIe
devices based on the SERDES configuration, but for us it's easier to
just enable them in the device tree.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/fsl-ls1046a-rdb.dts | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index 3586e08b04..ee4ddf0f2c 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -135,3 +135,17 @@
 &usb2 {
 	dr_mode = "host";
 };
+
+&soc {
+	pcie1: pcie@3400000 {
+		status = "okay";
+	};
+
+	pcie2: pcie@3500000 {
+		status = "okay";
+	};
+
+	pcie3: pcie@3600000 {
+		status = "okay";
+	};
+};
-- 
2.24.0


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[PATCH 5/6] ARM Layerscape: ls1046ardb: Fix EEPROM nodes

[Sascha Hauer]

The ls1046ardb only has one EEPROM instead of two and this is a 24c04
(which spans two addresses on the I2C bus) and not a 24c512.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/dts/fsl-ls1046a-rdb.dts | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1046a-rdb.dts b/arch/arm/dts/fsl-ls1046a-rdb.dts
index ee4ddf0f2c..32b3f40769 100644
--- a/arch/arm/dts/fsl-ls1046a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1046a-rdb.dts
@@ -5,6 +5,10 @@
 #include <arm64/freescale/fsl-ls1046a-rdb.dts>
 
 / {
+	aliases {
+		eeprom = &eeprom;
+	};
+
 	chosen {
 		stdout-path = &duart0;
 
@@ -46,6 +50,17 @@
 	status = "okay";
 };
 
+&i2c0 {
+	eeprom: eeprom@52 {
+		compatible = "atmel,24c04";
+	};
+
+	non_existent_eeprom: eeprom@53 {
+	};
+};
+
+/delete-node/ &non_existent_eeprom;
+
 &fman0 {
 	ethernet@e0000 {
 		status = "disabled";
-- 
2.24.0


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[PATCH 6/6] ARM Layerscape: ls1046ardb: read nxid eeprom

[Sascha Hauer]

This adds support for reading the EEPROM which has a "NXID" data
structure on it. The MAC addresses for the ethernet devices are
found here which are registered with this patch.

The NXID data structure is also found on other NXP Layerscape boards,
so once we support other boards the code should be moved somewhere
where it can be shared between boards.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/boards/ls1046ardb/board.c | 102 +++++++++++++++++++++++++++++
 1 file changed, 102 insertions(+)

diff --git a/arch/arm/boards/ls1046ardb/board.c b/arch/arm/boards/ls1046ardb/board.c
index 606f65ce9d..d744737773 100644
--- a/arch/arm/boards/ls1046ardb/board.c
+++ b/arch/arm/boards/ls1046ardb/board.c
@@ -3,7 +3,11 @@
 #include <common.h>
 #include <init.h>
 #include <bbu.h>
+#include <net.h>
+#include <crc.h>
+#include <fs.h>
 #include <envfs.h>
+#include <libfile.h>
 #include <asm/memory.h>
 #include <linux/sizes.h>
 #include <linux/clk.h>
@@ -12,6 +16,104 @@
 #include <mach/layerscape.h>
 #include <mach/bbu.h>
 
+#define MAX_NUM_PORTS 16
+struct nxid {
+	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
+	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
+	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
+	u8 date[6];       /* 0x15 - 0x1a Build Date */
+	u8 res_0;         /* 0x1b        Reserved */
+	u32 version;      /* 0x1c - 0x1f NXID Version */
+	u8 tempcal[8];    /* 0x20 - 0x27 Temperature Calibration Factors */
+	u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
+	u8 tempcalflags;  /* 0x2a        Temperature Calibration Flags */
+	u8 res_1[21];     /* 0x2b - 0x3f Reserved */
+	u8 mac_count;     /* 0x40        Number of MAC addresses */
+	u8 mac_flag;      /* 0x41        MAC table flags */
+	u8 mac[MAX_NUM_PORTS][6];     /* 0x42 - 0xa1 MAC addresses */
+	u8 res_2[90];     /* 0xa2 - 0xfb Reserved */	
+	u32 crc;          /* 0xfc - 0xff CRC32 checksum */
+} __packed;
+
+static int nxid_is_valid(struct nxid *nxid)
+{
+	unsigned char id[] = { 'N', 'X', 'I', 'D' };
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(id); i++)
+		if (nxid->id[i] != id[i])
+			return false;
+	return true;
+}
+
+static struct nxid *nxp_nxid_read(const char *filename, unsigned int offset)
+{
+	struct nxid *nxid;
+	int fd, ret, i;
+	struct device_node *root;
+	u32 crc, crc_expected;
+
+	nxid = xzalloc(sizeof(*nxid));
+
+	fd = open(filename, O_RDONLY);
+	if (fd < 0) {
+		ret = -errno;
+		goto out;
+	}
+
+	ret = pread(fd, nxid, sizeof(*nxid), offset);
+	if (ret < 0) {
+		close(fd);
+		goto out;
+	}
+
+	if (!nxid_is_valid(nxid)) {
+		ret = -ENODEV;
+		goto out;
+	}
+
+	crc = crc32(0, nxid, 256 - 4);
+	crc_expected = be32_to_cpu(nxid->crc);
+	if (crc != crc_expected) {
+		pr_err("CRC mismatch (%08x != %08x)\n", crc, crc_expected);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	root = of_get_root_node();
+
+	for (i = 0; i < nxid->mac_count; i++) {
+		struct device_node *np;
+		char alias[sizeof("ethernetxxx")];
+		const char *ethaddr = nxid->mac[i];
+
+		sprintf(alias, "ethernet%d", i);
+
+		np = of_find_node_by_alias(root, alias);
+		if (!np)
+			continue;
+		
+		of_eth_register_ethaddr(np, ethaddr);
+	}
+
+	ret = 0;
+out:
+	if (ret) {
+		free(nxid);
+		nxid = ERR_PTR(ret);
+	}
+
+	return nxid;
+}
+
+static int rdb_late_init(void)
+{
+	nxp_nxid_read("/dev/eeprom", 256);
+
+	return 0;
+}
+late_initcall(rdb_late_init);
+
 static int rdb_mem_init(void)
 {
 	int ret;
-- 
2.24.0


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