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From: Lucas Stach <l.stach@pengutronix.de>
To: barebox@lists.infradead.org
Subject: [PATCH] ARM: imx6: properly check for IPU presence
Date: Fri, 24 Jan 2020 18:46:48 +0100	[thread overview]
Message-ID: <20200124174648.31650-1-l.stach@pengutronix.de> (raw)

Since a73850bd76d0 (ARM: imx: disable IPU QoS setup for correct SoCs), which
fixed the condition to not execute the IPU QoS fixups on SoCs that don't have
a IPU, the fixups aren't applied on i.MX6Q/DP anymore, since those SoCs were
missing from the whitelist.

Add a function to make it a bit more clearer what we are checking here and add
the Q/DP SoCs.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 41e0066add09..e1c821456878 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -114,14 +114,23 @@ static void imx6_init_lowlevel(void)
 	}
 }
 
+static bool imx6_has_ipu(void)
+{
+	if (cpu_mx6_is_mx6qp() || cpu_mx6_is_mx6dp() ||
+	    cpu_mx6_is_mx6q() || cpu_mx6_is_mx6d() ||
+	    cpu_mx6_is_mx6dl() || cpu_mx6_is_mx6s())
+		return true;
+
+	return false;
+}
+
 static void imx6_setup_ipu_qos(void)
 {
 	void __iomem *iomux = (void *)MX6_IOMUXC_BASE_ADDR;
 	void __iomem *fast2 = (void *)MX6_FAST2_BASE_ADDR;
 	uint32_t val;
 
-	if (!cpu_mx6_is_mx6q() && !cpu_mx6_is_mx6d() &&
-	    !cpu_mx6_is_mx6dl() && !cpu_mx6_is_mx6s())
+	if (!imx6_has_ipu())
 		return;
 
 	val = readl(iomux + IOMUXC_GPR4);
-- 
2.20.1


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             reply	other threads:[~2020-01-24 17:46 UTC|newest]

Thread overview: 2+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-24 17:46 Lucas Stach [this message]
2020-01-27 13:01 ` Sascha Hauer

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