Re: [PATCH 3/3] arm64: Set PXN/UXN attributes for uncached mem

[Sascha Hauer <s.hauer@pengutronix.de>]

On Tue, Mar 31, 2020 at 11:01:35AM +0200, Sascha Hauer wrote:
> On Tue, Mar 31, 2020 at 10:33:54AM +0200, Ahmad Fatoum wrote:
> > 
> > 
> > On 3/31/20 10:01 AM, Sascha Hauer wrote:
> > > The attributes should be set to avoid speculative access to memory-mapped
> > > peripherals.
> > > 
> > > The patch has been tested with:
> > > 
> > > noinline unsigned long nox(void)
> > > {
> > > 	return get_pc();
> > > }
> > > 
> > > static void xn_test(void)
> > > {
> > > 	void *adr = (void *)SOME_SRAM_ADDRESS;
> > > 	unsigned long ret;
> > > 	unsigned long (*fn)(void) = adr;
> > > 
> > > 	memcpy(adr, nox, 0x1000);
> > > 
> > > 	sync_caches_for_execution();
> > > 
> > > 	ret = fn();
> > > 	printf("pc: 0x%08lx\n", ret);
> > > }
> > > 
> > > Without this patch nox() gets executed in SRAM, with it runs into a
> > > abort as expected.
> > > 
> > > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > > ---
> > >  arch/arm/cpu/mmu_64.h | 3 ++-
> > >  1 file changed, 2 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/arch/arm/cpu/mmu_64.h b/arch/arm/cpu/mmu_64.h
> > > index a2a5477569..f5b7624037 100644
> > > --- a/arch/arm/cpu/mmu_64.h
> > > +++ b/arch/arm/cpu/mmu_64.h
> > > @@ -6,7 +6,8 @@
> > >  			 PTE_BLOCK_AF)
> > >  #define UNCACHED_MEM    (PTE_BLOCK_MEMTYPE(MT_DEVICE_nGnRnE) | \
> > >  			 PTE_BLOCK_OUTER_SHARE | \
> > > -			 PTE_BLOCK_AF)
> > > +			 PTE_BLOCK_AF | \
> > > +			 PTE_BLOCK_UXN)
> > 
> > Don't we need PXN in EL1?
> 
> We are not in EL1 currently. What happens if we change the exception
> level after the MMU setup? In that case we would have to adjust the
> attributes of the existing page tables when doing so. We are currently
> not prepared for that so I am not sure how much sense it makes to test
> for the EL here.

Hm, this is no reason for not honoring the current EL in the first
place, I'll update the patch accordingly.

Sascha


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