From: Sascha Hauer <s.hauer@pengutronix.de>
To: Michael Graichen <michael.graichen@hotmail.com>
Cc: "barebox@lists.infradead.org" <barebox@lists.infradead.org>
Subject: Re: [PATCH 7/7] Zedboard added Zynq FPGA manager
Date: Fri, 3 Apr 2020 13:11:09 +0200 [thread overview]
Message-ID: <20200403111109.GT27288@pengutronix.de> (raw)
In-Reply-To: <DB7PR02MB4332AE69BFFEF787322B8DB2ABC60@DB7PR02MB4332.eurprd02.prod.outlook.com>
Hi Michael,
On Thu, Apr 02, 2020 at 08:23:56AM +0000, Michael Graichen wrote:
> This adds support to programm the PL part of the Zynq SoC,
> but only the non-secure way and no partial reconfiguration.
> It adds the 'zynq_fpga_manager' so we can use
>
> firmwareload -l
> firmwareload -t zynq-fpga-manager /mnt/mmc0.0/design_1_wrapper.bit
>
> to programm the PL.
...
>
> + start = get_time_ns();
> + while (1) {
> + reg = readl(mgr->regs + STATUS_OFFSET);
> +
> + if(!(reg & STATUS_PCFG_INIT_MASK))
> + break;
> +
> + if (is_timeout(start, 100 * MSECOND))
> + return -ETIMEDOUT;
> + }
You can use readl_poll_timeout() as a shortcut to such
register-poll-timeout loops.
The code looks good to me, but the patches need some coding style polish
before I can apply them. There are a lot of trailing whitespaces.
Indentation should be done with tabs, tab width is 8 chars.
Also the patches lack a "Signed-off-by:" line
Regards,
Sascha
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prev parent reply other threads:[~2020-04-03 11:11 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-02 8:23 Michael Graichen
2020-04-03 11:11 ` Sascha Hauer [this message]
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