* [PATCH 00/21] clk: at91: sync with Linux v5.6
@ 2020-04-13 7:51 Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle Ahmad Fatoum
` (21 more replies)
0 siblings, 22 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
During a bug hunt that ultimately turned out unrelated to the state
of the barebox at91 clk driver, I synchronized its state with Linux v5.6.
This imports it, after cleanup. It refactors other code a bit to reduce
the diff for the final port and future ones. What we gain from this:
- bug fixes that have been posted upstream in the meanwhile
- sam9x60 (new Microchip ARM926EJ-S) clock support
- sama5d2 audio PLL
- Some more helpers to make code porting slightly easier
- SPDX-License-Identifiers, not only for at91 clks, but for all of
drivers/clk
Cheers,
Ahmad Fatoum (17):
mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle
mfd: syscon: refactor of_syscon_register compatible check
mfd: syscon: implement device_node_to_regmap
regmap: retire of_node_to_regmap in favor of device_node_to_regmap
ARM: include: remove unused <asm/processor.h>
treewide: use cpu_relax() where appropriate
of: port Linux of_get_compatible_child helper
clk: implement clk_register_fixed_rate
clk: add clk_unregister stub
include: linux/kernel.h: port DIV_ROUND_CLOSEST_ULL definition
clk: migrate to SPDX-License-Identifier use
clk: at91: delete no-longer required DT compat code
clk: at91: compile dt-compat for all platforms that require it
clk: at91: add __init marker where appropriate
clk: at91: add sama5d2 audio PLL support
clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock support
clk: at91: sckc: fix off-by-1000 in udelay()
Alexandre Belloni (2):
clk: at91: fix masterck name
clk: at91: fix possible deadlock
Eugen Hristev (1):
clk: at91: allow 24 Mhz clock as input for PLL
Stephen Boyd (1):
clk: at91: Mark struct clk_range as const
arch/arm/include/asm/processor.h | 131 ------
arch/arm/mach-at91/Kconfig | 19 +
arch/arm/mach-omap/omap4_rom_usb.c | 6 +-
drivers/base/regmap/regmap-mmio.c | 5 +-
drivers/base/regmap/regmap.c | 20 -
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/at91/Makefile | 15 +-
drivers/clk/at91/at91sam9260.c | 16 +-
drivers/clk/at91/at91sam9rl.c | 4 +-
drivers/clk/at91/at91sam9x5.c | 18 +-
drivers/clk/at91/clk-audio-pll.c | 512 ++++++++++++++++++++++++
drivers/clk/at91/clk-generated.c | 68 ++--
drivers/clk/at91/clk-h32mx.c | 9 +-
drivers/clk/at91/clk-i2s-mux.c | 87 ++++
drivers/clk/at91/clk-main.c | 25 +-
drivers/clk/at91/clk-master.c | 16 +-
drivers/clk/at91/clk-peripheral.c | 54 +--
drivers/clk/at91/clk-pll.c | 21 +-
drivers/clk/at91/clk-plldiv.c | 9 +-
drivers/clk/at91/clk-programmable.c | 53 ++-
drivers/clk/at91/clk-sam9x60-pll.c | 322 +++++++++++++++
drivers/clk/at91/clk-slow.c | 7 +-
drivers/clk/at91/clk-smd.c | 9 +-
drivers/clk/at91/clk-system.c | 9 +-
drivers/clk/at91/clk-usb.c | 44 +-
drivers/clk/at91/clk-utmi.c | 7 +-
drivers/clk/at91/dt-compat.c | 140 +------
drivers/clk/at91/pmc.c | 19 +-
drivers/clk/at91/pmc.h | 91 +++--
drivers/clk/at91/sam9x60.c | 313 +++++++++++++++
drivers/clk/at91/sama5d2.c | 79 +++-
drivers/clk/at91/sama5d4.c | 14 +-
drivers/clk/at91/sckc.c | 387 +++++++++++-------
drivers/clk/clk-ar933x.c | 13 +-
drivers/clk/clk-ar9344.c | 10 +-
drivers/clk/clk-composite.c | 13 +-
drivers/clk/clk-conf.c | 5 +-
drivers/clk/clk-divider.c | 12 +-
drivers/clk/clk-fixed-factor.c | 12 +-
drivers/clk/clk-fixed.c | 28 +-
drivers/clk/clk-fractional-divider.c | 5 +-
drivers/clk/clk-gate-shared.c | 12 +-
drivers/clk/clk-gate.c | 12 +-
drivers/clk/clk-gpio.c | 12 +-
drivers/clk/clk-mux.c | 12 +-
drivers/clk/clk-qoric.c | 5 +-
drivers/clk/clk.c | 12 +-
drivers/clk/clkdev.c | 5 +-
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-cpu.c | 8 +-
drivers/clk/imx/clk-frac-pll.c | 8 +-
drivers/clk/imx/clk-gate-exclusive.c | 5 +-
drivers/clk/imx/clk-gate2.c | 12 +-
drivers/clk/imx/clk-imx1.c | 14 +-
drivers/clk/imx/clk-imx21.c | 15 +-
drivers/clk/imx/clk-imx25.c | 15 +-
drivers/clk/imx/clk-imx27.c | 1 +
drivers/clk/imx/clk-imx31.c | 14 +-
drivers/clk/imx/clk-imx35.c | 6 +-
drivers/clk/imx/clk-imx5.c | 6 +-
drivers/clk/imx/clk-imx6.c | 8 +-
drivers/clk/imx/clk-imx6sl.c | 8 +-
drivers/clk/imx/clk-imx6sx.c | 8 +-
drivers/clk/imx/clk-imx6ul.c | 8 +-
drivers/clk/imx/clk-imx7.c | 10 +-
drivers/clk/imx/clk-pfd.c | 8 +-
drivers/clk/imx/clk-pllv1.c | 14 +-
drivers/clk/imx/clk-pllv2.c | 14 +-
drivers/clk/imx/clk-pllv3.c | 14 +-
drivers/clk/imx/clk-sccg-pll.c | 8 +-
drivers/clk/imx/clk-vf610.c | 7 +-
drivers/clk/imx/clk.c | 1 +
drivers/clk/imx/clk.h | 1 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-370.c | 5 +-
drivers/clk/mvebu/armada-38x.c | 5 +-
drivers/clk/mvebu/armada-xp.c | 5 +-
drivers/clk/mvebu/common.c | 5 +-
drivers/clk/mvebu/common.h | 5 +-
drivers/clk/mvebu/corediv.c | 5 +-
drivers/clk/mvebu/dove.c | 5 +-
drivers/clk/mvebu/kirkwood.c | 5 +-
drivers/clk/mxs/Makefile | 1 +
drivers/clk/mxs/clk-div.c | 8 +-
drivers/clk/mxs/clk-frac.c | 8 +-
drivers/clk/mxs/clk-imx23.c | 14 +-
drivers/clk/mxs/clk-imx28.c | 14 +-
drivers/clk/mxs/clk-lcdif.c | 1 +
drivers/clk/mxs/clk-pll.c | 8 +-
drivers/clk/mxs/clk-ref.c | 8 +-
drivers/clk/mxs/clk.h | 1 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-cpu.c | 5 +-
drivers/clk/rockchip/clk-pll.c | 11 +-
drivers/clk/rockchip/clk-rk3188.c | 11 +-
drivers/clk/rockchip/clk-rk3288.c | 11 +-
drivers/clk/rockchip/clk.c | 11 +-
drivers/clk/rockchip/clk.h | 11 +-
drivers/clk/socfpga/Makefile | 1 +
drivers/clk/socfpga/clk-gate-a10.c | 13 +-
drivers/clk/socfpga/clk-periph-a10.c | 13 +-
drivers/clk/socfpga/clk-pll-a10.c | 13 +-
drivers/clk/socfpga/clk.c | 10 +-
drivers/clk/socfpga/clk.h | 11 +-
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-divider.c | 13 +-
drivers/clk/tegra/clk-periph.c | 13 +-
drivers/clk/tegra/clk-pll-out.c | 13 +-
drivers/clk/tegra/clk-pll.c | 13 +-
drivers/clk/tegra/clk-tegra124.c | 13 +-
drivers/clk/tegra/clk-tegra20.c | 13 +-
drivers/clk/tegra/clk-tegra30.c | 13 +-
drivers/clk/tegra/clk.c | 13 +-
drivers/clk/tegra/clk.h | 13 +-
drivers/clk/vexpress/Makefile | 1 +
drivers/clk/vexpress/clk-sp810.c | 10 +-
drivers/clk/vexpress/clk-vexpress-osc.c | 11 +-
drivers/clk/zynq/Makefile | 1 +
drivers/clk/zynq/clkc.c | 13 +-
drivers/clk/zynqmp/Makefile | 1 +
drivers/mfd/syscon.c | 36 +-
drivers/mtd/nand/nand_denali.c | 8 +-
drivers/of/base.c | 25 ++
include/linux/barebox-wrapper.h | 2 +
include/linux/clk.h | 13 +-
include/linux/clk/at91_pmc.h | 59 ++-
include/linux/kernel.h | 13 +
include/mfd/syscon.h | 5 +
include/of.h | 8 +
include/regmap.h | 3 +-
131 files changed, 2110 insertions(+), 1356 deletions(-)
delete mode 100644 arch/arm/include/asm/processor.h
create mode 100644 drivers/clk/at91/clk-audio-pll.c
create mode 100644 drivers/clk/at91/clk-i2s-mux.c
create mode 100644 drivers/clk/at91/clk-sam9x60-pll.c
create mode 100644 drivers/clk/at91/sam9x60.c
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-15 9:15 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 02/21] mfd: syscon: refactor of_syscon_register compatible check Ahmad Fatoum
` (20 subsequent siblings)
21 siblings, 1 reply; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Since commit b36b7b72 ("mfd: syscon: clock peripheral if specified in
device tree"), we now clock syscons during access if the device tree nodes
indicate a clocks property. We haven't been doing this for
syscon_base_lookup_by_phandle though, because we did this as part of the
regmap access functions.
The best way forward is probably dropping the syscon_base API altogether
and change users to the regmap API instead, but for now, make the behavior
consistent, by detaching the clock and enabling it permanently, so:
- We are safe from breakage that results from upstream device trees moving
a clocks property from the consumer to the syscon provider (like in [1])
- Another syscon consumer can't disable the clock for a syscon that's
also shared via a syscon_base_lookup_by_phandle
I've reviewed the current driver code users of syscon_base_lookup_by_phandle
and all upstream device trees that match against the drivers lack
a clocks property, so this shouldn't alter behavior (for now).
[1]: c9322d4fe ("net: designware: eqos: stm32: drop no longer needed syscfg-clk")
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/base/regmap/regmap-mmio.c | 5 ++++-
drivers/mfd/syscon.c | 4 ++++
include/regmap.h | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/base/regmap/regmap-mmio.c b/drivers/base/regmap/regmap-mmio.c
index 7ca95d6bea79..626c6fa3f387 100644
--- a/drivers/base/regmap/regmap-mmio.c
+++ b/drivers/base/regmap/regmap-mmio.c
@@ -308,9 +308,12 @@ int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
return 0;
}
-void regmap_mmio_detach_clk(struct regmap *map)
+struct clk *regmap_mmio_detach_clk(struct regmap *map)
{
struct regmap_mmio_context *ctx = map->bus_context;
+ struct clk *clk = ctx->clk;
ctx->clk = NULL;
+
+ return clk;
}
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index 67e2ebb6c2f5..ba0489bf95a8 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -128,10 +128,14 @@ static struct syscon *node_to_syscon(struct device_node *np)
static void __iomem *syscon_node_to_base(struct device_node *np)
{
struct syscon *syscon = node_to_syscon(np);
+ struct clk *clk;
if (IS_ERR(syscon))
return ERR_CAST(syscon);
+ clk = regmap_mmio_detach_clk(syscon->regmap);
+ clk_enable(clk);
+
return syscon->base;
}
diff --git a/include/regmap.h b/include/regmap.h
index 4172c00bd2da..d950971b7d48 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -91,7 +91,7 @@ struct regmap *regmap_init_mmio_clk(struct device_d *dev, const char *clk_id,
int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk);
-void regmap_mmio_detach_clk(struct regmap *map);
+struct clk *regmap_mmio_detach_clk(struct regmap *map);
void regmap_exit(struct regmap *map);
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 02/21] mfd: syscon: refactor of_syscon_register compatible check
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 03/21] mfd: syscon: implement device_node_to_regmap Ahmad Fatoum
` (19 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Linux also provides a device_node_to_regmap function that doesn't do a
compatible = "syscon" check. In preparation for having it in barebox,
factor out the compatible check into the callers.
While at it make the clock checking explicit, so the diff clearly
indicates, we touched all instances and to prepare for follow-up
commits.
No functional change.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/mfd/syscon.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index ba0489bf95a8..5f391dc08b10 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -46,9 +46,6 @@ static struct syscon *of_syscon_register(struct device_node *np, bool check_clk)
int ret;
struct resource res;
- if (!of_device_is_compatible(np, "syscon"))
- return ERR_PTR(-EINVAL);
-
syscon = xzalloc(sizeof(*syscon));
if (of_address_to_resource(np, 0, &res)) {
@@ -106,7 +103,7 @@ err_map:
return ERR_PTR(ret);
}
-static struct syscon *node_to_syscon(struct device_node *np)
+static struct syscon *node_to_syscon(struct device_node *np, bool check_clk)
{
struct syscon *entry, *syscon = NULL;
@@ -117,7 +114,7 @@ static struct syscon *node_to_syscon(struct device_node *np)
}
if (!syscon)
- syscon = of_syscon_register(np, true);
+ syscon = of_syscon_register(np, check_clk);
if (IS_ERR(syscon))
return ERR_CAST(syscon);
@@ -127,9 +124,13 @@ static struct syscon *node_to_syscon(struct device_node *np)
static void __iomem *syscon_node_to_base(struct device_node *np)
{
- struct syscon *syscon = node_to_syscon(np);
+ struct syscon *syscon;
struct clk *clk;
+ if (!of_device_is_compatible(np, "syscon"))
+ return ERR_PTR(-EINVAL);
+
+ syscon = node_to_syscon(np, true);
if (IS_ERR(syscon))
return ERR_CAST(syscon);
@@ -172,8 +173,12 @@ void __iomem *syscon_base_lookup_by_phandle(struct device_node *np,
struct regmap *syscon_node_to_regmap(struct device_node *np)
{
- struct syscon *syscon = node_to_syscon(np);
+ struct syscon *syscon;
+
+ if (!of_device_is_compatible(np, "syscon"))
+ return ERR_PTR(-EINVAL);
+ syscon = node_to_syscon(np, true);
if (IS_ERR(syscon))
return ERR_CAST(syscon);
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 03/21] mfd: syscon: implement device_node_to_regmap
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 02/21] mfd: syscon: refactor of_syscon_register compatible check Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 04/21] regmap: retire of_node_to_regmap in favor of device_node_to_regmap Ahmad Fatoum
` (18 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Extend our syscon API with a device_node_to_regmap function that has the
same semantics as upstream:
__________________________________________________________________________
| Linux commit 39233b7c611248c0d05209b4854bc63e26485655
| CommitDate: Thu Aug 8 15:30:07 2019 -0700
|
| mfd/syscon: Add device_node_to_regmap()
|
| device_node_to_regmap() is exactly like syscon_node_to_regmap(), but it
| does not check that the node is compatible with "syscon", and won't
| attach the first clock it finds to the regmap.
|
| The rationale behind this, is that one device node with a standard
| compatible string "foo,bar" can be covered by multiple drivers sharing a
| regmap, or by a single driver doing all the job without a regmap, but
| these are implementation details which shouldn't reflect on the
| devicetree.
|
| Signed-off-by: Paul Cercueil <paul@crapouillou.net>
| Acked-by: Arnd Bergmann <arnd@arndb.de>
| Signed-off-by: Paul Burton <paul.burton@mips.com>
|__________________________________________________________________________
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/mfd/syscon.c | 21 ++++++++++++++++-----
include/mfd/syscon.h | 5 +++++
2 files changed, 21 insertions(+), 5 deletions(-)
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index 5f391dc08b10..2d7a31095b31 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -171,20 +171,31 @@ void __iomem *syscon_base_lookup_by_phandle(struct device_node *np,
return syscon_node_to_base(syscon_np);
}
-struct regmap *syscon_node_to_regmap(struct device_node *np)
+static struct regmap *__device_node_to_regmap(struct device_node *np,
+ bool check_clk)
{
struct syscon *syscon;
- if (!of_device_is_compatible(np, "syscon"))
- return ERR_PTR(-EINVAL);
-
- syscon = node_to_syscon(np, true);
+ syscon = node_to_syscon(np, check_clk);
if (IS_ERR(syscon))
return ERR_CAST(syscon);
return syscon->regmap;
}
+struct regmap *device_node_to_regmap(struct device_node *np)
+{
+ return __device_node_to_regmap(np, false);
+}
+
+struct regmap *syscon_node_to_regmap(struct device_node *np)
+{
+ if (!of_device_is_compatible(np, "syscon"))
+ return ERR_PTR(-EINVAL);
+
+ return __device_node_to_regmap(np, true);
+}
+
struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
{
struct device_node *syscon_np;
diff --git a/include/mfd/syscon.h b/include/mfd/syscon.h
index ac33f2d34747..b47aa1e160e6 100644
--- a/include/mfd/syscon.h
+++ b/include/mfd/syscon.h
@@ -21,6 +21,7 @@ void __iomem *syscon_base_lookup_by_pdevname(const char *s);
void __iomem *syscon_base_lookup_by_phandle
(struct device_node *np, const char *property);
struct regmap *syscon_node_to_regmap(struct device_node *np);
+struct regmap *device_node_to_regmap(struct device_node *np);
struct regmap *syscon_regmap_lookup_by_compatible(const char *s);
extern struct regmap *syscon_regmap_lookup_by_phandle(
struct device_node *np,
@@ -41,6 +42,10 @@ static inline struct regmap *syscon_node_to_regmap(struct device_node *np)
{
return ERR_PTR(-ENOSYS);
}
+static inline struct regmap *device_node_to_regmap(struct device_node *np)
+{
+ return ERR_PTR(-ENOSYS);
+}
static inline struct regmap *syscon_regmap_lookup_by_compatible(const char *s)
{
return ERR_PTR(-ENOSYS);
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 04/21] regmap: retire of_node_to_regmap in favor of device_node_to_regmap
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (2 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 03/21] mfd: syscon: implement device_node_to_regmap Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 05/21] ARM: include: remove unused <asm/processor.h> Ahmad Fatoum
` (17 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
device_node_to_regmap is the current upstream API for this and is more
general, because it allocates a regmap on demand if none exists.
As of_node_to_regmap is unused anywhere, remove it.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/base/regmap/regmap.c | 20 --------------------
include/regmap.h | 1 -
2 files changed, 21 deletions(-)
diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c
index ee5120fd7465..6613670263f6 100644
--- a/drivers/base/regmap/regmap.c
+++ b/drivers/base/regmap/regmap.c
@@ -132,26 +132,6 @@ struct regmap *dev_get_regmap(struct device_d *dev, const char *name)
return ERR_PTR(-ENOENT);
}
-/*
- * of_node_to_regmap - get a regmap from a device node
- *
- * node: The device node
- *
- * Returns a pointer to the regmap or a ERR_PTR if the node has no
- * regmap attached.
- */
-struct regmap *of_node_to_regmap(struct device_node *node)
-{
- struct regmap *map;
-
- list_for_each_entry(map, ®maps, list) {
- if (map->dev && map->dev->device_node == node)
- return map;
- }
-
- return ERR_PTR(-ENOENT);
-}
-
/*
* regmap_write - write a register in a map
*
diff --git a/include/regmap.h b/include/regmap.h
index d950971b7d48..a34a9d2324c2 100644
--- a/include/regmap.h
+++ b/include/regmap.h
@@ -96,7 +96,6 @@ struct clk *regmap_mmio_detach_clk(struct regmap *map);
void regmap_exit(struct regmap *map);
struct regmap *dev_get_regmap(struct device_d *dev, const char *name);
-struct regmap *of_node_to_regmap(struct device_node *node);
int regmap_register_cdev(struct regmap *map, const char *name);
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 05/21] ARM: include: remove unused <asm/processor.h>
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (3 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 04/21] regmap: retire of_node_to_regmap in favor of device_node_to_regmap Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 06/21] treewide: use cpu_relax() where appropriate Ahmad Fatoum
` (16 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
File has been in source tree for 17 years and is unused.
Drop it. The only definition we might want out of the file is
cpu_relax(), which we already open code as barrier() with a comment in a
couple of places. Move the definition to <linux/barebox-wrapper.h>
and drop the file altogether.
No functional change.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/include/asm/processor.h | 131 -------------------------------
include/linux/barebox-wrapper.h | 2 +
2 files changed, 2 insertions(+), 131 deletions(-)
delete mode 100644 arch/arm/include/asm/processor.h
diff --git a/arch/arm/include/asm/processor.h b/arch/arm/include/asm/processor.h
deleted file mode 100644
index d5dbab0ac283..000000000000
--- a/arch/arm/include/asm/processor.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * linux/include/asm-arm/processor.h
- *
- * Copyright (C) 1995-2002 Russell King
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_PROCESSOR_H
-#define __ASM_ARM_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#define FP_SIZE 35
-
-struct fp_hard_struct {
- unsigned int save[FP_SIZE]; /* as yet undefined */
-};
-
-struct fp_soft_struct {
- unsigned int save[FP_SIZE]; /* undefined information */
-};
-
-union fp_state {
- struct fp_hard_struct hard;
- struct fp_soft_struct soft;
-};
-
-typedef unsigned long mm_segment_t; /* domain register */
-
-#ifdef __KERNEL__
-
-#define EISA_bus 0
-#define MCA_bus 0
-#define MCA_bus__is_a_macro
-
-#include <asm/atomic.h>
-#include <asm/ptrace.h>
-#include <asm/proc/processor.h>
-#include <asm/types.h>
-
-union debug_insn {
- u32 arm;
- u16 thumb;
-};
-
-struct debug_entry {
- u32 address;
- union debug_insn insn;
-};
-
-struct debug_info {
- int nsaved;
- struct debug_entry bp[2];
-};
-
-struct thread_struct {
- atomic_t refcount;
- /* fault info */
- unsigned long address;
- unsigned long trap_no;
- unsigned long error_code;
- /* floating point */
- union fp_state fpstate;
- /* debugging */
- struct debug_info debug;
- /* context info */
- struct context_save_struct *save;
- EXTRA_THREAD_STRUCT
-};
-
-#define INIT_THREAD { \
- refcount: ATOMIC_INIT(1), \
- EXTRA_THREAD_STRUCT_INIT \
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-static inline unsigned long thread_saved_pc(struct thread_struct *t)
-{
- return t->save ? pc_pointer(t->save->pc) : 0;
-}
-
-static inline unsigned long thread_saved_fp(struct thread_struct *t)
-{
- return t->save ? t->save->fp : 0;
-}
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-extern void release_thread(struct task_struct *);
-
-/* Copy and release all segment info associated with a VM */
-#define copy_segments(tsk, mm) do { } while (0)
-#define release_segments(mm) do { } while (0)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define THREAD_SIZE (8192)
-
-extern struct task_struct *alloc_task_struct(void);
-extern void __free_task_struct(struct task_struct *);
-#define get_task_struct(p) atomic_inc(&(p)->thread.refcount)
-#define free_task_struct(p) \
- do { \
- if (atomic_dec_and_test(&(p)->thread.refcount)) \
- __free_task_struct((p)); \
- } while (0)
-
-#define init_task (init_task_union.task)
-#define init_stack (init_task_union.stack)
-
-#define cpu_relax() barrier()
-
-/*
- * Create a new kernel thread
- */
-extern int arch_kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
-
-#endif
-
-#endif /* __ASM_ARM_PROCESSOR_H */
diff --git a/include/linux/barebox-wrapper.h b/include/linux/barebox-wrapper.h
index e998932d1201..82c52dd93309 100644
--- a/include/linux/barebox-wrapper.h
+++ b/include/linux/barebox-wrapper.h
@@ -52,4 +52,6 @@ typedef int irqreturn_t;
#define __clk_get_rate clk_get_rate
#define __clk_get_parent clk_get_parent
+#define cpu_relax() barrier()
+
#endif /* __INCLUDE_LINUX_BAREBOX_WRAPPER_H */
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 06/21] treewide: use cpu_relax() where appropriate
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (4 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 05/21] ARM: include: remove unused <asm/processor.h> Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 07/21] of: port Linux of_get_compatible_child helper Ahmad Fatoum
` (15 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Instead of doing /* cpu_relax(); */ barrier(); on upstream uses of
cpu_relax(), just use the new cpu_relax() #define directly.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-omap/omap4_rom_usb.c | 6 ++----
drivers/mtd/nand/nand_denali.c | 8 +++-----
2 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-omap/omap4_rom_usb.c b/arch/arm/mach-omap/omap4_rom_usb.c
index 31d93c34ee52..0b3124059021 100644
--- a/arch/arm/mach-omap/omap4_rom_usb.c
+++ b/arch/arm/mach-omap/omap4_rom_usb.c
@@ -111,8 +111,7 @@ int omap4_usbboot_wait_read(void)
{
int ret;
while (omap4_usbboot_data.dread.status == STATUS_WAITING)
- /* cpu_relax(); */
- barrier();
+ cpu_relax();
ret = omap4_usbboot_data.dread.status;
omap4_usbboot_data.dread.status = -1;
return ret;
@@ -153,8 +152,7 @@ int omap4_usbboot_wait_write(void)
{
int ret;
while (omap4_usbboot_data.dwrite.status == STATUS_WAITING)
- /* cpu_relax(); */
- barrier();
+ cpu_relax();
ret = omap4_usbboot_data.dwrite.status;
omap4_usbboot_data.dwrite.status = -1;
return ret;
diff --git a/drivers/mtd/nand/nand_denali.c b/drivers/mtd/nand/nand_denali.c
index ddb03813fe78..89958456491d 100644
--- a/drivers/mtd/nand/nand_denali.c
+++ b/drivers/mtd/nand/nand_denali.c
@@ -171,7 +171,7 @@ static void reset_bank(struct denali_nand_info *denali)
/* wait for completion */
while (ioread32(denali->flash_reg + DEVICE_RESET) & (1 << denali->flash_bank))
- barrier();
+ cpu_relax();
}
/* Reset the flash controller */
@@ -187,8 +187,7 @@ static uint16_t denali_nand_reset(struct denali_nand_info *denali)
iowrite32(1 << i, denali->flash_reg + DEVICE_RESET);
while (!(ioread32(denali->flash_reg + INTR_STATUS(i)) &
(INTR_STATUS__RST_COMP | INTR_STATUS__TIME_OUT)))
- /* cpu_relax(); */
- barrier();
+ cpu_relax();
if (ioread32(denali->flash_reg + INTR_STATUS(i)) &
INTR_STATUS__TIME_OUT)
dev_dbg(denali->dev,
@@ -953,8 +952,7 @@ static bool handle_ecc(struct denali_nand_info *denali, uint8_t *buf,
*/
while (!(read_interrupt_status(denali) &
INTR_STATUS__ECC_TRANSACTION_DONE))
- /* cpu_relax(); */
- barrier();
+ cpu_relax();
clear_interrupts(denali);
denali_set_intr_modes(denali, true);
}
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 07/21] of: port Linux of_get_compatible_child helper
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (5 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 06/21] treewide: use cpu_relax() where appropriate Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-14 6:46 ` Sascha Hauer
2020-04-13 7:51 ` [PATCH 08/21] clk: implement clk_register_fixed_rate Ahmad Fatoum
` (14 subsequent siblings)
21 siblings, 1 reply; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Incoming Linux code port makes use of the helper. Add it now instead of
having to open-code it later.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/of/base.c | 25 +++++++++++++++++++++++++
include/of.h | 8 ++++++++
2 files changed, 33 insertions(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 346d72e1e09e..5a0374a82c5c 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1712,6 +1712,31 @@ int of_get_available_child_count(const struct device_node *parent)
}
EXPORT_SYMBOL(of_get_available_child_count);
+/**
+ * of_get_compatible_child - Find compatible child node
+ * @parent: parent node
+ * @compatible: compatible string
+ *
+ * Lookup child node whose compatible property contains the given compatible
+ * string.
+ *
+ * Returns a node pointer with refcount incremented, use of_node_put() on it
+ * when done; or NULL if not found.
+ */
+struct device_node *of_get_compatible_child(const struct device_node *parent,
+ const char *compatible)
+{
+ struct device_node *child;
+
+ for_each_child_of_node(parent, child) {
+ if (of_device_is_compatible(child, compatible))
+ break;
+ }
+
+ return child;
+}
+EXPORT_SYMBOL(of_get_compatible_child);
+
/**
* of_get_child_by_name - Find the child node by name for a given parent
* @node: parent node
diff --git a/include/of.h b/include/of.h
index eea5abae459b..85d55f9b57dc 100644
--- a/include/of.h
+++ b/include/of.h
@@ -177,6 +177,8 @@ struct device_node *of_get_next_child(const struct device_node *node,
struct device_node *prev);
extern int of_get_child_count(const struct device_node *parent);
extern int of_get_available_child_count(const struct device_node *parent);
+extern struct device_node *of_get_compatible_child(const struct device_node *parent,
+ const char *compatible);
extern struct device_node *of_get_child_by_name(const struct device_node *node,
const char *name);
extern char *of_get_reproducible_name(struct device_node *node);
@@ -380,6 +382,12 @@ static inline int of_get_available_child_count(const struct device_node *parent)
return -ENOSYS;
}
+static inline struct device_node *of_get_compatible_child(const struct device_node *parent,
+ const char *compatible)
+{
+ return NULL;
+}
+
static inline struct device_node *of_get_child_by_name(
const struct device_node *node, const char *name)
{
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 08/21] clk: implement clk_register_fixed_rate
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (6 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 07/21] of: port Linux of_get_compatible_child helper Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 09/21] clk: add clk_unregister stub Ahmad Fatoum
` (13 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
We lack a way to instantiate a fixed clock while specifying a parent.
This is used in the at91 clock code sync with upstream in a later
commit, so prepare by porting clk_register_fixed_rate.
It's based on the Linux commit of the same name with the difference that
it doesn't use (and thus doesn't require) a struct device_d * as first
parameter.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/clk-fixed.c | 16 +++++++++++++++-
include/linux/clk.h | 9 ++++++++-
2 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c
index 57bf36b39ecd..411f6fe4736a 100644
--- a/drivers/clk/clk-fixed.c
+++ b/drivers/clk/clk-fixed.c
@@ -37,17 +37,31 @@ static struct clk_ops clk_fixed_ops = {
.is_enabled = clk_is_enabled_always,
};
-struct clk *clk_fixed(const char *name, int rate)
+struct clk *clk_register_fixed_rate(const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned long rate)
{
struct clk_fixed *fix = xzalloc(sizeof *fix);
+ const char **parent_names = NULL;
int ret;
fix->rate = rate;
fix->clk.ops = &clk_fixed_ops;
fix->clk.name = name;
+ fix->clk.flags = flags;
+
+ if (parent_name) {
+ parent_names = kzalloc(sizeof(const char *), GFP_KERNEL);
+ if (!parent_names)
+ return ERR_PTR(-ENOMEM);
+
+ fix->clk.parent_names = parent_names;
+ fix->clk.num_parents = 1;
+ }
ret = clk_register(&fix->clk);
if (ret) {
+ free(parent_names);
free(fix);
return ERR_PTR(ret);
}
diff --git a/include/linux/clk.h b/include/linux/clk.h
index c3aeea80ddc5..efb0fe4415aa 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -325,7 +325,14 @@ struct clk_div_table {
unsigned int div;
};
-struct clk *clk_fixed(const char *name, int rate);
+struct clk *clk_register_fixed_rate(const char *name,
+ const char *parent_name, unsigned long flags,
+ unsigned long fixed_rate);
+
+static inline struct clk *clk_fixed(const char *name, int rate)
+{
+ return clk_register_fixed_rate(name, NULL, 0, rate);
+}
struct clk_divider {
struct clk clk;
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 09/21] clk: add clk_unregister stub
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (7 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 08/21] clk: implement clk_register_fixed_rate Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 10/21] include: linux/kernel.h: port DIV_ROUND_CLOSEST_ULL definition Ahmad Fatoum
` (12 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Make kernel clk driver import a tiny bit more convenient by allowing
clk_unregister calls and control flow to remain as is.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
include/linux/clk.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/include/linux/clk.h b/include/linux/clk.h
index efb0fe4415aa..a005e7233de8 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -558,4 +558,8 @@ int clk_name_complete(struct string_list *sl, char *instr);
char *of_clk_get_parent_name(struct device_node *np, unsigned int index);
+static inline void clk_unregister(struct clk *clk)
+{
+}
+
#endif
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 10/21] include: linux/kernel.h: port DIV_ROUND_CLOSEST_ULL definition
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (8 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 09/21] clk: add clk_unregister stub Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 11/21] clk: migrate to SPDX-License-Identifier use Ahmad Fatoum
` (11 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
We already have DIV_ROUND_CLOSEST, but no DIV_ROUND_CLOSEST_ULL.
Import the latter for use by later commits.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
include/linux/kernel.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index b320f7e902f0..23c23a73f588 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -6,6 +6,7 @@
#include <linux/bug.h>
#include <linux/barebox-wrapper.h>
#include <linux/limits.h>
+#include <asm-generic/div64.h>
#define ALIGN(x, a) __ALIGN_MASK(x, (typeof(x))(a) - 1)
#define ALIGN_DOWN(x, a) ALIGN((x) - ((a) - 1), (a))
@@ -41,6 +42,18 @@
(((x) + ((__divisor) / 2)) / (__divisor)); \
} \
)
+/*
+ * Same as above but for u64 dividends. divisor must be a 32-bit
+ * number.
+ */
+#define DIV_ROUND_CLOSEST_ULL(x, divisor)( \
+{ \
+ typeof(divisor) __d = divisor; \
+ unsigned long long _tmp = (x) + (__d) / 2; \
+ do_div(_tmp, __d); \
+ _tmp; \
+} \
+)
/**
* upper_32_bits - return bits 32-63 of a number
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 11/21] clk: migrate to SPDX-License-Identifier use
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (9 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 10/21] include: linux/kernel.h: port DIV_ROUND_CLOSEST_ULL definition Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 12/21] clk: at91: fix masterck name Ahmad Fatoum
` (10 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Some of these are a product of source sync with Linux, the other were
done with macro assistance by searching for /later/, deleting license text,
adding appropriate SPDX-License-Identifier and manual post-review.
Devices without a license indicated where assumed GPL-2.0-only according
with the project's license.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/at91/Makefile | 1 +
drivers/clk/at91/clk-generated.c | 7 +------
drivers/clk/at91/clk-h32mx.c | 7 +------
drivers/clk/at91/clk-main.c | 7 +------
drivers/clk/at91/clk-master.c | 7 +------
drivers/clk/at91/clk-peripheral.c | 7 +------
drivers/clk/at91/clk-pll.c | 7 +------
drivers/clk/at91/clk-plldiv.c | 7 +------
drivers/clk/at91/clk-programmable.c | 7 +------
drivers/clk/at91/clk-slow.c | 7 +------
drivers/clk/at91/clk-smd.c | 7 +------
drivers/clk/at91/clk-system.c | 7 +------
drivers/clk/at91/clk-usb.c | 7 +------
drivers/clk/at91/clk-utmi.c | 7 +------
drivers/clk/at91/pmc.c | 7 +------
drivers/clk/at91/pmc.h | 6 +-----
drivers/clk/at91/sckc.c | 7 +------
drivers/clk/clk-ar933x.c | 13 +------------
drivers/clk/clk-ar9344.c | 10 +---------
drivers/clk/clk-composite.c | 13 +------------
drivers/clk/clk-conf.c | 5 +----
drivers/clk/clk-divider.c | 12 +-----------
drivers/clk/clk-fixed-factor.c | 12 +-----------
drivers/clk/clk-fixed.c | 12 +-----------
drivers/clk/clk-fractional-divider.c | 5 +----
drivers/clk/clk-gate-shared.c | 12 +-----------
drivers/clk/clk-gate.c | 12 +-----------
drivers/clk/clk-gpio.c | 12 +-----------
drivers/clk/clk-mux.c | 12 +-----------
drivers/clk/clk-qoric.c | 5 +----
drivers/clk/clk.c | 12 +-----------
drivers/clk/clkdev.c | 5 +----
drivers/clk/imx/Makefile | 1 +
drivers/clk/imx/clk-cpu.c | 8 +-------
drivers/clk/imx/clk-frac-pll.c | 8 +-------
drivers/clk/imx/clk-gate-exclusive.c | 5 +----
drivers/clk/imx/clk-gate2.c | 12 +-----------
drivers/clk/imx/clk-imx1.c | 14 +-------------
drivers/clk/imx/clk-imx21.c | 15 +--------------
drivers/clk/imx/clk-imx25.c | 15 +--------------
drivers/clk/imx/clk-imx27.c | 1 +
drivers/clk/imx/clk-imx31.c | 14 +-------------
drivers/clk/imx/clk-imx35.c | 6 +-----
drivers/clk/imx/clk-imx5.c | 6 +-----
drivers/clk/imx/clk-imx6.c | 8 +-------
drivers/clk/imx/clk-imx6sl.c | 8 +-------
drivers/clk/imx/clk-imx6sx.c | 8 +-------
drivers/clk/imx/clk-imx6ul.c | 8 +-------
drivers/clk/imx/clk-imx7.c | 10 ++--------
drivers/clk/imx/clk-pfd.c | 8 +-------
drivers/clk/imx/clk-pllv1.c | 14 ++------------
drivers/clk/imx/clk-pllv2.c | 14 ++------------
drivers/clk/imx/clk-pllv3.c | 14 ++------------
drivers/clk/imx/clk-sccg-pll.c | 8 +-------
drivers/clk/imx/clk-vf610.c | 7 +------
drivers/clk/imx/clk.c | 1 +
drivers/clk/imx/clk.h | 1 +
drivers/clk/mvebu/Makefile | 1 +
drivers/clk/mvebu/armada-370.c | 5 +----
drivers/clk/mvebu/armada-38x.c | 5 +----
drivers/clk/mvebu/armada-xp.c | 5 +----
drivers/clk/mvebu/common.c | 5 +----
drivers/clk/mvebu/common.h | 5 +----
drivers/clk/mvebu/corediv.c | 5 +----
drivers/clk/mvebu/dove.c | 5 +----
drivers/clk/mvebu/kirkwood.c | 5 +----
drivers/clk/mxs/Makefile | 1 +
drivers/clk/mxs/clk-div.c | 8 +-------
drivers/clk/mxs/clk-frac.c | 8 +-------
drivers/clk/mxs/clk-imx23.c | 14 +-------------
drivers/clk/mxs/clk-imx28.c | 14 +-------------
drivers/clk/mxs/clk-lcdif.c | 1 +
drivers/clk/mxs/clk-pll.c | 8 +-------
drivers/clk/mxs/clk-ref.c | 8 +-------
drivers/clk/mxs/clk.h | 1 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-cpu.c | 5 +----
drivers/clk/rockchip/clk-pll.c | 11 +----------
drivers/clk/rockchip/clk-rk3188.c | 11 +----------
drivers/clk/rockchip/clk-rk3288.c | 11 +----------
drivers/clk/rockchip/clk.c | 11 +----------
drivers/clk/rockchip/clk.h | 11 +----------
drivers/clk/socfpga/Makefile | 1 +
drivers/clk/socfpga/clk-gate-a10.c | 13 +------------
drivers/clk/socfpga/clk-periph-a10.c | 13 +------------
drivers/clk/socfpga/clk-pll-a10.c | 13 +------------
drivers/clk/socfpga/clk.c | 10 +---------
drivers/clk/socfpga/clk.h | 11 +----------
drivers/clk/tegra/Makefile | 1 +
drivers/clk/tegra/clk-divider.c | 13 +------------
drivers/clk/tegra/clk-periph.c | 13 +------------
drivers/clk/tegra/clk-pll-out.c | 13 +------------
drivers/clk/tegra/clk-pll.c | 13 +------------
drivers/clk/tegra/clk-tegra124.c | 13 +------------
drivers/clk/tegra/clk-tegra20.c | 13 +------------
drivers/clk/tegra/clk-tegra30.c | 13 +------------
drivers/clk/tegra/clk.c | 13 +------------
drivers/clk/tegra/clk.h | 13 +------------
drivers/clk/vexpress/Makefile | 1 +
drivers/clk/vexpress/clk-sp810.c | 10 +---------
drivers/clk/vexpress/clk-vexpress-osc.c | 11 +----------
drivers/clk/zynq/Makefile | 1 +
drivers/clk/zynq/clkc.c | 13 +------------
drivers/clk/zynqmp/Makefile | 1 +
include/linux/clk/at91_pmc.h | 6 +-----
107 files changed, 111 insertions(+), 756 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index dedbf6c4dda5..c05e06565192 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
config HAVE_CLK
bool
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 8160620dc618..09032744a0f7 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed.o clk-divider.o clk-fixed-factor.o \
clk-mux.o clk-gate.o clk-composite.o \
clk-fractional-divider.o clk-conf.o \
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index bf9b27f0f4b3..593d34e3487e 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
#
# Makefile for at91 specific clk
#
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 396c35f3a7b3..909c4a4530f8 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -1,14 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Atmel Corporation,
* Nicolas Ferre <nicolas.ferre@atmel.com>
*
* Based on clk-programmable & clk-peripheral drivers by Boris BREZILLON.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
index 31906a9e29c4..fcca37cb52c4 100644
--- a/drivers/clk/at91/clk-h32mx.c
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -1,15 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-h32mx.c
*
* Copyright (C) 2014 Atmel
*
* Alexandre Belloni <alexandre.belloni@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index abae35566c2f..cd61a35c69fd 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
#include <clock.h>
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index f7a0fb1d182b..6bd733ef4194 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
#include <clock.h>
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 00852672da37..9c3791dc5242 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index bc504e8a9510..acf2fae50ea9 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
index 98d79ef5992e..5a9686dc7856 100644
--- a/drivers/clk/at91/clk-plldiv.c
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index 857ede1ca93a..e002c8af47f7 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-slow.c b/drivers/clk/at91/clk-slow.c
index d19f7e15ac42..960678db1c96 100644
--- a/drivers/clk/at91/clk-slow.c
+++ b/drivers/clk/at91/clk-slow.c
@@ -1,13 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/clk/at91/clk-slow.c
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index e81f0d4d4e89..4a541322d459 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index 8be5c7f2b395..a8f30539400e 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
#include <clock.h>
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index 0eb0b1f5bccd..334bd5c88ee7 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index c40af34d0deb..3d71cd615fa2 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 86a50b680b8d..8df3a51f82bf 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <module.h>
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index b553ea259c65..c4de1e802e4e 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -1,12 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* drivers/clk/at91/pmc.h
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
#ifndef __PMC_H_
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index bac28999eac9..4a03819f0e30 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -1,13 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/clk/at91/sckc.c
*
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/clk-ar933x.c b/drivers/clk/clk-ar933x.c
index f5cfd39cd81f..875e9f506f75 100644
--- a/drivers/clk/clk-ar933x.c
+++ b/drivers/clk/clk-ar933x.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Antony Pavlov <antonynpavlov@gmail.com>
*
* Based on the Linux ath79 clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/clk-ar9344.c b/drivers/clk/clk-ar9344.c
index c3c49fb1093a..ad0e5c10e990 100644
--- a/drivers/clk/clk-ar9344.c
+++ b/drivers/clk/clk-ar9344.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2017 Oleksij Rempel <linux@rempel-privat.de>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
*/
#include <common.h>
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index e21ab9845321..e0f543bc1c98 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Taken from linux/drivers/clk/
*
* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/clk-conf.c b/drivers/clk/clk-conf.c
index 93271b4f992e..0bd99993cc4b 100644
--- a/drivers/clk/clk-conf.c
+++ b/drivers/clk/clk-conf.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Samsung Electronics Co., Ltd.
* Sylwester Nawrocki <s.nawrocki@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <common.h>
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 78b4153171d5..cad902fd324b 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-divider.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <io.h>
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 021c43339feb..e7738775f80d 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-fixed-factor.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <io.h>
diff --git a/drivers/clk/clk-fixed.c b/drivers/clk/clk-fixed.c
index 411f6fe4736a..d7ac59c4d48a 100644
--- a/drivers/clk/clk-fixed.c
+++ b/drivers/clk/clk-fixed.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-fixed.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <malloc.h>
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index 1504f7a72868..6f0763b05f97 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Intel Corporation
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
* Adjustable fractional divider clock implementation.
* Output rate = (m / n) * parent_rate.
*/
diff --git a/drivers/clk/clk-gate-shared.c b/drivers/clk/clk-gate-shared.c
index c3b678a311e9..54c002e836fe 100644
--- a/drivers/clk/clk-gate-shared.c
+++ b/drivers/clk/clk-gate-shared.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-gate-shared.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2017 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <io.h>
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b2b160555e6f..59dd643b9912 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-gate.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <io.h>
diff --git a/drivers/clk/clk-gpio.c b/drivers/clk/clk-gpio.c
index 352c85dfe210..1345fbc9ea9a 100644
--- a/drivers/clk/clk-gpio.c
+++ b/drivers/clk/clk-gpio.c
@@ -1,19 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-gpio.c - clock that can be enabled and disabled via GPIO output
* Based on Linux clk support
*
* Copyright (c) 2018 Nikita Yushchenko <nikita.yoush@cogentembedded.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <malloc.h>
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index e9cb6140055b..a4743c51b003 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-mux.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <io.h>
diff --git a/drivers/clk/clk-qoric.c b/drivers/clk/clk-qoric.c
index c40c6e90d96b..2ffc7613fa53 100644
--- a/drivers/clk/clk-qoric.c
+++ b/drivers/clk/clk-qoric.c
@@ -1,10 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2013 Freescale Semiconductor, Inc.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
* clock driver for Freescale QorIQ SoCs.
*/
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index b27ad6d24986..4386c95aa9ec 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -1,18 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk.c - generic barebox clock support. Based on Linux clk support
*
* Copyright (c) 2012 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
#include <errno.h>
diff --git a/drivers/clk/clkdev.c b/drivers/clk/clkdev.c
index f67a5c4d98d5..462a7e16ef63 100644
--- a/drivers/clk/clkdev.c
+++ b/drivers/clk/clkdev.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* drivers/clk/lookup_clkdev.c
*
* Copyright (C) 2008 Russell King.
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
* Helper for the clk API to assist looking up a struct clk.
*/
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
index e627ef4a090a..b1ce9d3d3e91 100644
--- a/drivers/clk/imx/Makefile
+++ b/drivers/clk/imx/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_COMMON_CLK) += \
clk-composite-8m.o \
clk-pllv1.o \
diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c
index 473500131e4c..13b2dfc9ad87 100644
--- a/drivers/clk/imx/clk-cpu.c
+++ b/drivers/clk/imx/clk-cpu.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 Lucas Stach <l.stach@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-frac-pll.c b/drivers/clk/imx/clk-frac-pll.c
index def870e24411..b3d665cff992 100644
--- a/drivers/clk/imx/clk-frac-pll.c
+++ b/drivers/clk/imx/clk-frac-pll.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2017 NXP.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-gate-exclusive.c b/drivers/clk/imx/clk-gate-exclusive.c
index db88db0237e3..4bf4de8bd360 100644
--- a/drivers/clk/imx/clk-gate-exclusive.c
+++ b/drivers/clk/imx/clk-gate-exclusive.c
@@ -1,9 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c
index 8d5ed7e05c1c..88eaae8db3ae 100644
--- a/drivers/clk/imx/clk-gate2.c
+++ b/drivers/clk/imx/clk-gate2.c
@@ -1,16 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* clk-gate2.c - barebox 2-bit clock support. Based on Linux clk support
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx1.c b/drivers/clk/imx/clk-imx1.c
index 9a817c36c0ac..258b9dd582c1 100644
--- a/drivers/clk/imx/clk-imx1.c
+++ b/drivers/clk/imx/clk-imx1.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx21.c b/drivers/clk/imx/clk-imx21.c
index 546461b8eeb6..0026a55f8669 100644
--- a/drivers/clk/imx/clk-imx21.c
+++ b/drivers/clk/imx/clk-imx21.c
@@ -1,21 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
* Copyright 2008 Martin Fuzzey, mfuzzey@gmail.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx25.c b/drivers/clk/imx/clk-imx25.c
index ce4fbed68cab..7c2140c215a6 100644
--- a/drivers/clk/imx/clk-imx25.c
+++ b/drivers/clk/imx/clk-imx25.c
@@ -1,19 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx27.c b/drivers/clk/imx/clk-imx27.c
index 4b632442116c..cba655c6fea9 100644
--- a/drivers/clk/imx/clk-imx27.c
+++ b/drivers/clk/imx/clk-imx27.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
#include <common.h>
#include <init.h>
#include <driver.h>
diff --git a/drivers/clk/imx/clk-imx31.c b/drivers/clk/imx/clk-imx31.c
index dbb5c15d1243..5fded58b114a 100644
--- a/drivers/clk/imx/clk-imx31.c
+++ b/drivers/clk/imx/clk-imx31.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2012 Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation.
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx35.c b/drivers/clk/imx/clk-imx35.c
index af6c4058d7c5..17e2ae5e6918 100644
--- a/drivers/clk/imx/clk-imx35.c
+++ b/drivers/clk/imx/clk-imx35.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#include <common.h>
#include <init.h>
diff --git a/drivers/clk/imx/clk-imx5.c b/drivers/clk/imx/clk-imx5.c
index 69ac2f5e3ed2..6a07816427aa 100644
--- a/drivers/clk/imx/clk-imx5.c
+++ b/drivers/clk/imx/clk-imx5.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
*/
#include <common.h>
#include <init.h>
diff --git a/drivers/clk/imx/clk-imx6.c b/drivers/clk/imx/clk-imx6.c
index ed29e8c271ad..b8b37a0c6832 100644
--- a/drivers/clk/imx/clk-imx6.c
+++ b/drivers/clk/imx/clk-imx6.c
@@ -1,13 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2011 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 89ede769f854..6ccc36e3b922 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/clock/imx6sl-clock.h>
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index d758957d4d09..d682e41e7c8b 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <dt-bindings/clock/imx6sx-clock.h>
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index 35483efde6ca..79b52b7ce936 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-imx7.c b/drivers/clk/imx/clk-imx7.c
index 781bc43e09d3..1f15d7ef11bc 100644
--- a/drivers/clk/imx/clk-imx7.c
+++ b/drivers/clk/imx/clk-imx7.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
@@ -866,4 +860,4 @@ static int imx7_ccm_init(void)
{
return platform_driver_register(&imx7_ccm_driver);
}
-core_initcall(imx7_ccm_init);
\ No newline at end of file
+core_initcall(imx7_ccm_init);
diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
index 8f6d5ad7a803..eb2b1700ae93 100644
--- a/drivers/clk/imx/clk-pfd.c
+++ b/drivers/clk/imx/clk-pfd.c
@@ -1,13 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Copyright 2012 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-pllv1.c b/drivers/clk/imx/clk-pllv1.c
index f992134f7ea7..9b5d28f22fbe 100644
--- a/drivers/clk/imx/clk-pllv1.c
+++ b/drivers/clk/imx/clk-pllv1.c
@@ -1,15 +1,5 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+
#include <common.h>
#include <init.h>
#include <driver.h>
diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c
index 5ba07fa5e6c1..56005ca725e2 100644
--- a/drivers/clk/imx/clk-pllv2.c
+++ b/drivers/clk/imx/clk-pllv2.c
@@ -1,15 +1,5 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+
#include <common.h>
#include <init.h>
#include <driver.h>
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 44642e88f302..e10b61b04055 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -1,15 +1,5 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
+// SPDX-License-Identifier: GPL-2.0-or-later
+
#include <common.h>
#include <init.h>
#include <driver.h>
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index bbfd95a11c61..aabab27a22a9 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2017 NXP.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk-vf610.c b/drivers/clk/imx/clk-vf610.c
index 4f7e097a8945..1bd1fe5c44d8 100644
--- a/drivers/clk/imx/clk-vf610.c
+++ b/drivers/clk/imx/clk-vf610.c
@@ -1,11 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012-2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
*/
#include <common.h>
diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c
index 7488dfcdc850..0994a149adf3 100644
--- a/drivers/clk/imx/clk.c
+++ b/drivers/clk/imx/clk.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
#include <common.h>
#include <init.h>
#include <driver.h>
diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index 39eff9ee74ae..5cd2c56a1b6c 100644
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __IMX_CLK_H
#define __IMX_CLK_H
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 53c759e4ef17..63beb80722a6 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += common.o
obj-$(CONFIG_ARCH_ARMADA_370) += armada-370.o corediv.o
obj-$(CONFIG_ARCH_ARMADA_XP) += armada-xp.o corediv.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
index 8d02ed93d905..d2ad1ba0cc62 100644
--- a/drivers/clk/mvebu/armada-370.c
+++ b/drivers/clk/mvebu/armada-370.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell Armada 370 SoC clocks
*
@@ -5,10 +6,6 @@
*
* Based on Linux Marvell MVEBU clock providers
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mvebu/armada-38x.c b/drivers/clk/mvebu/armada-38x.c
index d2d7c2a22576..627de7de6ce0 100644
--- a/drivers/clk/mvebu/armada-38x.c
+++ b/drivers/clk/mvebu/armada-38x.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell Armada 380/385 SoC clocks
*
@@ -6,10 +7,6 @@
* Gregory CLEMENT <gregory.clement@free-electrons.com>
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
index ffe4f2736d5e..d79f846d3f0e 100644
--- a/drivers/clk/mvebu/armada-xp.c
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell Armada XP SoC clocks
*
@@ -5,10 +6,6 @@
*
* Based on Linux Marvell MVEBU clock providers
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
index 609e63697ce9..c7de00ac77de 100644
--- a/drivers/clk/mvebu/common.c
+++ b/drivers/clk/mvebu/common.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell EBU SoC common clock handling
*
@@ -5,10 +6,6 @@
*
* Based on Linux Marvell MVEBU clock providers
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
index a3b27247f79e..8256d9c2f08e 100644
--- a/drivers/clk/mvebu/common.h
+++ b/drivers/clk/mvebu/common.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Marvell EBU SoC common clock handling
*
@@ -5,10 +6,6 @@
*
* Based on Linux Marvell MVEBU clock providers
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#ifndef __CLK_MVEBU_COMMON_H_
diff --git a/drivers/clk/mvebu/corediv.c b/drivers/clk/mvebu/corediv.c
index 87b1f8bd7c58..f740161e4540 100644
--- a/drivers/clk/mvebu/corediv.c
+++ b/drivers/clk/mvebu/corediv.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* MVEBU Core divider clock
*
@@ -6,10 +7,6 @@
* Based on Linux driver
* Copyright (C) 2013 Marvell
* Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
index 9bdf89a62338..ca9af2671d13 100644
--- a/drivers/clk/mvebu/dove.c
+++ b/drivers/clk/mvebu/dove.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell Dove SoC clocks
*
@@ -5,10 +6,6 @@
*
* Based on Linux Marvell MVEBU clock providers
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
index 5024baf18e1c..252bf2c69a95 100644
--- a/drivers/clk/mvebu/kirkwood.c
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Marvell Kirkwood SoC clocks
*
@@ -5,10 +6,6 @@
*
* Based on Linux Marvell MVEBU clock providers
* Copyright (C) 2012 Marvell
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
*/
#include <common.h>
diff --git a/drivers/clk/mxs/Makefile b/drivers/clk/mxs/Makefile
index fb4e5dbeead8..e1e3e5d70f94 100644
--- a/drivers/clk/mxs/Makefile
+++ b/drivers/clk/mxs/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_ARCH_MXS) += clk-ref.o clk-pll.o clk-frac.o clk-div.o
obj-$(CONFIG_DRIVER_VIDEO_STM) += clk-lcdif.o
diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c
index 797e5a274fd0..104587a8dce8 100644
--- a/drivers/clk/mxs/clk-div.c
+++ b/drivers/clk/mxs/clk-div.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c
index 7aa85045a410..21e572ff6f3a 100644
--- a/drivers/clk/mxs/clk-frac.c
+++ b/drivers/clk/mxs/clk-frac.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index 526efc52beaf..dae8e348e21b 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <common.h>
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 12bc9dd97741..4adb1c6866c9 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <common.h>
diff --git a/drivers/clk/mxs/clk-lcdif.c b/drivers/clk/mxs/clk-lcdif.c
index 86dfe890f995..246e68068dc0 100644
--- a/drivers/clk/mxs/clk-lcdif.c
+++ b/drivers/clk/mxs/clk-lcdif.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
#include <common.h>
#include <io.h>
#include <linux/clk.h>
diff --git a/drivers/clk/mxs/clk-pll.c b/drivers/clk/mxs/clk-pll.c
index 1b1c9b35434b..7527a777311a 100644
--- a/drivers/clk/mxs/clk-pll.c
+++ b/drivers/clk/mxs/clk-pll.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c
index 8d0be05615c9..16a2fc299122 100644
--- a/drivers/clk/mxs/clk-ref.c
+++ b/drivers/clk/mxs/clk-ref.c
@@ -1,12 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
*/
#include <common.h>
diff --git a/drivers/clk/mxs/clk.h b/drivers/clk/mxs/clk.h
index 00895de50718..60f2408cbadb 100644
--- a/drivers/clk/mxs/clk.h
+++ b/drivers/clk/mxs/clk.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __MXS_CLK_H
#define __MXS_CLK_H
diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile
index e43f57304c1d..5fcf0c25150c 100644
--- a/drivers/clk/rockchip/Makefile
+++ b/drivers/clk/rockchip/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clk-cpu.o clk-pll.o clk.o
obj-$(CONFIG_ARCH_RK3188) += clk-rk3188.o
obj-$(CONFIG_ARCH_RK3288) += clk-rk3288.o
diff --git a/drivers/clk/rockchip/clk-cpu.c b/drivers/clk/rockchip/clk-cpu.c
index 226b8192425c..71a64f71f6ff 100644
--- a/drivers/clk/rockchip/clk-cpu.c
+++ b/drivers/clk/rockchip/clk-cpu.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
@@ -6,10 +7,6 @@
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
* A CPU clock is defined as a clock supplied to a CPU or a group of CPUs.
* The CPU clock is typically derived from a hierarchy of clock
* blocks which includes mux and divider blocks. There are a number of other
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 39ccf0a22673..8d3fd6cf1c1d 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <asm-generic/div64.h>
diff --git a/drivers/clk/rockchip/clk-rk3188.c b/drivers/clk/rockchip/clk-rk3188.c
index 93407399459a..61dfb27ef4f4 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <common.h>
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index dcfaae24070e..b6c122d39366 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -1,16 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <common.h>
diff --git a/drivers/clk/rockchip/clk.c b/drivers/clk/rockchip/clk.c
index 9e0cbadd57ec..833e9bed0ece 100644
--- a/drivers/clk/rockchip/clk.c
+++ b/drivers/clk/rockchip/clk.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
@@ -8,16 +9,6 @@
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <common.h>
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index d6798a905513..006225b7e846 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* Copyright (c) 2014 MundoReader S.L.
* Author: Heiko Stuebner <heiko@sntech.de>
@@ -8,16 +9,6 @@
* Copyright (c) 2013 Samsung Electronics Co., Ltd.
* Copyright (c) 2013 Linaro Ltd.
* Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#ifndef CLK_ROCKCHIP_CLK_H
diff --git a/drivers/clk/socfpga/Makefile b/drivers/clk/socfpga/Makefile
index 341e6433e560..0a195cbf3f8e 100644
--- a/drivers/clk/socfpga/Makefile
+++ b/drivers/clk/socfpga/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clk.o
obj-$(CONFIG_ARCH_SOCFPGA_ARRIA10) += clk-gate-a10.o clk-periph-a10.o clk-pll-a10.o
diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c
index 07f6026c2e8d..401eb20d243b 100644
--- a/drivers/clk/socfpga/clk-gate-a10.c
+++ b/drivers/clk/socfpga/clk-gate-a10.c
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/socfpga/clk-periph-a10.c b/drivers/clk/socfpga/clk-periph-a10.c
index 9dd7fc9c2552..4ef00052e4f6 100644
--- a/drivers/clk/socfpga/clk-periph-a10.c
+++ b/drivers/clk/socfpga/clk-periph-a10.c
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c
index 4dae3e537bc2..12d6ef6fc327 100644
--- a/drivers/clk/socfpga/clk-pll-a10.c
+++ b/drivers/clk/socfpga/clk-pll-a10.c
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2015 Altera Corporation. All rights reserved
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <io.h>
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index ade608ffe314..1d34b15caf48 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -1,14 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <common.h>
diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h
index cea3fcf5ee9a..9d291f72431a 100644
--- a/drivers/clk/socfpga/clk.h
+++ b/drivers/clk/socfpga/clk.h
@@ -1,17 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2013, Steffen Trumtrar <s.trumtrar@pengutronix.de>
*
* based on drivers/clk/tegra/clk.h
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
*/
#ifndef __SOCFPGA_CLK_H
diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile
index 75569c79fe74..343eb8ab83d4 100644
--- a/drivers/clk/tegra/Makefile
+++ b/drivers/clk/tegra/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clk.o
obj-y += clk-divider.o
obj-y += clk-periph.o
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 0ddd64ecd634..28a1342bbf2c 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index b4182861e787..0cd5200e84b0 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk-pll-out.c b/drivers/clk/tegra/clk-pll-out.c
index 52d8473d6762..e186275563db 100644
--- a/drivers/clk/tegra/clk-pll-out.c
+++ b/drivers/clk/tegra/clk-pll-out.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index e677effba270..3ac49cae4753 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index cec7b5f80318..f5704b83c529 100644
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 2f843bb9ac12..9fccff61368b 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra30.c
index 77f31d213eb0..3d3a7854ffd2 100644
--- a/drivers/clk/tegra/clk-tegra30.c
+++ b/drivers/clk/tegra/clk-tegra30.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2014 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk.c b/drivers/clk/tegra/clk.c
index cb4d92020392..26ff9f258096 100644
--- a/drivers/clk/tegra/clk.c
+++ b/drivers/clk/tegra/clk.c
@@ -1,19 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013-2014 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 10d03573fd0b..5195e6dba4c9 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (C) 2013 Lucas Stach <l.stach@pengutronix.de>
*
* Based on the Linux Tegra clock code
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
/* struct tegra_clk_frac_div - fractional divider */
diff --git a/drivers/clk/vexpress/Makefile b/drivers/clk/vexpress/Makefile
index c6869bac8365..eae11492ec14 100644
--- a/drivers/clk/vexpress/Makefile
+++ b/drivers/clk/vexpress/Makefile
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clk-vexpress-osc.o clk-sp810.o
diff --git a/drivers/clk/vexpress/clk-sp810.c b/drivers/clk/vexpress/clk-sp810.c
index 959661e19e4c..78ec67fd155b 100644
--- a/drivers/clk/vexpress/clk-sp810.c
+++ b/drivers/clk/vexpress/clk-sp810.c
@@ -1,13 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
* Copyright (C) 2013 ARM Limited
*/
diff --git a/drivers/clk/vexpress/clk-vexpress-osc.c b/drivers/clk/vexpress/clk-vexpress-osc.c
index c0d6e6066ecd..6a24fa56c3e1 100644
--- a/drivers/clk/vexpress/clk-vexpress-osc.c
+++ b/drivers/clk/vexpress/clk-vexpress-osc.c
@@ -1,13 +1,4 @@
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
+// SPDX-License-Identifier: GPL-2.0-only
#include <common.h>
#include <malloc.h>
diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile
index 8fedfc77e4dc..a438159ab0a7 100644
--- a/drivers/clk/zynq/Makefile
+++ b/drivers/clk/zynq/Makefile
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clkc.o
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index a6d8ba92cabc..1d9d28ea1460 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2013 Josh Cartwright <joshc@eso.teric.us>
* Copyright (c) 2013 Steffen Trumtrar <s.trumtrar@pengutronix.de>
@@ -7,18 +8,6 @@
* Copyright (c) 2012 National Instruments
*
* Josh Cartwright <josh.cartwright@ni.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <common.h>
#include <init.h>
diff --git a/drivers/clk/zynqmp/Makefile b/drivers/clk/zynqmp/Makefile
index 9432cd398042..70f10bc22b24 100644
--- a/drivers/clk/zynqmp/Makefile
+++ b/drivers/clk/zynqmp/Makefile
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
obj-y += clkc.o
obj-y += clk-pll-zynqmp.o
obj-y += clk-gate-zynqmp.o
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 17f413bbbedf..d02dba1501b7 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
* include/linux/clk/at91_pmc.h
*
@@ -6,11 +7,6 @@
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
#ifndef AT91_PMC_H
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 12/21] clk: at91: fix masterck name
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (10 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 11/21] clk: migrate to SPDX-License-Identifier use Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 13/21] clk: at91: fix possible deadlock Ahmad Fatoum
` (9 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
The master clock is actually named masterck earlier in the driver. Having
"mck" in the parent list means that it can never be selected.
Fixes: 1eabdc2f9dd8 ("clk: at91: add at91sam9x5 PMCs driver")
Fixes: a2038077de9a ("clk: at91: add sama5d2 PMC driver")
Fixes: 084b696bb509 ("clk: at91: add sama5d4 pmc driver")
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: <stable@vger.kernel.org> # v4.20+
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[afa: ported to barebox from Linux commit 65a91e2e597dea]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/at91sam9x5.c | 2 +-
drivers/clk/at91/sama5d2.c | 4 ++--
drivers/clk/at91/sama5d4.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
index 5e0aacfbf653..c01dabe0e814 100644
--- a/drivers/clk/at91/at91sam9x5.c
+++ b/drivers/clk/at91/at91sam9x5.c
@@ -216,7 +216,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
parent_names[1] = "mainck";
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
- parent_names[4] = "mck";
+ parent_names[4] = "masterck";
for (i = 0; i < 2; i++) {
char *name;
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 7627c584ac08..6bc70aed9a3b 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -227,7 +227,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
parent_names[1] = "mainck";
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
- parent_names[4] = "mck";
+ parent_names[4] = "masterck";
for (i = 0; i < 3; i++) {
char *name;
@@ -278,7 +278,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
parent_names[1] = "mainck";
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
- parent_names[4] = "mck";
+ parent_names[4] = "masterck";
for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
hw = at91_clk_register_generated(regmap,
sama5d2_gck[i].n,
diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
index 2fbfca6f8500..d36ca4f85964 100644
--- a/drivers/clk/at91/sama5d4.c
+++ b/drivers/clk/at91/sama5d4.c
@@ -213,7 +213,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
parent_names[1] = "mainck";
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
- parent_names[4] = "mck";
+ parent_names[4] = "masterck";
for (i = 0; i < 3; i++) {
char *name;
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 13/21] clk: at91: fix possible deadlock
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (11 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 12/21] clk: at91: fix masterck name Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 14/21] clk: at91: delete no-longer required DT compat code Ahmad Fatoum
` (8 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
From: Alexandre Belloni <alexandre.belloni@bootlin.com>
Lockdep warns about a possible circular locking dependency because using
syscon_node_to_regmap() will make the created regmap get and enable the
first clock it can parse from the device tree. This clock is not needed to
access the registers and should not be enabled at that time.
Use the recently introduced device_node_to_regmap to solve that as it looks
up the regmap in the same list but doesn't care about the clocks.
Reported-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lkml.kernel.org/r/20191128102531.817549-1-alexandre.belloni@bootlin.com
Tested-by: Michał Mirosław <mirq-linux@rere.qmqm.pl>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[afa: ported to barebox from from Linux commit 6956eb33abb5dea]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/at91sam9260.c | 2 +-
drivers/clk/at91/at91sam9rl.c | 2 +-
drivers/clk/at91/at91sam9x5.c | 2 +-
drivers/clk/at91/pmc.c | 2 +-
drivers/clk/at91/sama5d2.c | 2 +-
drivers/clk/at91/sama5d4.c | 2 +-
6 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
index ac67dcc8f7f0..39135b6c9711 100644
--- a/drivers/clk/at91/at91sam9260.c
+++ b/drivers/clk/at91/at91sam9260.c
@@ -354,7 +354,7 @@ static void __init at91sam926x_pmc_setup(struct device_node *np,
return;
mainxtal_name = of_clk_get_parent_name(np, i);
- regmap = syscon_node_to_regmap(np);
+ regmap = device_node_to_regmap(np);
if (IS_ERR(regmap))
return;
diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
index 82acb38257ba..9be162d63bfe 100644
--- a/drivers/clk/at91/at91sam9rl.c
+++ b/drivers/clk/at91/at91sam9rl.c
@@ -89,7 +89,7 @@ static void __init at91sam9rl_pmc_setup(struct device_node *np)
return;
mainxtal_name = of_clk_get_parent_name(np, i);
- regmap = syscon_node_to_regmap(np);
+ regmap = device_node_to_regmap(np);
if (IS_ERR(regmap))
return;
diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
index c01dabe0e814..db3076967753 100644
--- a/drivers/clk/at91/at91sam9x5.c
+++ b/drivers/clk/at91/at91sam9x5.c
@@ -145,7 +145,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
return;
mainxtal_name = of_clk_get_parent_name(np, i);
- regmap = syscon_node_to_regmap(np);
+ regmap = device_node_to_regmap(np);
if (IS_ERR(regmap))
return;
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 8df3a51f82bf..bea3c89e2c3a 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -269,7 +269,7 @@ static int __init pmc_register_ops(void)
np = of_find_matching_node(NULL, sama5d2_pmc_dt_ids);
- pmcreg = syscon_node_to_regmap(np);
+ pmcreg = device_node_to_regmap(np);
if (IS_ERR(pmcreg))
return PTR_ERR(pmcreg);
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 6bc70aed9a3b..65c4f701bdd9 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -149,7 +149,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
return;
mainxtal_name = of_clk_get_parent_name(np, i);
- regmap = syscon_node_to_regmap(np);
+ regmap = device_node_to_regmap(np);
if (IS_ERR(regmap))
return;
diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
index d36ca4f85964..174bc341c905 100644
--- a/drivers/clk/at91/sama5d4.c
+++ b/drivers/clk/at91/sama5d4.c
@@ -136,7 +136,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
return;
mainxtal_name = of_clk_get_parent_name(np, i);
- regmap = syscon_node_to_regmap(np);
+ regmap = device_node_to_regmap(np);
if (IS_ERR(regmap))
return;
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 14/21] clk: at91: delete no-longer required DT compat code
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (12 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 13/21] clk: at91: fix possible deadlock Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 15/21] clk: at91: compile dt-compat for all platforms that require it Ahmad Fatoum
` (7 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
Unlike Linux, we don't require barebox drivers to support old device
tree bindings. Following device tree compatibles are no longer present
in barebox latest import of dts/:
* atmel,sama5d2-clk-generated
* atmel,sama5d4-clk-h32mx
* atmel,at91sam9g45-clk-pll
* atmel,at91sam9g20-clk-pllb
* atmel,at91sam9260-clk-slow
Drop their compat code.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/dt-compat.c | 133 -----------------------------------
1 file changed, 133 deletions(-)
diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
index beb86230f694..d82137638c4b 100644
--- a/drivers/clk/at91/dt-compat.c
+++ b/drivers/clk/at91/dt-compat.c
@@ -23,96 +23,6 @@
#define SYSTEM_MAX_ID 31
-#ifdef CONFIG_HAVE_AT91_GENERATED_CLK
-#define GENERATED_SOURCE_MAX 6
-
-#define GCK_ID_I2S0 54
-#define GCK_ID_I2S1 55
-#define GCK_ID_CLASSD 59
-
-static void __init of_sama5d2_clk_generated_setup(struct device_node *np)
-{
- int num;
- u32 id;
- const char *name;
- struct clk *hw;
- unsigned int num_parents;
- const char *parent_names[GENERATED_SOURCE_MAX];
- struct device_node *gcknp;
- struct clk_range range = CLK_RANGE(0, 0);
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > GENERATED_SOURCE_MAX)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
-
- num = of_get_child_count(np);
- if (!num || num > PERIPHERAL_MAX)
- return;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- for_each_child_of_node(np, gcknp) {
- bool pll_audio = false;
-
- if (of_property_read_u32(gcknp, "reg", &id))
- continue;
-
- if (id < PERIPHERAL_ID_MIN || id >= PERIPHERAL_MAX)
- continue;
-
- if (of_property_read_string(np, "clock-output-names", &name))
- name = gcknp->name;
-
- of_at91_get_clk_range(gcknp, "atmel,clk-output-range",
- &range);
-
- if (of_device_is_compatible(np, "atmel,sama5d2-clk-generated") &&
- (id == GCK_ID_I2S0 || id == GCK_ID_I2S1 ||
- id == GCK_ID_CLASSD))
- pll_audio = true;
-
- hw = at91_clk_register_generated(regmap, name,
- parent_names, num_parents,
- id, pll_audio, &range);
- if (IS_ERR(hw))
- continue;
-
- of_clk_add_provider(gcknp, of_clk_src_simple_get, hw);
- }
-}
-CLK_OF_DECLARE(of_sama5d2_clk_generated_setup, "atmel,sama5d2-clk-generated",
- of_sama5d2_clk_generated_setup);
-#endif /* CONFIG_HAVE_AT91_GENERATED_CLK */
-
-#ifdef CONFIG_HAVE_AT91_H32MX
-static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
-{
- struct clk *hw;
- const char *name = np->name;
- const char *parent_name;
- struct regmap *regmap;
-
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- parent_name = of_clk_get_parent_name(np, 0);
-
- hw = at91_clk_register_h32mx(regmap, name, parent_name);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_provider(np, of_clk_src_simple_get, hw);
-}
-CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
- of_sama5d4_clk_h32mx_setup);
-#endif /* CONFIG_HAVE_AT91_H32MX */
-
static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
{
struct clk *hw;
@@ -505,20 +415,6 @@ static void __init of_at91rm9200_clk_pll_setup(struct device_node *np)
CLK_OF_DECLARE(at91rm9200_clk_pll, "atmel,at91rm9200-clk-pll",
of_at91rm9200_clk_pll_setup);
-static void __init of_at91sam9g45_clk_pll_setup(struct device_node *np)
-{
- of_at91_clk_pll_setup(np, &at91sam9g45_pll_layout);
-}
-CLK_OF_DECLARE(at91sam9g45_clk_pll, "atmel,at91sam9g45-clk-pll",
- of_at91sam9g45_clk_pll_setup);
-
-static void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np)
-{
- of_at91_clk_pll_setup(np, &at91sam9g20_pllb_layout);
-}
-CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
- of_at91sam9g20_clk_pllb_setup);
-
static void __init of_sama5d3_clk_pll_setup(struct device_node *np)
{
of_at91_clk_pll_setup(np, &sama5d3_pll_layout);
@@ -616,35 +512,6 @@ static void __init of_at91sam9x5_clk_prog_setup(struct device_node *np)
CLK_OF_DECLARE(at91sam9x5_clk_prog, "atmel,at91sam9x5-clk-programmable",
of_at91sam9x5_clk_prog_setup);
-static void __init of_at91sam9260_clk_slow_setup(struct device_node *np)
-{
- struct clk *hw;
- const char *parent_names[2];
- unsigned int num_parents;
- const char *name = np->name;
- struct regmap *regmap;
-
- num_parents = of_clk_get_parent_count(np);
- if (num_parents != 2)
- return;
-
- of_clk_parent_fill(np, parent_names, num_parents);
- regmap = syscon_node_to_regmap(of_get_parent(np));
- if (IS_ERR(regmap))
- return;
-
- of_property_read_string(np, "clock-output-names", &name);
-
- hw = at91_clk_register_sam9260_slow(regmap, name, parent_names,
- num_parents);
- if (IS_ERR(hw))
- return;
-
- of_clk_add_provider(np, of_clk_src_simple_get, hw);
-}
-CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
- of_at91sam9260_clk_slow_setup);
-
#ifdef CONFIG_HAVE_AT91_SMD
#define SMD_SOURCE_MAX 2
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 15/21] clk: at91: compile dt-compat for all platforms that require it
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (13 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 14/21] clk: at91: delete no-longer required DT compat code Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 16/21] clk: at91: add __init marker where appropriate Ahmad Fatoum
` (6 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
We have so far compiled in dt-compat only for CONFIG_SOC_SAMA5D3,
but we require it for device tree support of CONFIG_SOC_AT91SAM9
as well. Fix this.
While at it move around the obj- rules a bit to minimize the diff to
upstream.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/Makefile | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 593d34e3487e..d07baedf580c 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -12,9 +12,7 @@ obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
-obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o
-obj-$(CONFIG_SOC_AT91SAM9) += at91sam9rl.o
-obj-$(CONFIG_SOC_AT91SAM9) += at91sam9x5.o
-obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
-obj-$(CONFIG_SOC_SAMA5D3) += dt-compat.o
-obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
+obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.o
+obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
+obj-$(CONFIG_SOC_SAMA5D3) += dt-compat.o
+obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 16/21] clk: at91: add __init marker where appropriate
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (14 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 15/21] clk: at91: compile dt-compat for all platforms that require it Ahmad Fatoum
@ 2020-04-13 7:51 ` Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 17/21] clk: at91: Mark struct clk_range as const Ahmad Fatoum
` (5 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:51 UTC (permalink / raw)
To: barebox
While redundant in barebox, it makes our diff to the upstream driver
smaller when synchronizing, so add it back.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/clk-h32mx.c | 2 +-
drivers/clk/at91/clk-main.c | 8 +++---
drivers/clk/at91/clk-master.c | 2 +-
drivers/clk/at91/clk-peripheral.c | 4 +--
drivers/clk/at91/clk-pll.c | 2 +-
drivers/clk/at91/clk-plldiv.c | 2 +-
drivers/clk/at91/clk-programmable.c | 2 +-
drivers/clk/at91/clk-smd.c | 2 +-
drivers/clk/at91/clk-system.c | 2 +-
drivers/clk/at91/clk-usb.c | 6 ++---
drivers/clk/at91/pmc.h | 38 ++++++++++++++---------------
drivers/clk/at91/sckc.c | 6 ++---
12 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
index fcca37cb52c4..6052886cca45 100644
--- a/drivers/clk/at91/clk-h32mx.c
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -83,7 +83,7 @@ static const struct clk_ops h32mx_ops = {
.set_rate = clk_sama5d4_h32mx_set_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_h32mx(struct regmap *regmap, const char *name,
const char *parent_name)
{
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index cd61a35c69fd..46bb47914960 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -123,7 +123,7 @@ static const struct clk_ops main_osc_ops = {
.is_enabled = clk_main_osc_is_enabled,
};
-struct clk *
+struct clk * __init
at91_clk_register_main_osc(struct regmap *regmap,
const char *name,
const char *parent_name,
@@ -229,7 +229,7 @@ static const struct clk_ops main_rc_osc_ops = {
.recalc_rate = clk_main_rc_osc_recalc_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_main_rc_osc(struct regmap *regmap,
const char *name,
u32 frequency, u32 accuracy)
@@ -320,7 +320,7 @@ static const struct clk_ops rm9200_main_ops = {
.recalc_rate = clk_rm9200_main_recalc_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_rm9200_main(struct regmap *regmap,
const char *name,
const char *parent_name)
@@ -428,7 +428,7 @@ static const struct clk_ops sam9x5_main_ops = {
.get_parent = clk_sam9x5_main_get_parent,
};
-struct clk *
+struct clk * __init
at91_clk_register_sam9x5_main(struct regmap *regmap,
const char *name,
const char **parent_names,
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 6bd733ef4194..766502fd7a3d 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -105,7 +105,7 @@ static const struct clk_ops master_ops = {
.get_parent = clk_master_get_parent,
};
-struct clk *
+struct clk * __init
at91_clk_register_master(struct regmap *regmap,
const char *name, int num_parents,
const char **parent_names,
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 9c3791dc5242..21d58b4a34fd 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -94,7 +94,7 @@ static const struct clk_ops peripheral_ops = {
.is_enabled = clk_peripheral_is_enabled,
};
-struct clk *
+struct clk * __init
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
const char *parent_name, u32 id)
{
@@ -306,7 +306,7 @@ static const struct clk_ops sam9x5_peripheral_ops = {
.set_rate = clk_sam9x5_peripheral_set_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_sam9x5_peripheral(struct regmap *regmap,
const char *name, const char *parent_name,
u32 id, const struct clk_range *range)
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index acf2fae50ea9..d3c4ab6f7a26 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -280,7 +280,7 @@ static const struct clk_ops pll_ops = {
.set_rate = clk_pll_set_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_pll(struct regmap *regmap, const char *name,
const char *parent_name, u8 id,
const struct clk_pll_layout *layout,
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
index 5a9686dc7856..1cbb61bb2c3c 100644
--- a/drivers/clk/at91/clk-plldiv.c
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -73,7 +73,7 @@ static const struct clk_ops plldiv_ops = {
.set_rate = clk_plldiv_set_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_plldiv(struct regmap *regmap, const char *name,
const char *parent_name)
{
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index e002c8af47f7..09bd8bc5306e 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -118,7 +118,7 @@ static const struct clk_ops programmable_ops = {
.set_rate = clk_programmable_set_rate,
};
-struct clk *
+struct clk * __init
at91_clk_register_programmable(struct regmap *regmap,
const char *name, const char **parent_names,
u8 num_parents, u8 id,
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index 4a541322d459..0027ebc8bb6b 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -109,7 +109,7 @@ static const struct clk_ops at91sam9x5_smd_ops = {
.set_rate = at91sam9x5_clk_smd_set_rate,
};
-struct clk *
+struct clk * __init
at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents)
{
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
index a8f30539400e..77f0dff98b35 100644
--- a/drivers/clk/at91/clk-system.c
+++ b/drivers/clk/at91/clk-system.c
@@ -85,7 +85,7 @@ static const struct clk_ops system_ops = {
.is_enabled = clk_system_is_enabled,
};
-struct clk *
+struct clk * __init
at91_clk_register_system(struct regmap *regmap, const char *name,
const char *parent_name, u8 id)
{
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index 334bd5c88ee7..da37f8ea3783 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -138,7 +138,7 @@ static const struct clk_ops at91sam9n12_usb_ops = {
.set_rate = at91sam9x5_clk_usb_set_rate,
};
-struct clk *
+struct clk * __init
at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents)
{
@@ -166,7 +166,7 @@ at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
return &usb->clk;
}
-struct clk *
+struct clk * __init
at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name)
{
@@ -276,7 +276,7 @@ static const struct clk_ops at91rm9200_usb_ops = {
.set_rate = at91rm9200_clk_usb_set_rate,
};
-struct clk *
+struct clk * __init
at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name, const u32 *divisors)
{
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index c4de1e802e4e..67890300c750 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -84,83 +84,83 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname,
struct clk *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
-struct clk *
+struct clk * __init
at91_clk_register_generated(struct regmap *regmap,
const char *name, const char **parent_names,
u8 num_parents, u8 id, bool pll_audio,
const struct clk_range *range);
-struct clk *
+struct clk * __init
at91_clk_register_h32mx(struct regmap *regmap, const char *name,
const char *parent_name);
-struct clk *
+struct clk * __init
at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
u32 frequency, u32 accuracy);
-struct clk *
+struct clk * __init
at91_clk_register_main_osc(struct regmap *regmap, const char *name,
const char *parent_name, bool bypass);
-struct clk *
+struct clk * __init
at91_clk_register_rm9200_main(struct regmap *regmap,
const char *name,
const char *parent_name);
-struct clk *
+struct clk * __init
at91_clk_register_sam9x5_main(struct regmap *regmap, const char *name,
const char **parent_names, int num_parents);
-struct clk *
+struct clk * __init
at91_clk_register_master(struct regmap *regmap, const char *name,
int num_parents, const char **parent_names,
const struct clk_master_layout *layout,
const struct clk_master_characteristics *characteristics);
-struct clk *
+struct clk * __init
at91_clk_register_peripheral(struct regmap *regmap, const char *name,
const char *parent_name, u32 id);
-struct clk *
+struct clk * __init
at91_clk_register_sam9x5_peripheral(struct regmap *regmap,
const char *name, const char *parent_name,
u32 id, const struct clk_range *range);
-struct clk *
+struct clk * __init
at91_clk_register_pll(struct regmap *regmap, const char *name,
const char *parent_name, u8 id,
const struct clk_pll_layout *layout,
const struct clk_pll_characteristics *characteristics);
-struct clk *
+struct clk * __init
at91_clk_register_plldiv(struct regmap *regmap, const char *name,
const char *parent_name);
-struct clk *
+struct clk * __init
at91_clk_register_programmable(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents, u8 id,
const struct clk_programmable_layout *layout);
-struct clk *
+struct clk * __init
at91_clk_register_sam9260_slow(struct regmap *regmap,
const char *name,
const char **parent_names,
int num_parents);
-struct clk *
+struct clk * __init
at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents);
-struct clk *
+struct clk * __init
at91_clk_register_system(struct regmap *regmap, const char *name,
const char *parent_name, u8 id);
-struct clk *
+struct clk * __init
at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents);
-struct clk *
+struct clk * __init
at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name);
-struct clk *
+struct clk * __init
at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name, const u32 *divisors);
-struct clk *
+struct clk * __init
at91_clk_register_utmi(struct regmap *regmap_pmc, struct regmap *regmap_sfr,
const char *name, const char *parent_name);
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 4a03819f0e30..7998d6a50986 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -113,7 +113,7 @@ static const struct clk_ops slow_osc_ops = {
.is_enabled = clk_slow_osc_is_enabled,
};
-static struct clk *
+static struct clk * __init
at91_clk_register_slow_osc(void __iomem *sckcr,
const char *name,
const char *parent_name,
@@ -214,7 +214,7 @@ static const struct clk_ops slow_rc_osc_ops = {
.recalc_rate = clk_slow_rc_osc_recalc_rate,
};
-static struct clk *
+static struct clk * __init
at91_clk_register_slow_rc_osc(void __iomem *sckcr,
const char *name,
unsigned long frequency,
@@ -304,7 +304,7 @@ static const struct clk_ops sam9x5_slow_ops = {
.get_parent = clk_sam9x5_slow_get_parent,
};
-static struct clk *
+static struct clk * __init
at91_clk_register_sam9x5_slow(void __iomem *sckcr,
const char *name,
const char **parent_names,
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 17/21] clk: at91: Mark struct clk_range as const
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (15 preceding siblings ...)
2020-04-13 7:51 ` [PATCH 16/21] clk: at91: add __init marker where appropriate Ahmad Fatoum
@ 2020-04-13 7:52 ` Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 18/21] clk: at91: allow 24 Mhz clock as input for PLL Ahmad Fatoum
` (4 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:52 UTC (permalink / raw)
To: barebox
From: Stephen Boyd <sboyd@kernel.org>
It's just some static data that doesn't get changed after being used.
Mark it const everywhere.
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[afa: ported to barebox from Linux commit 7b4c162e03d47e0]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/at91sam9260.c | 14 +++++++-------
drivers/clk/at91/at91sam9rl.c | 2 +-
drivers/clk/at91/at91sam9x5.c | 2 +-
drivers/clk/at91/pmc.h | 2 +-
drivers/clk/at91/sama5d2.c | 2 +-
drivers/clk/at91/sama5d4.c | 2 +-
6 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/at91/at91sam9260.c b/drivers/clk/at91/at91sam9260.c
index 39135b6c9711..066dedf2a146 100644
--- a/drivers/clk/at91/at91sam9260.c
+++ b/drivers/clk/at91/at91sam9260.c
@@ -47,7 +47,7 @@ static u8 sam9260_plla_out[] = { 0, 2 };
static u16 sam9260_plla_icpll[] = { 1, 1 };
-static struct clk_range sam9260_plla_outputs[] = {
+static const struct clk_range sam9260_plla_outputs[] = {
{ .min = 80000000, .max = 160000000 },
{ .min = 150000000, .max = 240000000 },
};
@@ -64,7 +64,7 @@ static u8 sam9260_pllb_out[] = { 1 };
static u16 sam9260_pllb_icpll[] = { 1 };
-static struct clk_range sam9260_pllb_outputs[] = {
+static const struct clk_range sam9260_pllb_outputs[] = {
{ .min = 70000000, .max = 130000000 },
};
@@ -134,7 +134,7 @@ static u8 sam9g20_plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
static u16 sam9g20_plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
-static struct clk_range sam9g20_plla_outputs[] = {
+static const struct clk_range sam9g20_plla_outputs[] = {
{ .min = 745000000, .max = 800000000 },
{ .min = 695000000, .max = 750000000 },
{ .min = 645000000, .max = 700000000 },
@@ -157,7 +157,7 @@ static u8 sam9g20_pllb_out[] = { 0 };
static u16 sam9g20_pllb_icpll[] = { 0 };
-static struct clk_range sam9g20_pllb_outputs[] = {
+static const struct clk_range sam9g20_pllb_outputs[] = {
{ .min = 30000000, .max = 100000000 },
};
@@ -188,7 +188,7 @@ static const struct clk_master_characteristics sam9261_mck_characteristics = {
.divisors = { 1, 2, 4, 0 },
};
-static struct clk_range sam9261_plla_outputs[] = {
+static const struct clk_range sam9261_plla_outputs[] = {
{ .min = 80000000, .max = 200000000 },
{ .min = 190000000, .max = 240000000 },
};
@@ -205,7 +205,7 @@ static u8 sam9261_pllb_out[] = { 1 };
static u16 sam9261_pllb_icpll[] = { 1 };
-static struct clk_range sam9261_pllb_outputs[] = {
+static const struct clk_range sam9261_pllb_outputs[] = {
{ .min = 70000000, .max = 130000000 },
};
@@ -268,7 +268,7 @@ static const struct clk_master_characteristics sam9263_mck_characteristics = {
.divisors = { 1, 2, 4, 0 },
};
-static struct clk_range sam9263_pll_outputs[] = {
+static const struct clk_range sam9263_pll_outputs[] = {
{ .min = 80000000, .max = 200000000 },
{ .min = 190000000, .max = 240000000 },
};
diff --git a/drivers/clk/at91/at91sam9rl.c b/drivers/clk/at91/at91sam9rl.c
index 9be162d63bfe..ff47f94a8df0 100644
--- a/drivers/clk/at91/at91sam9rl.c
+++ b/drivers/clk/at91/at91sam9rl.c
@@ -20,7 +20,7 @@ static const struct clk_master_characteristics sam9rl_mck_characteristics = {
static u8 sam9rl_plla_out[] = { 0, 2 };
-static struct clk_range sam9rl_plla_outputs[] = {
+static const struct clk_range sam9rl_plla_outputs[] = {
{ .min = 80000000, .max = 200000000 },
{ .min = 190000000, .max = 240000000 },
};
diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
index db3076967753..87b0fd2e1cad 100644
--- a/drivers/clk/at91/at91sam9x5.c
+++ b/drivers/clk/at91/at91sam9x5.c
@@ -23,7 +23,7 @@ static u8 plla_out[] = { 0, 1, 2, 3, 0, 1, 2, 3 };
static u16 plla_icpll[] = { 0, 0, 0, 0, 1, 1, 1, 1 };
-static struct clk_range plla_outputs[] = {
+static const struct clk_range plla_outputs[] = {
{ .min = 745000000, .max = 800000000 },
{ .min = 695000000, .max = 750000000 },
{ .min = 645000000, .max = 700000000 },
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 67890300c750..705486a1f440 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -58,7 +58,7 @@ extern const struct clk_pll_layout sama5d3_pll_layout;
struct clk_pll_characteristics {
struct clk_range input;
int num_output;
- struct clk_range *output;
+ const struct clk_range *output;
u16 *icpll;
u8 *out;
};
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 65c4f701bdd9..3daff89f5958 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -22,7 +22,7 @@ static u8 plla_out[] = { 0 };
static u16 plla_icpll[] = { 0 };
-static struct clk_range plla_outputs[] = {
+static const struct clk_range plla_outputs[] = {
{ .min = 600000000, .max = 1200000000 },
};
diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
index 174bc341c905..de14640f91d2 100644
--- a/drivers/clk/at91/sama5d4.c
+++ b/drivers/clk/at91/sama5d4.c
@@ -22,7 +22,7 @@ static u8 plla_out[] = { 0 };
static u16 plla_icpll[] = { 0 };
-static struct clk_range plla_outputs[] = {
+static const struct clk_range plla_outputs[] = {
{ .min = 600000000, .max = 1200000000 },
};
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 18/21] clk: at91: allow 24 Mhz clock as input for PLL
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (16 preceding siblings ...)
2020-04-13 7:52 ` [PATCH 17/21] clk: at91: Mark struct clk_range as const Ahmad Fatoum
@ 2020-04-13 7:52 ` Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 19/21] clk: at91: add sama5d2 audio PLL support Ahmad Fatoum
` (3 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:52 UTC (permalink / raw)
To: barebox
From: Eugen Hristev <eugen.hristev@microchip.com>
The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
[afa: ported to barebox from Linux commit 81a6b601f9f49]
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/sama5d2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 3daff89f5958..61fdf256c036 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -27,7 +27,7 @@ static const struct clk_range plla_outputs[] = {
};
static const struct clk_pll_characteristics plla_characteristics = {
- .input = { .min = 12000000, .max = 12000000 },
+ .input = { .min = 12000000, .max = 24000000 },
.num_output = ARRAY_SIZE(plla_outputs),
.output = plla_outputs,
.icpll = plla_icpll,
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 19/21] clk: at91: add sama5d2 audio PLL support
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (17 preceding siblings ...)
2020-04-13 7:52 ` [PATCH 18/21] clk: at91: allow 24 Mhz clock as input for PLL Ahmad Fatoum
@ 2020-04-13 7:52 ` Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 20/21] clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock support Ahmad Fatoum
` (2 subsequent siblings)
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:52 UTC (permalink / raw)
To: barebox
Commit 7310b976 ("clk: at91: fix compilation errors in sama5d2.c") and
follow-up commit ca3077068c ("clk: at91: delete dead i2s/audio code")
had deleted the i2s/audio clock related parts of the upstream driver.
This was mostly due to unwillingness on my part to understand the code
enough for porting them and because I deemed them unnecessary to support
in barebox. The former has changed and the latter is not totally true as
audio PLL derived clocks may be muxed as inputs for programmable and
generated clocks.
Port them over and mimize the diff to upstream.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Kconfig | 8 +
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/clk-audio-pll.c | 512 +++++++++++++++++++++++++++++++
drivers/clk/at91/clk-generated.c | 5 +-
drivers/clk/at91/clk-i2s-mux.c | 87 ++++++
drivers/clk/at91/pmc.c | 2 +
drivers/clk/at91/pmc.h | 17 +
drivers/clk/at91/sama5d2.c | 49 ++-
include/linux/clk/at91_pmc.h | 25 ++
9 files changed, 702 insertions(+), 5 deletions(-)
create mode 100644 drivers/clk/at91/clk-audio-pll.c
create mode 100644 drivers/clk/at91/clk-i2s-mux.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index eb14cd2c28da..022635381009 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -34,6 +34,12 @@ config HAVE_AT91_GENERATED_CLK
config HAVE_AT91_BOOTSTRAP
bool
+config HAVE_AT91_AUDIO_PLL
+ bool
+
+config HAVE_AT91_I2S_MUX_CLK
+ bool
+
# Select if board uses the common at91sam926x_board_init
config AT91SAM926X_BOARD_INIT
bool
@@ -71,6 +77,8 @@ config SOC_SAMA5D2
select HAVE_AT91_USB_CLK
select HAVE_AT91_GENERATED_CLK
select PINCTRL
+ select HAVE_AT91_AUDIO_PLL
+ select HAVE_AT91_I2S_MUX_CLK
select PINCTRL_AT91PIO4
select HAS_MACB
select HAVE_MACH_ARM_HEAD
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index d07baedf580c..605f698439d0 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -7,11 +7,13 @@ obj-y += pmc.o sckc.o
obj-y += clk-slow.o clk-main.o clk-pll.o clk-plldiv.o clk-master.o
obj-y += clk-system.o clk-peripheral.o clk-programmable.o
+obj-$(CONFIG_HAVE_AT91_AUDIO_PLL) += clk-audio-pll.o
obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
+obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_SOC_SAMA5D3) += dt-compat.o
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
new file mode 100644
index 000000000000..47bff32fe83b
--- /dev/null
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -0,0 +1,512 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 Atmel Corporation,
+ * Songjun Wu <songjun.wu@atmel.com>,
+ * Nicolas Ferre <nicolas.ferre@atmel.com>
+ * Copyright (C) 2017 Free Electrons,
+ * Quentin Schulz <quentin.schulz@free-electrons.com>
+ *
+ * The Sama5d2 SoC has two audio PLLs (PMC and PAD) that shares the same parent
+ * (FRAC). FRAC can output between 620 and 700MHz and only multiply the rate of
+ * its own parent. PMC and PAD can then divide the FRAC rate to best match the
+ * asked rate.
+ *
+ * Traits of FRAC clock:
+ * enable - clk_enable writes nd, fracr parameters and enables PLL
+ * rate - rate is adjustable.
+ * clk->rate = parent->rate * ((nd + 1) + (fracr / 2^22))
+ * parent - fixed parent. No clk_set_parent support
+ *
+ * Traits of PMC clock:
+ * enable - clk_enable writes qdpmc, and enables PMC output
+ * rate - rate is adjustable.
+ * clk->rate = parent->rate / (qdpmc + 1)
+ * parent - fixed parent. No clk_set_parent support
+ *
+ * Traits of PAD clock:
+ * enable - clk_enable writes divisors and enables PAD output
+ * rate - rate is adjustable.
+ * clk->rate = parent->rate / (qdaudio * div))
+ * parent - fixed parent. No clk_set_parent support
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <of.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/clk/at91_pmc.h>
+#include <mfd/syscon.h>
+#include <regmap.h>
+
+#include "pmc.h"
+
+#define AUDIO_PLL_DIV_FRAC BIT(22)
+#define AUDIO_PLL_ND_MAX (AT91_PMC_AUDIO_PLL_ND_MASK >> \
+ AT91_PMC_AUDIO_PLL_ND_OFFSET)
+
+#define AUDIO_PLL_QDPAD(qd, div) ((AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(qd) & \
+ AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK) | \
+ (AT91_PMC_AUDIO_PLL_QDPAD_DIV(div) & \
+ AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK))
+
+#define AUDIO_PLL_QDPMC_MAX (AT91_PMC_AUDIO_PLL_QDPMC_MASK >> \
+ AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+
+#define AUDIO_PLL_FOUT_MIN 620000000UL
+#define AUDIO_PLL_FOUT_MAX 700000000UL
+
+struct clk_audio_frac {
+ struct clk clk;
+ struct regmap *regmap;
+ u32 fracr;
+ u8 nd;
+ const char *parent_name;
+};
+
+struct clk_audio_pad {
+ struct clk clk;
+ struct regmap *regmap;
+ u8 qdaudio;
+ u8 div;
+ const char *parent_name;
+};
+
+struct clk_audio_pmc {
+ struct clk clk;
+ struct regmap *regmap;
+ u8 qdpmc;
+ const char *parent_name;
+};
+
+#define to_clk_audio_frac(clk) container_of(clk, struct clk_audio_frac, clk)
+#define to_clk_audio_pad(clk) container_of(clk, struct clk_audio_pad, clk)
+#define to_clk_audio_pmc(clk) container_of(clk, struct clk_audio_pmc, clk)
+
+static int clk_audio_pll_frac_enable(struct clk *clk)
+{
+ struct clk_audio_frac *frac = to_clk_audio_frac(clk);
+
+ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_RESETN, 0);
+ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_RESETN,
+ AT91_PMC_AUDIO_PLL_RESETN);
+ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL1,
+ AT91_PMC_AUDIO_PLL_FRACR_MASK, frac->fracr);
+
+ /*
+ * reset and enable have to be done in 2 separated writes
+ * for AT91_PMC_AUDIO_PLL0
+ */
+ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_PLLEN |
+ AT91_PMC_AUDIO_PLL_ND_MASK,
+ AT91_PMC_AUDIO_PLL_PLLEN |
+ AT91_PMC_AUDIO_PLL_ND(frac->nd));
+
+ return 0;
+}
+
+static int clk_audio_pll_pad_enable(struct clk *clk)
+{
+ struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk);
+
+ regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL1,
+ AT91_PMC_AUDIO_PLL_QDPAD_MASK,
+ AUDIO_PLL_QDPAD(apad_ck->qdaudio, apad_ck->div));
+ regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_PADEN, AT91_PMC_AUDIO_PLL_PADEN);
+
+ return 0;
+}
+
+static int clk_audio_pll_pmc_enable(struct clk *clk)
+{
+ struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk);
+
+ regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_PMCEN |
+ AT91_PMC_AUDIO_PLL_QDPMC_MASK,
+ AT91_PMC_AUDIO_PLL_PMCEN |
+ AT91_PMC_AUDIO_PLL_QDPMC(apmc_ck->qdpmc));
+ return 0;
+}
+
+static void clk_audio_pll_frac_disable(struct clk *clk)
+{
+ struct clk_audio_frac *frac = to_clk_audio_frac(clk);
+
+ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_PLLEN, 0);
+ /* do it in 2 separated writes */
+ regmap_update_bits(frac->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_RESETN, 0);
+}
+
+static void clk_audio_pll_pad_disable(struct clk *clk)
+{
+ struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk);
+
+ regmap_update_bits(apad_ck->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_PADEN, 0);
+}
+
+static void clk_audio_pll_pmc_disable(struct clk *clk)
+{
+ struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk);
+
+ regmap_update_bits(apmc_ck->regmap, AT91_PMC_AUDIO_PLL0,
+ AT91_PMC_AUDIO_PLL_PMCEN, 0);
+}
+
+static unsigned long clk_audio_pll_fout(unsigned long parent_rate,
+ unsigned long nd, unsigned long fracr)
+{
+ unsigned long long fr = (unsigned long long)parent_rate * fracr;
+
+ pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
+
+ fr = DIV_ROUND_CLOSEST_ULL(fr, AUDIO_PLL_DIV_FRAC);
+
+ pr_debug("A PLL: %s, fr = %llu\n", __func__, fr);
+
+ return parent_rate * (nd + 1) + fr;
+}
+
+static unsigned long clk_audio_pll_frac_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_audio_frac *frac = to_clk_audio_frac(clk);
+ unsigned long fout;
+
+ fout = clk_audio_pll_fout(parent_rate, frac->nd, frac->fracr);
+
+ pr_debug("A PLL: %s, fout = %lu (nd = %u, fracr = %lu)\n", __func__,
+ fout, frac->nd, (unsigned long)frac->fracr);
+
+ return fout;
+}
+
+static unsigned long clk_audio_pll_pad_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk);
+ unsigned long apad_rate = 0;
+
+ if (apad_ck->qdaudio && apad_ck->div)
+ apad_rate = parent_rate / (apad_ck->qdaudio * apad_ck->div);
+
+ pr_debug("A PLL/PAD: %s, apad_rate = %lu (div = %u, qdaudio = %u)\n",
+ __func__, apad_rate, apad_ck->div, apad_ck->qdaudio);
+
+ return apad_rate;
+}
+
+static unsigned long clk_audio_pll_pmc_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk);
+ unsigned long apmc_rate = 0;
+
+ apmc_rate = parent_rate / (apmc_ck->qdpmc + 1);
+
+ pr_debug("A PLL/PMC: %s, apmc_rate = %lu (qdpmc = %u)\n", __func__,
+ apmc_rate, apmc_ck->qdpmc);
+
+ return apmc_rate;
+}
+
+static int clk_audio_pll_frac_compute_frac(unsigned long rate,
+ unsigned long parent_rate,
+ unsigned long *nd,
+ unsigned long *fracr)
+{
+ unsigned long long tmp, rem;
+
+ if (!rate)
+ return -EINVAL;
+
+ tmp = rate;
+ rem = do_div(tmp, parent_rate);
+ if (!tmp || tmp >= AUDIO_PLL_ND_MAX)
+ return -EINVAL;
+
+ *nd = tmp - 1;
+
+ tmp = rem * AUDIO_PLL_DIV_FRAC;
+ tmp = DIV_ROUND_CLOSEST_ULL(tmp, parent_rate);
+ if (tmp > AT91_PMC_AUDIO_PLL_FRACR_MASK)
+ return -EINVAL;
+
+ /* we can cast here as we verified the bounds just above */
+ *fracr = (unsigned long)tmp;
+
+ return 0;
+}
+
+static long clk_audio_pll_pad_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk *pclk = clk_get_parent(clk);
+ long best_rate = -EINVAL;
+ unsigned long best_parent_rate;
+ unsigned long tmp_qd;
+ u32 div;
+ long tmp_rate;
+ int tmp_diff;
+ int best_diff = -1;
+
+ pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+ rate, *parent_rate);
+
+ /*
+ * Rate divisor is actually made of two different divisors, multiplied
+ * between themselves before dividing the rate.
+ * tmp_qd goes from 1 to 31 and div is either 2 or 3.
+ * In order to avoid testing twice the rate divisor (e.g. divisor 12 can
+ * be found with (tmp_qd, div) = (2, 6) or (3, 4)), we remove any loop
+ * for a rate divisor when div is 2 and tmp_qd is a multiple of 3.
+ * We cannot inverse it (condition div is 3 and tmp_qd is even) or we
+ * would miss some rate divisor that aren't reachable with div being 2
+ * (e.g. rate divisor 90 is made with div = 3 and tmp_qd = 30, thus
+ * tmp_qd is even so we skip it because we think div 2 could make this
+ * rate divisor which isn't possible since tmp_qd has to be <= 31).
+ */
+ for (tmp_qd = 1; tmp_qd < AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX; tmp_qd++)
+ for (div = 2; div <= 3; div++) {
+ if (div == 2 && tmp_qd % 3 == 0)
+ continue;
+
+ best_parent_rate = clk_round_rate(pclk,
+ rate * tmp_qd * div);
+ tmp_rate = best_parent_rate / (div * tmp_qd);
+ tmp_diff = abs(rate - tmp_rate);
+
+ if (best_diff < 0 || best_diff > tmp_diff) {
+ *parent_rate = best_parent_rate;
+ best_rate = tmp_rate;
+ best_diff = tmp_diff;
+ }
+ }
+
+ pr_debug("A PLL/PAD: %s, best_rate = %ld, best_parent_rate = %lu\n",
+ __func__, best_rate, best_parent_rate);
+
+ return best_rate;
+}
+
+static long clk_audio_pll_pmc_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct clk *pclk = clk_get_parent(clk);
+ long best_rate = -EINVAL;
+ unsigned long best_parent_rate = 0;
+ u32 tmp_qd = 0, div;
+ long tmp_rate;
+ int tmp_diff;
+ int best_diff = -1;
+
+ pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+ rate, *parent_rate);
+
+ if (!rate)
+ return 0;
+
+ best_parent_rate = clk_round_rate(pclk, 1);
+ div = max(best_parent_rate / rate, 1UL);
+ for (; div <= AUDIO_PLL_QDPMC_MAX; div++) {
+ best_parent_rate = clk_round_rate(pclk, rate * div);
+ tmp_rate = best_parent_rate / div;
+ tmp_diff = abs(rate - tmp_rate);
+
+ if (best_diff < 0 || best_diff > tmp_diff) {
+ *parent_rate = best_parent_rate;
+ best_rate = tmp_rate;
+ best_diff = tmp_diff;
+ tmp_qd = div;
+ if (!best_diff)
+ break; /* got exact match */
+ }
+ }
+
+ pr_debug("A PLL/PMC: %s, best_rate = %ld, best_parent_rate = %lu (qd = %d)\n",
+ __func__, best_rate, *parent_rate, tmp_qd - 1);
+
+ return best_rate;
+}
+
+static int clk_audio_pll_frac_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_audio_frac *frac = to_clk_audio_frac(clk);
+ unsigned long fracr, nd;
+ int ret;
+
+ pr_debug("A PLL: %s, rate = %lu (parent_rate = %lu)\n", __func__, rate,
+ parent_rate);
+
+ if (rate < AUDIO_PLL_FOUT_MIN || rate > AUDIO_PLL_FOUT_MAX)
+ return -EINVAL;
+
+ ret = clk_audio_pll_frac_compute_frac(rate, parent_rate, &nd, &fracr);
+ if (ret)
+ return ret;
+
+ frac->nd = nd;
+ frac->fracr = fracr;
+
+ return 0;
+}
+
+static int clk_audio_pll_pad_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_audio_pad *apad_ck = to_clk_audio_pad(clk);
+ u8 tmp_div;
+
+ pr_debug("A PLL/PAD: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+ rate, parent_rate);
+
+ if (!rate)
+ return -EINVAL;
+
+ tmp_div = parent_rate / rate;
+ if (tmp_div % 3 == 0) {
+ apad_ck->qdaudio = tmp_div / 3;
+ apad_ck->div = 3;
+ } else {
+ apad_ck->qdaudio = tmp_div / 2;
+ apad_ck->div = 2;
+ }
+
+ return 0;
+}
+
+static int clk_audio_pll_pmc_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_audio_pmc *apmc_ck = to_clk_audio_pmc(clk);
+
+ if (!rate)
+ return -EINVAL;
+
+ pr_debug("A PLL/PMC: %s, rate = %lu (parent_rate = %lu)\n", __func__,
+ rate, parent_rate);
+
+ apmc_ck->qdpmc = parent_rate / rate - 1;
+
+ return 0;
+}
+
+static const struct clk_ops audio_pll_frac_ops = {
+ .enable = clk_audio_pll_frac_enable,
+ .disable = clk_audio_pll_frac_disable,
+ .recalc_rate = clk_audio_pll_frac_recalc_rate,
+ .set_rate = clk_audio_pll_frac_set_rate,
+};
+
+static const struct clk_ops audio_pll_pad_ops = {
+ .enable = clk_audio_pll_pad_enable,
+ .disable = clk_audio_pll_pad_disable,
+ .recalc_rate = clk_audio_pll_pad_recalc_rate,
+ .round_rate = clk_audio_pll_pad_round_rate,
+ .set_rate = clk_audio_pll_pad_set_rate,
+};
+
+static const struct clk_ops audio_pll_pmc_ops = {
+ .enable = clk_audio_pll_pmc_enable,
+ .disable = clk_audio_pll_pmc_disable,
+ .recalc_rate = clk_audio_pll_pmc_recalc_rate,
+ .round_rate = clk_audio_pll_pmc_round_rate,
+ .set_rate = clk_audio_pll_pmc_set_rate,
+};
+
+struct clk * __init
+at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
+ const char *parent_name)
+{
+ struct clk_audio_frac *frac_ck;
+ int ret;
+
+ frac_ck = kzalloc(sizeof(*frac_ck), GFP_KERNEL);
+ if (!frac_ck)
+ return ERR_PTR(-ENOMEM);
+
+ frac_ck->clk.name = name;
+ frac_ck->clk.ops = &audio_pll_frac_ops;
+ frac_ck->parent_name = parent_name;
+ frac_ck->clk.parent_names = &frac_ck->parent_name;
+ frac_ck->clk.num_parents = 1;
+ /* frac_ck->clk.flags = CLK_SET_RATE_GATE; */
+
+ frac_ck->regmap = regmap;
+
+ ret = clk_register(&frac_ck->clk);
+ if (ret) {
+ kfree(frac_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &frac_ck->clk;
+}
+
+struct clk * __init
+at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
+ const char *parent_name)
+{
+ struct clk_audio_pad *apad_ck;
+ int ret;
+
+ apad_ck = kzalloc(sizeof(*apad_ck), GFP_KERNEL);
+ if (!apad_ck)
+ return ERR_PTR(-ENOMEM);
+
+ apad_ck->clk.name = name;
+ apad_ck->clk.ops = &audio_pll_pad_ops;
+ apad_ck->parent_name = parent_name;
+ apad_ck->clk.parent_names = &apad_ck->parent_name;
+ apad_ck->clk.num_parents = 1;
+ /* apad_ck->clk.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ CLK_SET_RATE_PARENT; */
+
+ apad_ck->regmap = regmap;
+
+ ret = clk_register(&apad_ck->clk);
+ if (ret) {
+ kfree(apad_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &apad_ck->clk;
+}
+
+struct clk * __init
+at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
+ const char *parent_name)
+{
+ struct clk_audio_pmc *apmc_ck;
+ int ret;
+
+ apmc_ck = kzalloc(sizeof(*apmc_ck), GFP_KERNEL);
+ if (!apmc_ck)
+ return ERR_PTR(-ENOMEM);
+
+ apmc_ck->clk.name = name;
+ apmc_ck->clk.ops = &audio_pll_pmc_ops;
+ apmc_ck->parent_name = parent_name;
+ apmc_ck->clk.parent_names = &apmc_ck->parent_name;
+ apmc_ck->clk.num_parents = 1;
+ /* apmc_ck.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
+ CLK_SET_RATE_PARENT; */
+
+ apmc_ck->regmap = regmap;
+
+ ret = clk_register(&apmc_ck->clk);
+ if (ret) {
+ kfree(apmc_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &apmc_ck->clk;
+}
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 909c4a4530f8..79b83b45ab62 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -19,6 +19,8 @@
#define GENERATED_MAX_DIV 255
+#define GCK_INDEX_DT_AUDIO_PLL 5
+
struct clk_generated {
struct clk hw;
struct regmap *regmap;
@@ -26,6 +28,7 @@ struct clk_generated {
u32 id;
u32 gckdiv;
u8 parent_id;
+ bool audio_pll_allowed;
};
#define to_clk_generated(hw) \
@@ -182,7 +185,7 @@ at91_clk_register_generated(struct regmap *regmap,
/* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */
gck->regmap = regmap;
gck->range = *range;
- /* gck->audio_pll_allowed = pll_audio; */
+ gck->audio_pll_allowed = pll_audio;
hw = &gck->hw;
ret = clk_register(&gck->hw);
diff --git a/drivers/clk/at91/clk-i2s-mux.c b/drivers/clk/at91/clk-i2s-mux.c
new file mode 100644
index 000000000000..1418ec8662c9
--- /dev/null
+++ b/drivers/clk/at91/clk-i2s-mux.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 Microchip Technology Inc,
+ * Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
+ *
+ *
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <of.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/clk/at91_pmc.h>
+#include <mfd/syscon.h>
+#include <regmap.h>
+
+#include <soc/at91/atmel-sfr.h>
+
+#include "pmc.h"
+
+#define I2S_MUX_SOURCE_MAX 2
+
+struct clk_i2s_mux {
+ struct clk clk;
+ struct regmap *regmap;
+ u8 bus_id;
+ const char *parent_names[I2S_MUX_SOURCE_MAX];
+};
+
+#define to_clk_i2s_mux(clk) container_of(clk, struct clk_i2s_mux, clk)
+
+static int clk_i2s_mux_get_parent(struct clk *clk)
+{
+ struct clk_i2s_mux *mux = to_clk_i2s_mux(clk);
+ u32 val;
+
+ regmap_read(mux->regmap, AT91_SFR_I2SCLKSEL, &val);
+
+ return (val & BIT(mux->bus_id)) >> mux->bus_id;
+}
+
+static int clk_i2s_mux_set_parent(struct clk *clk, u8 index)
+{
+ struct clk_i2s_mux *mux = to_clk_i2s_mux(clk);
+
+ return regmap_update_bits(mux->regmap, AT91_SFR_I2SCLKSEL,
+ BIT(mux->bus_id), index << mux->bus_id);
+}
+
+static const struct clk_ops clk_i2s_mux_ops = {
+ .set_rate = clk_parent_set_rate,
+ .round_rate = clk_parent_round_rate,
+ .get_parent = clk_i2s_mux_get_parent,
+ .set_parent = clk_i2s_mux_set_parent,
+};
+
+struct clk * __init
+at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
+ const char * const *parent_names,
+ unsigned int num_parents, u8 bus_id)
+{
+ struct clk_i2s_mux *i2s_ck;
+ int ret;
+
+ i2s_ck = kzalloc(sizeof(*i2s_ck), GFP_KERNEL);
+ if (!i2s_ck)
+ return ERR_PTR(-ENOMEM);
+
+ i2s_ck->clk.name = name;
+ i2s_ck->clk.ops = &clk_i2s_mux_ops;
+ memcpy(i2s_ck->parent_names, parent_names,
+ num_parents * sizeof(i2s_ck->parent_names[0]));
+ i2s_ck->clk.parent_names = &i2s_ck->parent_names[0];
+ i2s_ck->clk.num_parents = num_parents;
+
+ i2s_ck->bus_id = bus_id;
+ i2s_ck->regmap = regmap;
+
+ ret = clk_register(&i2s_ck->clk);
+ if (ret) {
+ kfree(i2s_ck);
+ return ERR_PTR(ret);
+ }
+
+ return &i2s_ck->clk;
+}
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index bea3c89e2c3a..3f7aabbb551a 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -135,6 +135,8 @@ static struct
u32 imr;
u32 pcsr1;
u32 pcr[PMC_MAX_IDS];
+ u32 audio_pll0;
+ u32 audio_pll1;
u32 pckr[PMC_MAX_PCKS];
} pmc_cache;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 705486a1f440..0efd70b7fcb3 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -84,6 +84,18 @@ int of_at91_get_clk_range(struct device_node *np, const char *propname,
struct clk *of_clk_hw_pmc_get(struct of_phandle_args *clkspec, void *data);
+struct clk * __init
+at91_clk_register_audio_pll_frac(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk * __init
+at91_clk_register_audio_pll_pad(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
+struct clk * __init
+at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
+ const char *parent_name);
+
struct clk * __init
at91_clk_register_generated(struct regmap *regmap,
const char *name, const char **parent_names,
@@ -94,6 +106,11 @@ struct clk * __init
at91_clk_register_h32mx(struct regmap *regmap, const char *name,
const char *parent_name);
+struct clk * __init
+at91_clk_i2s_mux_register(struct regmap *regmap, const char *name,
+ const char * const *parent_names,
+ unsigned int num_parents, u8 bus_id);
+
struct clk * __init
at91_clk_register_main_rc_osc(struct regmap *regmap, const char *name,
u32 frequency, u32 accuracy);
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index 61fdf256c036..f17a88cd8845 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -84,6 +84,8 @@ static const struct {
{ .n = "trng_clk", .id = 47, .r = { .min = 0, .max = 83000000 }, },
{ .n = "pdmic_clk", .id = 48, .r = { .min = 0, .max = 83000000 }, },
{ .n = "securam_clk", .id = 51, },
+ { .n = "i2s0_clk", .id = 54, .r = { .min = 0, .max = 83000000 }, },
+ { .n = "i2s1_clk", .id = 55, .r = { .min = 0, .max = 83000000 }, },
{ .n = "can0_clk", .id = 56, .r = { .min = 0, .max = 83000000 }, },
{ .n = "can1_clk", .id = 57, .r = { .min = 0, .max = 83000000 }, },
{ .n = "classd_clk", .id = 59, .r = { .min = 0, .max = 83000000 }, },
@@ -121,6 +123,8 @@ static const struct {
{ .n = "pwm_gclk", .id = 38, .r = { .min = 0, .max = 83000000 }, },
{ .n = "isc_gclk", .id = 46, },
{ .n = "pdmic_gclk", .id = 48, },
+ { .n = "i2s0_gclk", .id = 54, .pll = true },
+ { .n = "i2s1_gclk", .id = 55, .pll = true },
{ .n = "can0_gclk", .id = 56, .r = { .min = 0, .max = 80000000 }, },
{ .n = "can1_gclk", .id = 57, .r = { .min = 0, .max = 80000000 }, },
{ .n = "classd_gclk", .id = 59, .r = { .min = 0, .max = 100000000 },
@@ -132,7 +136,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
struct clk_range range = CLK_RANGE(0, 0);
const char *slck_name, *mainxtal_name;
struct pmc_data *sama5d2_pmc;
- const char *parent_names[5];
+ const char *parent_names[6];
struct regmap *regmap, *regmap_sfr;
struct clk *hw;
int i;
@@ -153,7 +157,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
if (IS_ERR(regmap))
return;
- sama5d2_pmc = pmc_data_allocate(PMC_MCK2 + 1,
+ sama5d2_pmc = pmc_data_allocate(PMC_I2S1_MUX + 1,
nck(sama5d2_systemck),
nck(sama5d2_periph32ck),
nck(sama5d2_gck));
@@ -189,6 +193,21 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
if (IS_ERR(hw))
goto err_free;
+ hw = at91_clk_register_audio_pll_frac(regmap, "audiopll_fracck",
+ "mainck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_audio_pll_pad(regmap, "audiopll_padck",
+ "audiopll_fracck");
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = at91_clk_register_audio_pll_pmc(regmap, "audiopll_pmcck",
+ "audiopll_fracck");
+ if (IS_ERR(hw))
+ goto err_free;
+
regmap_sfr = syscon_regmap_lookup_by_compatible("atmel,sama5d2-sfr");
if (IS_ERR(regmap_sfr))
regmap_sfr = NULL;
@@ -228,13 +247,14 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
parent_names[4] = "masterck";
+ parent_names[5] = "audiopll_pmcck";
for (i = 0; i < 3; i++) {
char *name;
name = xasprintf("prog%d", i);
hw = at91_clk_register_programmable(regmap, name,
- parent_names, 5, i,
+ parent_names, 6, i,
&at91sam9x5_programmable_layout);
if (IS_ERR(hw))
goto err_free;
@@ -279,10 +299,11 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
parent_names[2] = "plladivck";
parent_names[3] = "utmick";
parent_names[4] = "masterck";
+ parent_names[5] = "audiopll_pmcck";
for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
hw = at91_clk_register_generated(regmap,
sama5d2_gck[i].n,
- parent_names, 5,
+ parent_names, 6,
sama5d2_gck[i].id,
sama5d2_gck[i].pll,
&sama5d2_gck[i].r);
@@ -292,6 +313,26 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
sama5d2_pmc->ghws[sama5d2_gck[i].id] = hw;
}
+ if (regmap_sfr) {
+ parent_names[0] = "i2s0_clk";
+ parent_names[1] = "i2s0_gclk";
+ hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s0_muxclk",
+ parent_names, 2, 0);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_I2S0_MUX] = hw;
+
+ parent_names[0] = "i2s1_clk";
+ parent_names[1] = "i2s1_gclk";
+ hw = at91_clk_i2s_mux_register(regmap_sfr, "i2s1_muxclk",
+ parent_names, 2, 1);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sama5d2_pmc->chws[PMC_I2S1_MUX] = hw;
+ }
+
of_clk_add_provider(np, of_clk_hw_pmc_get, sama5d2_pmc);
return;
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index d02dba1501b7..08a07556568a 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -181,4 +181,29 @@
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
+#define AT91_PMC_AUDIO_PLL0 0x14c
+#define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0)
+#define AT91_PMC_AUDIO_PLL_PADEN (1 << 1)
+#define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2)
+#define AT91_PMC_AUDIO_PLL_RESETN (1 << 3)
+#define AT91_PMC_AUDIO_PLL_ND_OFFSET 8
+#define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET)
+#define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16
+#define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET)
+
+#define AT91_PMC_AUDIO_PLL1 0x150
+#define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff
+#define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24
+#define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET
+#define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26
+#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f
+#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
+#define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET)
+
#endif
--
2.26.0.rc2
_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 20/21] clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock support
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (18 preceding siblings ...)
2020-04-13 7:52 ` [PATCH 19/21] clk: at91: add sama5d2 audio PLL support Ahmad Fatoum
@ 2020-04-13 7:52 ` Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 21/21] clk: at91: sckc: fix off-by-1000 in udelay() Ahmad Fatoum
2020-04-15 9:23 ` [PATCH 00/21] clk: at91: sync with Linux v5.6 Sascha Hauer
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:52 UTC (permalink / raw)
To: barebox
During a bug hunt that ultimately turned out unrelated to the state
of the barebox at91 clk driver, I synchronized its state with Linux v5.6.
Bug fixes and clean up to minimize the diff were split out in separate
prior commits. This last commit imports the rest, which is basically
support for Microchip's new ARM926EJ-S SoC, the SAM9x60.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
arch/arm/mach-at91/Kconfig | 11 +
drivers/clk/at91/Makefile | 2 +
drivers/clk/at91/at91sam9x5.c | 12 +-
drivers/clk/at91/clk-generated.c | 56 +++--
drivers/clk/at91/clk-main.c | 10 +-
drivers/clk/at91/clk-master.c | 7 +-
drivers/clk/at91/clk-peripheral.c | 43 ++--
drivers/clk/at91/clk-pll.c | 12 +-
drivers/clk/at91/clk-programmable.c | 44 +++-
drivers/clk/at91/clk-sam9x60-pll.c | 322 ++++++++++++++++++++++++
drivers/clk/at91/clk-usb.c | 33 ++-
drivers/clk/at91/dt-compat.c | 9 +
drivers/clk/at91/pmc.c | 8 +-
drivers/clk/at91/pmc.h | 28 ++-
drivers/clk/at91/sam9x60.c | 313 +++++++++++++++++++++++
drivers/clk/at91/sama5d2.c | 20 +-
drivers/clk/at91/sama5d4.c | 8 +
drivers/clk/at91/sckc.c | 372 ++++++++++++++++++----------
include/linux/clk/at91_pmc.h | 28 ++-
19 files changed, 1115 insertions(+), 223 deletions(-)
create mode 100644 drivers/clk/at91/clk-sam9x60-pll.c
create mode 100644 drivers/clk/at91/sam9x60.c
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 022635381009..77b3e9db64c8 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -40,6 +40,9 @@ config HAVE_AT91_AUDIO_PLL
config HAVE_AT91_I2S_MUX_CLK
bool
+config HAVE_AT91_SAM9X60_PLL
+ bool
+
# Select if board uses the common at91sam926x_board_init
config AT91SAM926X_BOARD_INIT
bool
@@ -108,6 +111,14 @@ config SOC_SAMA5D4
select HAS_MACB
select HAVE_MACH_ARM_HEAD
+config SOC_SAM9X60
+ bool
+ select CPU_ARM926T
+ select HAVE_AT91_USB_CLK
+ select HAVE_AT91_GENERATED_CLK
+ select HAVE_AT91_SAM9X60_PLL
+ select PINCTRL_AT91
+
config ARCH_TEXT_BASE
hex
default 0x73f00000 if SOC_AT91SAM9G45
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
index 605f698439d0..423605f45203 100644
--- a/drivers/clk/at91/Makefile
+++ b/drivers/clk/at91/Makefile
@@ -14,7 +14,9 @@ obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
obj-$(CONFIG_HAVE_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_HAVE_AT91_GENERATED_CLK) += clk-generated.o
obj-$(CONFIG_HAVE_AT91_I2S_MUX_CLK) += clk-i2s-mux.o
+obj-$(CONFIG_HAVE_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
obj-$(CONFIG_SOC_AT91SAM9) += at91sam9260.o at91sam9rl.o at91sam9x5.o dt-compat.o
+obj-$(CONFIG_SOC_SAM9X60) += sam9x60.o
obj-$(CONFIG_SOC_SAMA5D4) += sama5d4.o
obj-$(CONFIG_SOC_SAMA5D3) += dt-compat.o
obj-$(CONFIG_SOC_SAMA5D2) += sama5d2.o
diff --git a/drivers/clk/at91/at91sam9x5.c b/drivers/clk/at91/at91sam9x5.c
index 87b0fd2e1cad..baa71aa10534 100644
--- a/drivers/clk/at91/at91sam9x5.c
+++ b/drivers/clk/at91/at91sam9x5.c
@@ -55,6 +55,13 @@ static const struct {
{ .n = "pck1", .p = "prog1", .id = 9 },
};
+static const struct clk_pcr_layout at91sam9x5_pcr_layout = {
+ .offset = 0x10c,
+ .cmd = BIT(12),
+ .pid_mask = GENMASK(5, 0),
+ .div_mask = GENMASK(17, 16),
+};
+
struct pck {
char *n;
u8 id;
@@ -150,8 +157,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
return;
at91sam9x5_pmc = pmc_data_allocate(PMC_MAIN + 1,
- nck(at91sam9x5_systemck),
- nck(at91sam9x35_periphck), 0);
+ nck(at91sam9x5_systemck), 31, 0);
if (!at91sam9x5_pmc)
return;
@@ -249,6 +255,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
for (i = 0; i < ARRAY_SIZE(at91sam9x5_periphck); i++) {
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &at91sam9x5_pcr_layout,
at91sam9x5_periphck[i].n,
"masterck",
at91sam9x5_periphck[i].id,
@@ -261,6 +268,7 @@ static void __init at91sam9x5_pmc_setup(struct device_node *np,
for (i = 0; extra_pcks[i].id; i++) {
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &at91sam9x5_pcr_layout,
extra_pcks[i].n,
"masterck",
extra_pcks[i].id,
diff --git a/drivers/clk/at91/clk-generated.c b/drivers/clk/at91/clk-generated.c
index 79b83b45ab62..56b800facbaf 100644
--- a/drivers/clk/at91/clk-generated.c
+++ b/drivers/clk/at91/clk-generated.c
@@ -14,6 +14,7 @@
#include <linux/clk/at91_pmc.h>
#include <mfd/syscon.h>
#include <regmap.h>
+#include <linux/bitfield.h>
#include "pmc.h"
@@ -27,6 +28,7 @@ struct clk_generated {
struct clk_range range;
u32 id;
u32 gckdiv;
+ const struct clk_pcr_layout *layout;
u8 parent_id;
bool audio_pll_allowed;
};
@@ -41,14 +43,14 @@ static int clk_generated_enable(struct clk *hw)
pr_debug("GCLK: %s, gckdiv = %d, parent id = %d\n",
__func__, gck->gckdiv, gck->parent_id);
- regmap_write(gck->regmap, AT91_PMC_PCR,
- (gck->id & AT91_PMC_PCR_PID_MASK));
- regmap_update_bits(gck->regmap, AT91_PMC_PCR,
- AT91_PMC_PCR_GCKDIV_MASK | AT91_PMC_PCR_GCKCSS_MASK |
- AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
- AT91_PMC_PCR_GCKCSS(gck->parent_id) |
- AT91_PMC_PCR_CMD |
- AT91_PMC_PCR_GCKDIV(gck->gckdiv) |
+ regmap_write(gck->regmap, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ regmap_update_bits(gck->regmap, gck->layout->offset,
+ AT91_PMC_PCR_GCKDIV_MASK | gck->layout->gckcss_mask |
+ gck->layout->cmd | AT91_PMC_PCR_GCKEN,
+ field_prep(gck->layout->gckcss_mask, gck->parent_id) |
+ gck->layout->cmd |
+ FIELD_PREP(AT91_PMC_PCR_GCKDIV_MASK, gck->gckdiv) |
AT91_PMC_PCR_GCKEN);
return 0;
}
@@ -57,11 +59,11 @@ static void clk_generated_disable(struct clk *hw)
{
struct clk_generated *gck = to_clk_generated(hw);
- regmap_write(gck->regmap, AT91_PMC_PCR,
- (gck->id & AT91_PMC_PCR_PID_MASK));
- regmap_update_bits(gck->regmap, AT91_PMC_PCR,
- AT91_PMC_PCR_CMD | AT91_PMC_PCR_GCKEN,
- AT91_PMC_PCR_CMD);
+ regmap_write(gck->regmap, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ regmap_update_bits(gck->regmap, gck->layout->offset,
+ gck->layout->cmd | AT91_PMC_PCR_GCKEN,
+ gck->layout->cmd);
}
static int clk_generated_is_enabled(struct clk *hw)
@@ -69,9 +71,9 @@ static int clk_generated_is_enabled(struct clk *hw)
struct clk_generated *gck = to_clk_generated(hw);
unsigned int status;
- regmap_write(gck->regmap, AT91_PMC_PCR,
- (gck->id & AT91_PMC_PCR_PID_MASK));
- regmap_read(gck->regmap, AT91_PMC_PCR, &status);
+ regmap_write(gck->regmap, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ regmap_read(gck->regmap, gck->layout->offset, &status);
return status & AT91_PMC_PCR_GCKEN ? 1 : 0;
}
@@ -149,18 +151,17 @@ static void clk_generated_startup(struct clk_generated *gck)
{
u32 tmp;
- regmap_write(gck->regmap, AT91_PMC_PCR,
- (gck->id & AT91_PMC_PCR_PID_MASK));
- regmap_read(gck->regmap, AT91_PMC_PCR, &tmp);
+ regmap_write(gck->regmap, gck->layout->offset,
+ (gck->id & gck->layout->pid_mask));
+ regmap_read(gck->regmap, gck->layout->offset, &tmp);
- gck->parent_id = (tmp & AT91_PMC_PCR_GCKCSS_MASK)
- >> AT91_PMC_PCR_GCKCSS_OFFSET;
- gck->gckdiv = (tmp & AT91_PMC_PCR_GCKDIV_MASK)
- >> AT91_PMC_PCR_GCKDIV_OFFSET;
+ gck->parent_id = field_get(gck->layout->gckcss_mask, tmp);
+ gck->gckdiv = FIELD_GET(AT91_PMC_PCR_GCKDIV_MASK, tmp);
}
struct clk * __init
at91_clk_register_generated(struct regmap *regmap,
+ const struct clk_pcr_layout *layout,
const char *name, const char **parent_names,
u8 num_parents, u8 id, bool pll_audio,
const struct clk_range *range)
@@ -182,18 +183,21 @@ at91_clk_register_generated(struct regmap *regmap,
gck->hw.parent_names = xmemdup(parent_names, parents_array_size);
gck->hw.num_parents = num_parents;
- /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE; */
+ /* gck->hw.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | CLK_SET_PARENT; */
gck->regmap = regmap;
gck->range = *range;
gck->audio_pll_allowed = pll_audio;
+ gck->layout = layout;
+ clk_generated_startup(gck);
hw = &gck->hw;
ret = clk_register(&gck->hw);
if (ret) {
kfree(gck);
hw = ERR_PTR(ret);
- } else
- clk_generated_startup(gck);
+ } else {
+ pmc_register_id(id);
+ }
return hw;
}
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index 46bb47914960..08abb1673b31 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -21,6 +21,10 @@
#define MOR_KEY_MASK (0xff << 16)
+#define clk_main_parent_select(s) (((s) & \
+ (AT91_PMC_MOSCEN | \
+ AT91_PMC_OSCBYPASS)) ? 1 : 0)
+
struct clk_main_osc {
struct clk clk;
struct regmap *regmap;
@@ -114,7 +118,7 @@ static int clk_main_osc_is_enabled(struct clk *clk)
regmap_read(regmap, AT91_PMC_SR, &status);
- return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN);
+ return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
}
static const struct clk_ops main_osc_ops = {
@@ -417,7 +421,7 @@ static int clk_sam9x5_main_get_parent(struct clk *clk)
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
- return status & AT91_PMC_MOSCEN ? 1 : 0;
+ return clk_main_parent_select(status);
}
static const struct clk_ops sam9x5_main_ops = {
@@ -457,7 +461,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
clkmain->regmap = regmap;
regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
- clkmain->parent = status & AT91_PMC_MOSCEN ? 1 : 0;
+ clkmain->parent = clk_main_parent_select(status);
ret = clk_register(&clkmain->clk);
if (ret) {
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index 766502fd7a3d..4e3b512aaaaf 100644
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -27,6 +27,7 @@ struct clk_master {
const struct clk_master_layout *layout;
const struct clk_master_characteristics *characteristics;
const char *parents[MASTER_SOURCE_MAX];
+ u32 mckr;
};
static inline bool clk_master_ready(struct regmap *regmap)
@@ -67,7 +68,7 @@ static unsigned long clk_master_recalc_rate(struct clk *clk,
master->characteristics;
unsigned int mckr;
- regmap_read(master->regmap, AT91_PMC_MCKR, &mckr);
+ regmap_read(master->regmap, master->layout->offset, &mckr);
mckr &= layout->mask;
pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
@@ -93,7 +94,7 @@ static int clk_master_get_parent(struct clk *clk)
struct clk_master *master = to_clk_master(clk);
unsigned int mckr;
- regmap_read(master->regmap, AT91_PMC_MCKR, &mckr);
+ regmap_read(master->regmap, master->layout->offset, &mckr);
return mckr & AT91_PMC_CSS;
}
@@ -144,9 +145,11 @@ at91_clk_register_master(struct regmap *regmap,
const struct clk_master_layout at91rm9200_master_layout = {
.mask = 0x31F,
.pres_shift = 2,
+ .offset = AT91_PMC_MCKR,
};
const struct clk_master_layout at91sam9x5_master_layout = {
.mask = 0x373,
.pres_shift = 4,
+ .offset = AT91_PMC_MCKR,
};
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 21d58b4a34fd..2b9008eb2ce1 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -37,6 +37,7 @@ struct clk_sam9x5_peripheral {
struct clk_range range;
u32 id;
u32 div;
+ const struct clk_pcr_layout *layout;
bool auto_div;
const char *parent;
};
@@ -159,13 +160,13 @@ static int clk_sam9x5_peripheral_enable(struct clk *clk)
if (periph->id < PERIPHERAL_ID_MIN)
return 0;
- regmap_write(periph->regmap, AT91_PMC_PCR,
- (periph->id & AT91_PMC_PCR_PID_MASK));
- regmap_write_bits(periph->regmap, AT91_PMC_PCR,
- AT91_PMC_PCR_DIV_MASK | AT91_PMC_PCR_CMD |
+ regmap_write(periph->regmap, periph->layout->offset,
+ (periph->id & periph->layout->pid_mask));
+ regmap_write_bits(periph->regmap, periph->layout->offset,
+ periph->layout->div_mask | periph->layout->cmd |
AT91_PMC_PCR_EN,
- AT91_PMC_PCR_DIV(periph->div) |
- AT91_PMC_PCR_CMD |
+ field_prep(periph->layout->div_mask, periph->div) |
+ periph->layout->cmd |
AT91_PMC_PCR_EN);
return 0;
@@ -178,11 +179,11 @@ static void clk_sam9x5_peripheral_disable(struct clk *clk)
if (periph->id < PERIPHERAL_ID_MIN)
return;
- regmap_write(periph->regmap, AT91_PMC_PCR,
- (periph->id & AT91_PMC_PCR_PID_MASK));
- regmap_write_bits(periph->regmap, AT91_PMC_PCR,
- AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD,
- AT91_PMC_PCR_CMD);
+ regmap_write(periph->regmap, periph->layout->offset,
+ (periph->id & periph->layout->pid_mask));
+ regmap_write_bits(periph->regmap, periph->layout->offset,
+ AT91_PMC_PCR_EN | periph->layout->cmd,
+ periph->layout->cmd);
}
static int clk_sam9x5_peripheral_is_enabled(struct clk *clk)
@@ -193,9 +194,9 @@ static int clk_sam9x5_peripheral_is_enabled(struct clk *clk)
if (periph->id < PERIPHERAL_ID_MIN)
return 1;
- regmap_write(periph->regmap, AT91_PMC_PCR,
- (periph->id & AT91_PMC_PCR_PID_MASK));
- regmap_read(periph->regmap, AT91_PMC_PCR, &status);
+ regmap_write(periph->regmap, periph->layout->offset,
+ (periph->id & periph->layout->pid_mask));
+ regmap_read(periph->regmap, periph->layout->offset, &status);
return status & AT91_PMC_PCR_EN ? 1 : 0;
}
@@ -210,12 +211,12 @@ clk_sam9x5_peripheral_recalc_rate(struct clk *clk,
if (periph->id < PERIPHERAL_ID_MIN)
return parent_rate;
- regmap_write(periph->regmap, AT91_PMC_PCR,
- (periph->id & AT91_PMC_PCR_PID_MASK));
- regmap_read(periph->regmap, AT91_PMC_PCR, &status);
+ regmap_write(periph->regmap, periph->layout->offset,
+ (periph->id & periph->layout->pid_mask));
+ regmap_read(periph->regmap, periph->layout->offset, &status);
if (status & AT91_PMC_PCR_EN) {
- periph->div = PERIPHERAL_RSHIFT(status);
+ periph->div = field_get(periph->layout->div_mask, status);
periph->auto_div = false;
} else {
clk_sam9x5_peripheral_autodiv(periph);
@@ -308,6 +309,7 @@ static const struct clk_ops sam9x5_peripheral_ops = {
struct clk * __init
at91_clk_register_sam9x5_peripheral(struct regmap *regmap,
+ const struct clk_pcr_layout *layout,
const char *name, const char *parent_name,
u32 id, const struct clk_range *range)
{
@@ -331,7 +333,9 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap,
periph->id = id;
periph->div = 0;
periph->regmap = regmap;
- periph->auto_div = true;
+ if (layout->div_mask)
+ periph->auto_div = true;
+ periph->layout = layout;
periph->range = *range;
ret = clk_register(&periph->clk);
@@ -341,6 +345,7 @@ at91_clk_register_sam9x5_peripheral(struct regmap *regmap,
}
clk_sam9x5_peripheral_autodiv(periph);
+ pmc_register_id(id);
return &periph->clk;
}
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index d3c4ab6f7a26..5cb156e784e6 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -116,19 +116,11 @@ static unsigned long clk_pll_recalc_rate(struct clk *clk,
unsigned long parent_rate)
{
struct clk_pll *pll = to_clk_pll(clk);
- unsigned int pllr;
- u16 mul;
- u8 div;
-
- regmap_read(pll->regmap, PLL_REG(pll->id), &pllr);
-
- div = PLL_DIV(pllr);
- mul = PLL_MUL(pllr, pll->layout);
- if (!div || !mul)
+ if (!pll->div || !pll->mul)
return 0;
- return (parent_rate / div) * (mul + 1);
+ return (parent_rate / pll->div) * (pll->mul + 1);
}
static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
index 09bd8bc5306e..26c36a882d8c 100644
--- a/drivers/clk/at91/clk-programmable.c
+++ b/drivers/clk/at91/clk-programmable.c
@@ -18,8 +18,7 @@
#define PROG_ID_MAX 7
#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
-#define PROG_PRES_MASK 0x7
-#define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & PROG_PRES_MASK)
+#define PROG_PRES(layout, pckr) ((pckr >> layout->pres_shift) & layout->pres_mask)
#define PROG_MAX_RM9200_CSS 3
struct clk_programmable {
@@ -36,11 +35,18 @@ static unsigned long clk_programmable_recalc_rate(struct clk *clk,
unsigned long parent_rate)
{
struct clk_programmable *prog = to_clk_programmable(clk);
+ const struct clk_programmable_layout *layout = prog->layout;
unsigned int pckr;
+ unsigned long rate;
regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr);
- return parent_rate >> PROG_PRES(prog->layout, pckr);
+ if (layout->is_pres_direct)
+ rate = parent_rate / (PROG_PRES(layout, pckr) + 1);
+ else
+ rate = parent_rate >> PROG_PRES(layout, pckr);
+
+ return rate;
}
static int clk_programmable_set_parent(struct clk *clk, u8 index)
@@ -88,25 +94,29 @@ static int clk_programmable_set_rate(struct clk *clk, unsigned long rate,
struct clk_programmable *prog = to_clk_programmable(clk);
const struct clk_programmable_layout *layout = prog->layout;
unsigned long div = parent_rate / rate;
- unsigned int pckr;
int shift = 0;
- regmap_read(prog->regmap, AT91_PMC_PCKR(prog->id), &pckr);
-
if (!div)
return -EINVAL;
- shift = fls(div) - 1;
+ if (layout->is_pres_direct) {
+ shift = div - 1;
- if (div != (1 << shift))
- return -EINVAL;
+ if (shift > layout->pres_mask)
+ return -EINVAL;
+ } else {
+ shift = fls(div) - 1;
- if (shift >= PROG_PRES_MASK)
- return -EINVAL;
+ if (div != (1 << shift))
+ return -EINVAL;
+
+ if (shift >= layout->pres_mask)
+ return -EINVAL;
+ }
regmap_write_bits(prog->regmap, AT91_PMC_PCKR(prog->id),
- PROG_PRES_MASK << layout->pres_shift,
- shift << layout->pres_shift);
+ layout->pres_mask << layout->pres_shift,
+ shift << layout->pres_shift);
return 0;
}
@@ -152,23 +162,31 @@ at91_clk_register_programmable(struct regmap *regmap,
return ERR_PTR(ret);
}
+ pmc_register_pck(id);
+
return &prog->clk;
}
const struct clk_programmable_layout at91rm9200_programmable_layout = {
+ .pres_mask = 0x7,
.pres_shift = 2,
.css_mask = 0x3,
.have_slck_mck = 0,
+ .is_pres_direct = 0,
};
const struct clk_programmable_layout at91sam9g45_programmable_layout = {
+ .pres_mask = 0x7,
.pres_shift = 2,
.css_mask = 0x3,
.have_slck_mck = 1,
+ .is_pres_direct = 0,
};
const struct clk_programmable_layout at91sam9x5_programmable_layout = {
+ .pres_mask = 0x7,
.pres_shift = 4,
.css_mask = 0x7,
.have_slck_mck = 0,
+ .is_pres_direct = 0,
};
diff --git a/drivers/clk/at91/clk-sam9x60-pll.c b/drivers/clk/at91/clk-sam9x60-pll.c
new file mode 100644
index 000000000000..9ca77f87226b
--- /dev/null
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -0,0 +1,322 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc.
+ *
+ */
+
+#include <common.h>
+#include <clock.h>
+#include <of.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/clk/at91_pmc.h>
+#include <mfd/syscon.h>
+#include <regmap.h>
+#include <linux/bitfield.h>
+
+#include "pmc.h"
+
+#define PMC_PLL_CTRL0 0xc
+#define PMC_PLL_CTRL0_DIV_MSK GENMASK(7, 0)
+#define PMC_PLL_CTRL0_ENPLL BIT(28)
+#define PMC_PLL_CTRL0_ENPLLCK BIT(29)
+#define PMC_PLL_CTRL0_ENLOCK BIT(31)
+
+#define PMC_PLL_CTRL1 0x10
+#define PMC_PLL_CTRL1_FRACR_MSK GENMASK(21, 0)
+#define PMC_PLL_CTRL1_MUL_MSK GENMASK(30, 24)
+
+#define PMC_PLL_ACR 0x18
+#define PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL
+#define PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL
+#define PMC_PLL_ACR_UTMIVR BIT(12)
+#define PMC_PLL_ACR_UTMIBG BIT(13)
+#define PMC_PLL_ACR_LOOP_FILTER_MSK GENMASK(31, 24)
+
+#define PMC_PLL_UPDT 0x1c
+#define PMC_PLL_UPDT_UPDATE BIT(8)
+
+#define PMC_PLL_ISR0 0xec
+
+#define PLL_DIV_MAX (FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
+#define UPLL_DIV 2
+#define PLL_MUL_MAX (FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, UINT_MAX) + 1)
+
+#define PLL_MAX_ID 1
+
+struct sam9x60_pll {
+ struct clk clk;
+ struct regmap *regmap;
+ const struct clk_pll_characteristics *characteristics;
+ u32 frac;
+ u8 id;
+ u8 div;
+ u16 mul;
+ const char *parent_name;
+};
+
+#define to_sam9x60_pll(clk) container_of(clk, struct sam9x60_pll, clk)
+
+static inline bool sam9x60_pll_ready(struct regmap *regmap, int id)
+{
+ unsigned int status;
+
+ regmap_read(regmap, PMC_PLL_ISR0, &status);
+
+ return !!(status & BIT(id));
+}
+
+static int sam9x60_pll_enable(struct clk *clk)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+ struct regmap *regmap = pll->regmap;
+ u8 div;
+ u16 mul;
+ u32 val;
+
+ regmap_write(regmap, PMC_PLL_UPDT, pll->id);
+
+ regmap_read(regmap, PMC_PLL_CTRL0, &val);
+ div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, val);
+
+ regmap_read(regmap, PMC_PLL_CTRL1, &val);
+ mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, val);
+
+ if (sam9x60_pll_ready(regmap, pll->id) &&
+ (div == pll->div && mul == pll->mul)) {
+ return 0;
+ }
+
+ /* Recommended value for PMC_PLL_ACR */
+ if (pll->characteristics->upll)
+ val = PMC_PLL_ACR_DEFAULT_UPLL;
+ else
+ val = PMC_PLL_ACR_DEFAULT_PLLA;
+ regmap_write(regmap, PMC_PLL_ACR, val);
+
+ regmap_write(regmap, PMC_PLL_CTRL1,
+ FIELD_PREP(PMC_PLL_CTRL1_MUL_MSK, pll->mul));
+
+ if (pll->characteristics->upll) {
+ /* Enable the UTMI internal bandgap */
+ val |= PMC_PLL_ACR_UTMIBG;
+ regmap_write(regmap, PMC_PLL_ACR, val);
+
+ udelay(10);
+
+ /* Enable the UTMI internal regulator */
+ val |= PMC_PLL_ACR_UTMIVR;
+ regmap_write(regmap, PMC_PLL_ACR, val);
+
+ udelay(10);
+ }
+
+ regmap_update_bits(regmap, PMC_PLL_UPDT,
+ PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
+
+ regmap_write(regmap, PMC_PLL_CTRL0,
+ PMC_PLL_CTRL0_ENLOCK | PMC_PLL_CTRL0_ENPLL |
+ PMC_PLL_CTRL0_ENPLLCK | pll->div);
+
+ regmap_update_bits(regmap, PMC_PLL_UPDT,
+ PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
+
+ while (!sam9x60_pll_ready(regmap, pll->id))
+ cpu_relax();
+
+ return 0;
+}
+
+static int sam9x60_pll_is_enabled(struct clk *clk)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+
+ return sam9x60_pll_ready(pll->regmap, pll->id);
+}
+
+static void sam9x60_pll_disable(struct clk *clk)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+
+ regmap_write(pll->regmap, PMC_PLL_UPDT, pll->id);
+
+ regmap_update_bits(pll->regmap, PMC_PLL_CTRL0,
+ PMC_PLL_CTRL0_ENPLLCK, 0);
+
+ regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
+ PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
+
+ regmap_update_bits(pll->regmap, PMC_PLL_CTRL0, PMC_PLL_CTRL0_ENPLL, 0);
+
+ if (pll->characteristics->upll)
+ regmap_update_bits(pll->regmap, PMC_PLL_ACR,
+ PMC_PLL_ACR_UTMIBG | PMC_PLL_ACR_UTMIVR, 0);
+
+ regmap_update_bits(pll->regmap, PMC_PLL_UPDT,
+ PMC_PLL_UPDT_UPDATE, PMC_PLL_UPDT_UPDATE);
+}
+
+static unsigned long sam9x60_pll_recalc_rate(struct clk *clk,
+ unsigned long parent_rate)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+
+ return (parent_rate * (pll->mul + 1)) / (pll->div + 1);
+}
+
+static long sam9x60_pll_get_best_div_mul(struct sam9x60_pll *pll,
+ unsigned long rate,
+ unsigned long parent_rate,
+ bool update)
+{
+ const struct clk_pll_characteristics *characteristics =
+ pll->characteristics;
+ unsigned long bestremainder = ULONG_MAX;
+ unsigned long maxdiv, mindiv, tmpdiv;
+ long bestrate = -ERANGE;
+ unsigned long bestdiv = 0;
+ unsigned long bestmul = 0;
+ unsigned long bestfrac = 0;
+
+ if (rate < characteristics->output[0].min ||
+ rate > characteristics->output[0].max)
+ return -ERANGE;
+
+ if (!pll->characteristics->upll) {
+ mindiv = parent_rate / rate;
+ if (mindiv < 2)
+ mindiv = 2;
+
+ maxdiv = DIV_ROUND_UP(parent_rate * PLL_MUL_MAX, rate);
+ if (maxdiv > PLL_DIV_MAX)
+ maxdiv = PLL_DIV_MAX;
+ } else {
+ mindiv = maxdiv = UPLL_DIV;
+ }
+
+ for (tmpdiv = mindiv; tmpdiv <= maxdiv; tmpdiv++) {
+ unsigned long remainder;
+ unsigned long tmprate;
+ unsigned long tmpmul;
+ unsigned long tmpfrac = 0;
+
+ /*
+ * Calculate the multiplier associated with the current
+ * divider that provide the closest rate to the requested one.
+ */
+ tmpmul = mult_frac(rate, tmpdiv, parent_rate);
+ tmprate = mult_frac(parent_rate, tmpmul, tmpdiv);
+ remainder = rate - tmprate;
+
+ if (remainder) {
+ tmpfrac = DIV_ROUND_CLOSEST_ULL((u64)remainder * tmpdiv * (1 << 22),
+ parent_rate);
+
+ tmprate += DIV_ROUND_CLOSEST_ULL((u64)tmpfrac * parent_rate,
+ tmpdiv * (1 << 22));
+
+ if (tmprate > rate)
+ remainder = tmprate - rate;
+ else
+ remainder = rate - tmprate;
+ }
+
+ /*
+ * Compare the remainder with the best remainder found until
+ * now and elect a new best multiplier/divider pair if the
+ * current remainder is smaller than the best one.
+ */
+ if (remainder < bestremainder) {
+ bestremainder = remainder;
+ bestdiv = tmpdiv;
+ bestmul = tmpmul;
+ bestrate = tmprate;
+ bestfrac = tmpfrac;
+ }
+
+ /* We've found a perfect match! */
+ if (!remainder)
+ break;
+ }
+
+ /* Check if bestrate is a valid output rate */
+ if (bestrate < characteristics->output[0].min &&
+ bestrate > characteristics->output[0].max)
+ return -ERANGE;
+
+ if (update) {
+ pll->div = bestdiv - 1;
+ pll->mul = bestmul - 1;
+ pll->frac = bestfrac;
+ }
+
+ return bestrate;
+}
+
+static long sam9x60_pll_round_rate(struct clk *clk, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+
+ return sam9x60_pll_get_best_div_mul(pll, rate, *parent_rate, false);
+}
+
+static int sam9x60_pll_set_rate(struct clk *clk, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sam9x60_pll *pll = to_sam9x60_pll(clk);
+
+ return sam9x60_pll_get_best_div_mul(pll, rate, parent_rate, true);
+}
+
+static const struct clk_ops pll_ops = {
+ .enable = sam9x60_pll_enable,
+ .disable = sam9x60_pll_disable,
+ .is_enabled = sam9x60_pll_is_enabled,
+ .recalc_rate = sam9x60_pll_recalc_rate,
+ .round_rate = sam9x60_pll_round_rate,
+ .set_rate = sam9x60_pll_set_rate,
+};
+
+struct clk * __init
+sam9x60_clk_register_pll(struct regmap *regmap,
+ const char *name, const char *parent_name, u8 id,
+ const struct clk_pll_characteristics *characteristics)
+{
+ struct sam9x60_pll *pll;
+ unsigned int pllr;
+ int ret;
+
+ if (id > PLL_MAX_ID)
+ return ERR_PTR(-EINVAL);
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ pll->clk.name = name;
+ pll->clk.ops = &pll_ops;
+ pll->parent_name = parent_name;
+ pll->clk.parent_names = &pll->parent_name;
+ pll->clk.num_parents = 1;
+ /* pll->clk.flags = CLK_SET_RATE_GATE; */
+
+ pll->id = id;
+ pll->characteristics = characteristics;
+ pll->regmap = regmap;
+
+ regmap_write(regmap, PMC_PLL_UPDT, id);
+ regmap_read(regmap, PMC_PLL_CTRL0, &pllr);
+ pll->div = FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, pllr);
+ regmap_read(regmap, PMC_PLL_CTRL1, &pllr);
+ pll->mul = FIELD_GET(PMC_PLL_CTRL1_MUL_MSK, pllr);
+
+ ret = clk_register(&pll->clk);
+ if (ret) {
+ kfree(pll);
+ return ERR_PTR(ret);
+ }
+
+ return &pll->clk;
+}
+
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index da37f8ea3783..2cf68593c0ec 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -22,10 +22,14 @@
#define RM9200_USB_DIV_SHIFT 28
#define RM9200_USB_DIV_TAB_SIZE 4
+#define SAM9X5_USBS_MASK GENMASK(0, 0)
+#define SAM9X60_USBS_MASK GENMASK(1, 0)
+
struct at91sam9x5_clk_usb {
struct clk clk;
struct regmap *regmap;
const char *parent_names[USB_SOURCE_MAX];
+ u32 usbs_mask;
};
#define to_at91sam9x5_clk_usb(clk) \
@@ -61,8 +65,7 @@ static int at91sam9x5_clk_usb_set_parent(struct clk *clk, u8 index)
if (index > 1)
return -EINVAL;
- regmap_write_bits(usb->regmap, AT91_PMC_USB, AT91_PMC_USBS,
- index ? AT91_PMC_USBS : 0);
+ regmap_write_bits(usb->regmap, AT91_PMC_USB, usb->usbs_mask, index);
return 0;
}
@@ -74,7 +77,7 @@ static int at91sam9x5_clk_usb_get_parent(struct clk *clk)
regmap_read(usb->regmap, AT91_PMC_USB, &usbr);
- return usbr & AT91_PMC_USBS;
+ return usbr & usb->usbs_mask;
}
static int at91sam9x5_clk_usb_set_rate(struct clk *clk, unsigned long rate,
@@ -138,9 +141,10 @@ static const struct clk_ops at91sam9n12_usb_ops = {
.set_rate = at91sam9x5_clk_usb_set_rate,
};
-struct clk * __init
-at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
- const char **parent_names, u8 num_parents)
+static struct clk * __init
+_at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents,
+ u32 usbs_mask)
{
struct at91sam9x5_clk_usb *usb;
int ret;
@@ -156,6 +160,7 @@ at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
/* init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE | */
/* CLK_SET_RATE_PARENT; */
usb->regmap = regmap;
+ usb->usbs_mask = SAM9X5_USBS_MASK;
ret = clk_register(&usb->clk);
if (ret) {
@@ -166,6 +171,22 @@ at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
return &usb->clk;
}
+struct clk * __init
+at91sam9x5_clk_register_usb(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents)
+{
+ return _at91sam9x5_clk_register_usb(regmap, name, parent_names,
+ num_parents, SAM9X5_USBS_MASK);
+}
+
+struct clk * __init
+sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents)
+{
+ return _at91sam9x5_clk_register_usb(regmap, name, parent_names,
+ num_parents, SAM9X60_USBS_MASK);
+}
+
struct clk * __init
at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name)
diff --git a/drivers/clk/at91/dt-compat.c b/drivers/clk/at91/dt-compat.c
index d82137638c4b..b888249199b5 100644
--- a/drivers/clk/at91/dt-compat.c
+++ b/drivers/clk/at91/dt-compat.c
@@ -23,6 +23,14 @@
#define SYSTEM_MAX_ID 31
+static const struct clk_pcr_layout dt_pcr_layout = {
+ .offset = 0x10c,
+ .cmd = BIT(12),
+ .pid_mask = GENMASK(5, 0),
+ .div_mask = GENMASK(17, 16),
+ .gckcss_mask = GENMASK(10, 8),
+};
+
static void __init of_at91rm9200_clk_main_osc_setup(struct device_node *np)
{
struct clk *hw;
@@ -248,6 +256,7 @@ of_at91_clk_periph_setup(struct device_node *np, u8 type)
&range);
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &dt_pcr_layout,
name,
parent_name,
id, &range);
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
index 3f7aabbb551a..171b62cbfd08 100644
--- a/drivers/clk/at91/pmc.c
+++ b/drivers/clk/at91/pmc.c
@@ -89,22 +89,22 @@ struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
return NULL;
pmc_data->ncore = ncore;
- pmc_data->chws = kcalloc(ncore, sizeof(struct clk_hw *), GFP_KERNEL);
+ pmc_data->chws = kcalloc(ncore, sizeof(struct clk *), GFP_KERNEL);
if (!pmc_data->chws)
goto err;
pmc_data->nsystem = nsystem;
- pmc_data->shws = kcalloc(nsystem, sizeof(struct clk_hw *), GFP_KERNEL);
+ pmc_data->shws = kcalloc(nsystem, sizeof(struct clk *), GFP_KERNEL);
if (!pmc_data->shws)
goto err;
pmc_data->nperiph = nperiph;
- pmc_data->phws = kcalloc(nperiph, sizeof(struct clk_hw *), GFP_KERNEL);
+ pmc_data->phws = kcalloc(nperiph, sizeof(struct clk *), GFP_KERNEL);
if (!pmc_data->phws)
goto err;
pmc_data->ngck = ngck;
- pmc_data->ghws = kcalloc(ngck, sizeof(struct clk_hw *), GFP_KERNEL);
+ pmc_data->ghws = kcalloc(ngck, sizeof(struct clk *), GFP_KERNEL);
if (!pmc_data->ghws)
goto err;
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 0efd70b7fcb3..d96a94e6e5fd 100644
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -9,7 +9,7 @@
#define __PMC_H_
#include <io.h>
-#include <linux/spinlock.h>
+#include <linux/bitops.h>
#include <printk.h>
struct pmc_data {
@@ -31,6 +31,7 @@ struct clk_range {
#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
struct clk_master_layout {
+ u32 offset;
u32 mask;
u8 pres_shift;
};
@@ -61,18 +62,32 @@ struct clk_pll_characteristics {
const struct clk_range *output;
u16 *icpll;
u8 *out;
+ u8 upll : 1;
};
struct clk_programmable_layout {
+ u8 pres_mask;
u8 pres_shift;
u8 css_mask;
u8 have_slck_mck;
+ u8 is_pres_direct;
};
extern const struct clk_programmable_layout at91rm9200_programmable_layout;
extern const struct clk_programmable_layout at91sam9g45_programmable_layout;
extern const struct clk_programmable_layout at91sam9x5_programmable_layout;
+struct clk_pcr_layout {
+ u32 offset;
+ u32 cmd;
+ u32 div_mask;
+ u32 gckcss_mask;
+ u32 pid_mask;
+};
+
+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
+#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
+
#define ndck(a, s) (a[s - 1].id + 1)
#define nck(a) (a[ARRAY_SIZE(a) - 1].id + 1)
struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem,
@@ -98,6 +113,7 @@ at91_clk_register_audio_pll_pmc(struct regmap *regmap, const char *name,
struct clk * __init
at91_clk_register_generated(struct regmap *regmap,
+ const struct clk_pcr_layout *layout,
const char *name, const char **parent_names,
u8 num_parents, u8 id, bool pll_audio,
const struct clk_range *range);
@@ -136,6 +152,7 @@ at91_clk_register_peripheral(struct regmap *regmap, const char *name,
const char *parent_name, u32 id);
struct clk * __init
at91_clk_register_sam9x5_peripheral(struct regmap *regmap,
+ const struct clk_pcr_layout *layout,
const char *name, const char *parent_name,
u32 id, const struct clk_range *range);
@@ -148,6 +165,11 @@ struct clk * __init
at91_clk_register_plldiv(struct regmap *regmap, const char *name,
const char *parent_name);
+struct clk * __init
+sam9x60_clk_register_pll(struct regmap *regmap,
+ const char *name, const char *parent_name, u8 id,
+ const struct clk_pll_characteristics *characteristics);
+
struct clk * __init
at91_clk_register_programmable(struct regmap *regmap, const char *name,
const char **parent_names, u8 num_parents, u8 id,
@@ -174,6 +196,10 @@ struct clk * __init
at91sam9n12_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name);
struct clk * __init
+sam9x60_clk_register_usb(struct regmap *regmap, const char *name,
+ const char **parent_names, u8 num_parents);
+
+struct clk * __init
at91rm9200_clk_register_usb(struct regmap *regmap, const char *name,
const char *parent_name, const u32 *divisors);
diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
new file mode 100644
index 000000000000..36a7a846ef06
--- /dev/null
+++ b/drivers/clk/at91/sam9x60.c
@@ -0,0 +1,313 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <driver.h>
+#include <regmap.h>
+#include <stdio.h>
+#include <mfd/syscon.h>
+
+#include <linux/clk.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <dt-bindings/clock/at91.h>
+
+#include "pmc.h"
+
+static const struct clk_master_characteristics mck_characteristics = {
+ .output = { .min = 140000000, .max = 200000000 },
+ .divisors = { 1, 2, 4, 3 },
+ .have_div3_pres = 1,
+};
+
+static const struct clk_master_layout sam9x60_master_layout = {
+ .mask = 0x373,
+ .pres_shift = 4,
+ .offset = 0x28,
+};
+
+static const struct clk_range plla_outputs[] = {
+ { .min = 300000000, .max = 600000000 },
+};
+
+static const struct clk_pll_characteristics plla_characteristics = {
+ .input = { .min = 12000000, .max = 48000000 },
+ .num_output = ARRAY_SIZE(plla_outputs),
+ .output = plla_outputs,
+};
+
+static const struct clk_range upll_outputs[] = {
+ { .min = 300000000, .max = 500000000 },
+};
+
+static const struct clk_pll_characteristics upll_characteristics = {
+ .input = { .min = 12000000, .max = 48000000 },
+ .num_output = ARRAY_SIZE(upll_outputs),
+ .output = upll_outputs,
+ .upll = true,
+};
+
+static const struct clk_programmable_layout sam9x60_programmable_layout = {
+ .pres_mask = 0xff,
+ .pres_shift = 8,
+ .css_mask = 0x1f,
+ .have_slck_mck = 0,
+ .is_pres_direct = 1,
+};
+
+static const struct clk_pcr_layout sam9x60_pcr_layout = {
+ .offset = 0x88,
+ .cmd = BIT(31),
+ .gckcss_mask = GENMASK(12, 8),
+ .pid_mask = GENMASK(6, 0),
+};
+
+static const struct {
+ char *n;
+ char *p;
+ u8 id;
+} sam9x60_systemck[] = {
+ { .n = "ddrck", .p = "masterck", .id = 2 },
+ { .n = "uhpck", .p = "usbck", .id = 6 },
+ { .n = "pck0", .p = "prog0", .id = 8 },
+ { .n = "pck1", .p = "prog1", .id = 9 },
+ { .n = "qspick", .p = "masterck", .id = 19 },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+} sam9x60_periphck[] = {
+ { .n = "pioA_clk", .id = 2, },
+ { .n = "pioB_clk", .id = 3, },
+ { .n = "pioC_clk", .id = 4, },
+ { .n = "flex0_clk", .id = 5, },
+ { .n = "flex1_clk", .id = 6, },
+ { .n = "flex2_clk", .id = 7, },
+ { .n = "flex3_clk", .id = 8, },
+ { .n = "flex6_clk", .id = 9, },
+ { .n = "flex7_clk", .id = 10, },
+ { .n = "flex8_clk", .id = 11, },
+ { .n = "sdmmc0_clk", .id = 12, },
+ { .n = "flex4_clk", .id = 13, },
+ { .n = "flex5_clk", .id = 14, },
+ { .n = "flex9_clk", .id = 15, },
+ { .n = "flex10_clk", .id = 16, },
+ { .n = "tcb0_clk", .id = 17, },
+ { .n = "pwm_clk", .id = 18, },
+ { .n = "adc_clk", .id = 19, },
+ { .n = "dma0_clk", .id = 20, },
+ { .n = "matrix_clk", .id = 21, },
+ { .n = "uhphs_clk", .id = 22, },
+ { .n = "udphs_clk", .id = 23, },
+ { .n = "macb0_clk", .id = 24, },
+ { .n = "lcd_clk", .id = 25, },
+ { .n = "sdmmc1_clk", .id = 26, },
+ { .n = "macb1_clk", .id = 27, },
+ { .n = "ssc_clk", .id = 28, },
+ { .n = "can0_clk", .id = 29, },
+ { .n = "can1_clk", .id = 30, },
+ { .n = "flex11_clk", .id = 32, },
+ { .n = "flex12_clk", .id = 33, },
+ { .n = "i2s_clk", .id = 34, },
+ { .n = "qspi_clk", .id = 35, },
+ { .n = "gfx2d_clk", .id = 36, },
+ { .n = "pit64b_clk", .id = 37, },
+ { .n = "trng_clk", .id = 38, },
+ { .n = "aes_clk", .id = 39, },
+ { .n = "tdes_clk", .id = 40, },
+ { .n = "sha_clk", .id = 41, },
+ { .n = "classd_clk", .id = 42, },
+ { .n = "isi_clk", .id = 43, },
+ { .n = "pioD_clk", .id = 44, },
+ { .n = "tcb1_clk", .id = 45, },
+ { .n = "dbgu_clk", .id = 47, },
+ { .n = "mpddr_clk", .id = 49, },
+};
+
+static const struct {
+ char *n;
+ u8 id;
+ struct clk_range r;
+ bool pll;
+} sam9x60_gck[] = {
+ { .n = "flex0_gclk", .id = 5, },
+ { .n = "flex1_gclk", .id = 6, },
+ { .n = "flex2_gclk", .id = 7, },
+ { .n = "flex3_gclk", .id = 8, },
+ { .n = "flex6_gclk", .id = 9, },
+ { .n = "flex7_gclk", .id = 10, },
+ { .n = "flex8_gclk", .id = 11, },
+ { .n = "sdmmc0_gclk", .id = 12, .r = { .min = 0, .max = 105000000 }, },
+ { .n = "flex4_gclk", .id = 13, },
+ { .n = "flex5_gclk", .id = 14, },
+ { .n = "flex9_gclk", .id = 15, },
+ { .n = "flex10_gclk", .id = 16, },
+ { .n = "tcb0_gclk", .id = 17, },
+ { .n = "adc_gclk", .id = 19, },
+ { .n = "lcd_gclk", .id = 25, .r = { .min = 0, .max = 140000000 }, },
+ { .n = "sdmmc1_gclk", .id = 26, .r = { .min = 0, .max = 105000000 }, },
+ { .n = "flex11_gclk", .id = 32, },
+ { .n = "flex12_gclk", .id = 33, },
+ { .n = "i2s_gclk", .id = 34, .r = { .min = 0, .max = 105000000 },
+ .pll = true, },
+ { .n = "pit64b_gclk", .id = 37, },
+ { .n = "classd_gclk", .id = 42, .r = { .min = 0, .max = 100000000 },
+ .pll = true, },
+ { .n = "tcb1_gclk", .id = 45, },
+ { .n = "dbgu_gclk", .id = 47, },
+};
+
+static void __init sam9x60_pmc_setup(struct device_node *np)
+{
+ struct clk_range range = CLK_RANGE(0, 0);
+ const char *td_slck_name, *md_slck_name, *mainxtal_name;
+ struct pmc_data *sam9x60_pmc;
+ const char *parent_names[6];
+ struct regmap *regmap;
+ struct clk *hw;
+ int i;
+ bool bypass;
+
+ i = of_property_match_string(np, "clock-names", "td_slck");
+ if (i < 0)
+ return;
+
+ td_slck_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "md_slck");
+ if (i < 0)
+ return;
+
+ md_slck_name = of_clk_get_parent_name(np, i);
+
+ i = of_property_match_string(np, "clock-names", "main_xtal");
+ if (i < 0)
+ return;
+ mainxtal_name = of_clk_get_parent_name(np, i);
+
+ regmap = syscon_node_to_regmap(np);
+ if (IS_ERR(regmap))
+ return;
+
+ sam9x60_pmc = pmc_data_allocate(PMC_MAIN + 1,
+ nck(sam9x60_systemck),
+ nck(sam9x60_periphck),
+ nck(sam9x60_gck));
+ if (!sam9x60_pmc)
+ return;
+
+ hw = at91_clk_register_main_rc_osc(regmap, "main_rc_osc", 24000000,
+ 50000000);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+
+ hw = at91_clk_register_main_osc(regmap, "main_osc", mainxtal_name,
+ bypass);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = "main_rc_osc";
+ parent_names[1] = "main_osc";
+ hw = at91_clk_register_sam9x5_main(regmap, "mainck", parent_names, 2);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sam9x60_pmc->chws[PMC_MAIN] = hw;
+
+ hw = sam9x60_clk_register_pll(regmap, "pllack",
+ "mainck", 0, &plla_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ hw = sam9x60_clk_register_pll(regmap, "upllck",
+ "main_osc", 1, &upll_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sam9x60_pmc->chws[PMC_UTMI] = hw;
+
+ parent_names[0] = md_slck_name;
+ parent_names[1] = "mainck";
+ parent_names[2] = "pllack";
+ hw = at91_clk_register_master(regmap, "masterck", 3, parent_names,
+ &sam9x60_master_layout,
+ &mck_characteristics);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sam9x60_pmc->chws[PMC_MCK] = hw;
+
+ parent_names[0] = "pllack";
+ parent_names[1] = "upllck";
+ parent_names[2] = "mainck";
+ parent_names[3] = "mainck";
+ hw = sam9x60_clk_register_usb(regmap, "usbck", parent_names, 4);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ parent_names[0] = md_slck_name;
+ parent_names[1] = td_slck_name;
+ parent_names[2] = "mainck";
+ parent_names[3] = "masterck";
+ parent_names[4] = "pllack";
+ parent_names[5] = "upllck";
+ for (i = 0; i < 8; i++) {
+ char name[6];
+
+ snprintf(name, sizeof(name), "prog%d", i);
+
+ hw = at91_clk_register_programmable(regmap, name,
+ parent_names, 6, i,
+ &sam9x60_programmable_layout);
+ if (IS_ERR(hw))
+ goto err_free;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sam9x60_systemck); i++) {
+ hw = at91_clk_register_system(regmap, sam9x60_systemck[i].n,
+ sam9x60_systemck[i].p,
+ sam9x60_systemck[i].id);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sam9x60_pmc->shws[sam9x60_systemck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sam9x60_periphck); i++) {
+ hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &sam9x60_pcr_layout,
+ sam9x60_periphck[i].n,
+ "masterck",
+ sam9x60_periphck[i].id,
+ &range);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sam9x60_pmc->phws[sam9x60_periphck[i].id] = hw;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(sam9x60_gck); i++) {
+ hw = at91_clk_register_generated(regmap,
+ &sam9x60_pcr_layout,
+ sam9x60_gck[i].n,
+ parent_names, 6,
+ sam9x60_gck[i].id,
+ sam9x60_gck[i].pll,
+ &sam9x60_gck[i].r);
+ if (IS_ERR(hw))
+ goto err_free;
+
+ sam9x60_pmc->ghws[sam9x60_gck[i].id] = hw;
+ }
+
+ of_clk_add_provider(np, of_clk_hw_pmc_get, sam9x60_pmc);
+
+ return;
+
+err_free:
+ pmc_data_free(sam9x60_pmc);
+}
+/* Some clks are used for a clocksource */
+CLK_OF_DECLARE(sam9x60_pmc, "microchip,sam9x60-pmc", sam9x60_pmc_setup);
diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c
index f17a88cd8845..731637e4abb1 100644
--- a/drivers/clk/at91/sama5d2.c
+++ b/drivers/clk/at91/sama5d2.c
@@ -34,6 +34,13 @@ static const struct clk_pll_characteristics plla_characteristics = {
.out = plla_out,
};
+static const struct clk_pcr_layout sama5d2_pcr_layout = {
+ .offset = 0x10c,
+ .cmd = BIT(12),
+ .gckcss_mask = GENMASK(10, 8),
+ .pid_mask = GENMASK(6, 0),
+};
+
static const struct {
char *n;
char *p;
@@ -131,6 +138,14 @@ static const struct {
.pll = true },
};
+static const struct clk_programmable_layout sama5d2_programmable_layout = {
+ .pres_mask = 0xff,
+ .pres_shift = 4,
+ .css_mask = 0x7,
+ .have_slck_mck = 0,
+ .is_pres_direct = 1,
+};
+
static void __init sama5d2_pmc_setup(struct device_node *np)
{
struct clk_range range = CLK_RANGE(0, 0);
@@ -255,7 +270,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
hw = at91_clk_register_programmable(regmap, name,
parent_names, 6, i,
- &at91sam9x5_programmable_layout);
+ &sama5d2_programmable_layout);
if (IS_ERR(hw))
goto err_free;
}
@@ -272,6 +287,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
for (i = 0; i < ARRAY_SIZE(sama5d2_periphck); i++) {
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &sama5d2_pcr_layout,
sama5d2_periphck[i].n,
"masterck",
sama5d2_periphck[i].id,
@@ -284,6 +300,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
for (i = 0; i < ARRAY_SIZE(sama5d2_periph32ck); i++) {
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &sama5d2_pcr_layout,
sama5d2_periph32ck[i].n,
"h32mxck",
sama5d2_periph32ck[i].id,
@@ -302,6 +319,7 @@ static void __init sama5d2_pmc_setup(struct device_node *np)
parent_names[5] = "audiopll_pmcck";
for (i = 0; i < ARRAY_SIZE(sama5d2_gck); i++) {
hw = at91_clk_register_generated(regmap,
+ &sama5d2_pcr_layout,
sama5d2_gck[i].n,
parent_names, 6,
sama5d2_gck[i].id,
diff --git a/drivers/clk/at91/sama5d4.c b/drivers/clk/at91/sama5d4.c
index de14640f91d2..77ccd77404cf 100644
--- a/drivers/clk/at91/sama5d4.c
+++ b/drivers/clk/at91/sama5d4.c
@@ -34,6 +34,12 @@ static const struct clk_pll_characteristics plla_characteristics = {
.out = plla_out,
};
+static const struct clk_pcr_layout sama5d4_pcr_layout = {
+ .offset = 0x10c,
+ .cmd = BIT(12),
+ .pid_mask = GENMASK(6, 0),
+};
+
static const struct {
char *n;
char *p;
@@ -238,6 +244,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
for (i = 0; i < ARRAY_SIZE(sama5d4_periphck); i++) {
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &sama5d4_pcr_layout,
sama5d4_periphck[i].n,
"masterck",
sama5d4_periphck[i].id,
@@ -250,6 +257,7 @@ static void __init sama5d4_pmc_setup(struct device_node *np)
for (i = 0; i < ARRAY_SIZE(sama5d4_periph32ck); i++) {
hw = at91_clk_register_sam9x5_peripheral(regmap,
+ &sama5d4_pcr_layout,
sama5d4_periph32ck[i].n,
"h32mxck",
sama5d4_periph32ck[i].id,
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 7998d6a50986..3dc7843fcc11 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -24,14 +24,18 @@
SLOW_CLOCK_FREQ)
#define AT91_SCKC_CR 0x00
-#define AT91_SCKC_RCEN (1 << 0)
-#define AT91_SCKC_OSC32EN (1 << 1)
-#define AT91_SCKC_OSC32BYP (1 << 2)
-#define AT91_SCKC_OSCSEL (1 << 3)
+
+struct clk_slow_bits {
+ u32 cr_rcen;
+ u32 cr_osc32en;
+ u32 cr_osc32byp;
+ u32 cr_oscsel;
+};
struct clk_slow_osc {
struct clk clk;
void __iomem *sckcr;
+ const struct clk_slow_bits *bits;
unsigned long startup_usec;
const char *parent_name;
};
@@ -41,6 +45,7 @@ struct clk_slow_osc {
struct clk_sama5d4_slow_osc {
struct clk clk;
void __iomem *sckcr;
+ const struct clk_slow_bits *bits;
unsigned long startup_usec;
bool prepared;
const char *parent_name;
@@ -51,6 +56,7 @@ struct clk_sama5d4_slow_osc {
struct clk_slow_rc_osc {
struct clk clk;
void __iomem *sckcr;
+ const struct clk_slow_bits *bits;
unsigned long frequency;
unsigned long startup_usec;
const char *parent_name;
@@ -61,6 +67,7 @@ struct clk_slow_rc_osc {
struct clk_sam9x5_slow {
struct clk clk;
void __iomem *sckcr;
+ const struct clk_slow_bits *bits;
u8 parent;
const char *parent_names[2];
};
@@ -73,10 +80,10 @@ static int clk_slow_osc_enable(struct clk *clk)
void __iomem *sckcr = osc->sckcr;
u32 tmp = readl(sckcr);
- if (tmp & (AT91_SCKC_OSC32BYP | AT91_SCKC_OSC32EN))
+ if (tmp & (osc->bits->cr_osc32byp | osc->bits->cr_osc32en))
return 0;
- writel(tmp | AT91_SCKC_OSC32EN, sckcr);
+ writel(tmp | osc->bits->cr_osc32en, sckcr);
udelay(osc->startup_usec);
@@ -89,10 +96,10 @@ static void clk_slow_osc_disable(struct clk *clk)
void __iomem *sckcr = osc->sckcr;
u32 tmp = readl(sckcr);
- if (tmp & AT91_SCKC_OSC32BYP)
+ if (tmp & osc->bits->cr_osc32byp)
return;
- writel(tmp & ~AT91_SCKC_OSC32EN, sckcr);
+ writel(tmp & ~osc->bits->cr_osc32en, sckcr);
}
static int clk_slow_osc_is_enabled(struct clk *clk)
@@ -101,10 +108,10 @@ static int clk_slow_osc_is_enabled(struct clk *clk)
void __iomem *sckcr = osc->sckcr;
u32 tmp = readl(sckcr);
- if (tmp & AT91_SCKC_OSC32BYP)
+ if (tmp & osc->bits->cr_osc32byp)
return 1;
- return !!(tmp & AT91_SCKC_OSC32EN);
+ return !!(tmp & osc->bits->cr_osc32en);
}
static const struct clk_ops slow_osc_ops = {
@@ -118,7 +125,8 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
const char *name,
const char *parent_name,
unsigned long startup,
- bool bypass)
+ bool bypass,
+ const struct clk_slow_bits *bits)
{
int ret;
struct clk_slow_osc *osc;
@@ -133,13 +141,15 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
osc->parent_name = parent_name;
osc->clk.parent_names = &osc->parent_name;
osc->clk.num_parents = 1;
+ /* osc->clk.flags = CLK_IGNORE_UNUSED; */
osc->sckcr = sckcr;
osc->startup_usec = startup;
+ osc->bits = bits;
if (bypass)
- writel((readl(sckcr) & ~AT91_SCKC_OSC32EN) | AT91_SCKC_OSC32BYP,
- sckcr);
+ writel((readl(sckcr) & ~osc->bits->cr_osc32en) |
+ osc->bits->cr_osc32byp, sckcr);
ret = clk_register(&osc->clk);
if (ret) {
@@ -150,26 +160,12 @@ at91_clk_register_slow_osc(void __iomem *sckcr,
return &osc->clk;
}
-static void
-of_at91sam9x5_clk_slow_osc_setup(struct device_node *np, void __iomem *sckcr)
+static void at91_clk_unregister_slow_osc(struct clk *clk)
{
- struct clk *clk;
- const char *parent_name;
- const char *name = np->name;
- u32 startup;
- bool bypass;
-
- parent_name = of_clk_get_parent_name(np, 0);
- of_property_read_string(np, "clock-output-names", &name);
- of_property_read_u32(np, "atmel,startup-time-usec", &startup);
- bypass = of_property_read_bool(np, "atmel,osc-bypass");
-
- clk = at91_clk_register_slow_osc(sckcr, name, parent_name, startup,
- bypass);
- if (IS_ERR(clk))
- return;
+ struct clk_slow_osc *osc = to_clk_slow_osc(clk);
- of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ clk_unregister(clk);
+ kfree(osc);
}
static unsigned long clk_slow_rc_osc_recalc_rate(struct clk *clk,
@@ -185,7 +181,7 @@ static int clk_slow_rc_osc_enable(struct clk *clk)
struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk);
void __iomem *sckcr = osc->sckcr;
- writel(readl(sckcr) | AT91_SCKC_RCEN, sckcr);
+ writel(readl(sckcr) | osc->bits->cr_rcen, sckcr);
udelay(osc->startup_usec);
@@ -197,14 +193,14 @@ static void clk_slow_rc_osc_disable(struct clk *clk)
struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk);
void __iomem *sckcr = osc->sckcr;
- writel(readl(sckcr) & ~AT91_SCKC_RCEN, sckcr);
+ writel(readl(sckcr) & ~osc->bits->cr_rcen, sckcr);
}
static int clk_slow_rc_osc_is_enabled(struct clk *clk)
{
struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk);
- return !!(readl(osc->sckcr) & AT91_SCKC_RCEN);
+ return !!(readl(osc->sckcr) & osc->bits->cr_rcen);
}
static const struct clk_ops slow_rc_osc_ops = {
@@ -218,7 +214,9 @@ static struct clk * __init
at91_clk_register_slow_rc_osc(void __iomem *sckcr,
const char *name,
unsigned long frequency,
- unsigned long startup)
+ unsigned long accuracy,
+ unsigned long startup,
+ const struct clk_slow_bits *bits)
{
struct clk_slow_rc_osc *osc;
int ret;
@@ -234,6 +232,7 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr,
/* init.flags = CLK_IGNORE_UNUSED; */
osc->sckcr = sckcr;
+ osc->bits = bits;
osc->frequency = frequency;
osc->startup_usec = startup;
@@ -246,23 +245,12 @@ at91_clk_register_slow_rc_osc(void __iomem *sckcr,
return &osc->clk;
}
-static void
-of_at91sam9x5_clk_slow_rc_osc_setup(struct device_node *np, void __iomem *sckcr)
+static void at91_clk_unregister_slow_rc_osc(struct clk *clk)
{
- struct clk *clk;
- u32 frequency = 0;
- u32 startup = 0;
- const char *name = np->name;
-
- of_property_read_string(np, "clock-output-names", &name);
- of_property_read_u32(np, "clock-frequency", &frequency);
- of_property_read_u32(np, "atmel,startup-time-usec", &startup);
-
- clk = at91_clk_register_slow_rc_osc(sckcr, name, frequency, startup);
- if (IS_ERR(clk))
- return;
+ struct clk_slow_rc_osc *osc = to_clk_slow_rc_osc(clk);
- of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ clk_unregister(clk);
+ kfree(osc);
}
static int clk_sam9x5_slow_set_parent(struct clk *clk, u8 index)
@@ -276,14 +264,14 @@ static int clk_sam9x5_slow_set_parent(struct clk *clk, u8 index)
tmp = readl(sckcr);
- if ((!index && !(tmp & AT91_SCKC_OSCSEL)) ||
- (index && (tmp & AT91_SCKC_OSCSEL)))
+ if ((!index && !(tmp & slowck->bits->cr_oscsel)) ||
+ (index && (tmp & slowck->bits->cr_oscsel)))
return 0;
if (index)
- tmp |= AT91_SCKC_OSCSEL;
+ tmp |= slowck->bits->cr_oscsel;
else
- tmp &= ~AT91_SCKC_OSCSEL;
+ tmp &= ~slowck->bits->cr_oscsel;
writel(tmp, sckcr);
@@ -296,7 +284,7 @@ static int clk_sam9x5_slow_get_parent(struct clk *clk)
{
struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk);
- return !!(readl(slowck->sckcr) & AT91_SCKC_OSCSEL);
+ return !!(readl(slowck->sckcr) & slowck->bits->cr_oscsel);
}
static const struct clk_ops sam9x5_slow_ops = {
@@ -308,7 +296,8 @@ static struct clk * __init
at91_clk_register_sam9x5_slow(void __iomem *sckcr,
const char *name,
const char **parent_names,
- int num_parents)
+ int num_parents,
+ const struct clk_slow_bits *bits)
{
struct clk_sam9x5_slow *slowck;
int ret;
@@ -325,7 +314,8 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
slowck->clk.parent_names = slowck->parent_names;
slowck->clk.num_parents = num_parents;
slowck->sckcr = sckcr;
- slowck->parent = !!(readl(sckcr) & AT91_SCKC_OSCSEL);
+ slowck->bits = bits;
+ slowck->parent = !!(readl(sckcr) & slowck->bits->cr_oscsel);
ret = clk_register(&slowck->clk);
if (ret) {
@@ -336,69 +326,183 @@ at91_clk_register_sam9x5_slow(void __iomem *sckcr,
return &slowck->clk;
}
-static int
-of_at91sam9x5_clk_slow_setup(struct device_node *np, void __iomem *sckcr)
+static void at91_clk_unregister_sam9x5_slow(struct clk *clk)
{
- struct clk *clk;
- const char *parent_names[2];
- unsigned int num_parents;
- const char *name = np->name;
+ struct clk_sam9x5_slow *slowck = to_clk_sam9x5_slow(clk);
- num_parents = of_clk_get_parent_count(np);
- if (num_parents == 0 || num_parents > 2)
- return -EINVAL;
+ clk_unregister(clk);
+ kfree(slowck);
+}
+
+static void __init at91sam9x5_sckc_register(struct device_node *np,
+ unsigned int rc_osc_startup_us,
+ const struct clk_slow_bits *bits)
+{
+ const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
+ void __iomem *regbase = of_iomap(np, 0);
+ struct device_node *child = NULL;
+ const char *xtal_name;
+ struct clk *slow_rc, *slow_osc, *slowck;
+ bool bypass;
+ int ret;
+
+ if (!regbase)
+ return;
+
+ slow_rc = at91_clk_register_slow_rc_osc(regbase, parent_names[0],
+ 32768, 50000000,
+ rc_osc_startup_us, bits);
+ if (IS_ERR(slow_rc))
+ return;
+
+ xtal_name = of_clk_get_parent_name(np, 0);
+ if (!xtal_name) {
+ /* DT backward compatibility */
+ child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow-osc");
+ if (!child)
+ goto unregister_slow_rc;
+
+ xtal_name = of_clk_get_parent_name(child, 0);
+ bypass = of_property_read_bool(child, "atmel,osc-bypass");
+
+ child = of_get_compatible_child(np, "atmel,at91sam9x5-clk-slow");
+ } else {
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+ }
+
+ if (!xtal_name)
+ goto unregister_slow_rc;
+
+ slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
+ xtal_name, 1200000, bypass, bits);
+ if (IS_ERR(slow_osc))
+ goto unregister_slow_rc;
+
+ slowck = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names,
+ 2, bits);
+ if (IS_ERR(slowck))
+ goto unregister_slow_osc;
+
+ /* DT backward compatibility */
+ if (child)
+ ret = of_clk_add_provider(child, of_clk_src_simple_get,
+ slowck);
+ else
+ ret = of_clk_add_provider(np, of_clk_src_simple_get, slowck);
- of_clk_parent_fill(np, parent_names, num_parents);
+ if (WARN_ON(ret))
+ goto unregister_slowck;
- of_property_read_string(np, "clock-output-names", &name);
+ return;
- clk = at91_clk_register_sam9x5_slow(sckcr, name, parent_names,
- num_parents);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
+unregister_slowck:
+ at91_clk_unregister_sam9x5_slow(slowck);
+unregister_slow_osc:
+ at91_clk_unregister_slow_osc(slow_osc);
+unregister_slow_rc:
+ at91_clk_unregister_slow_rc_osc(slow_rc);
+}
+
+static const struct clk_slow_bits at91sam9x5_bits = {
+ .cr_rcen = BIT(0),
+ .cr_osc32en = BIT(1),
+ .cr_osc32byp = BIT(2),
+ .cr_oscsel = BIT(3),
+};
+
+static void __init of_at91sam9x5_sckc_setup(struct device_node *np)
+{
+ at91sam9x5_sckc_register(np, 75, &at91sam9x5_bits);
+}
+CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
+ of_at91sam9x5_sckc_setup);
- return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+static void __init of_sama5d3_sckc_setup(struct device_node *np)
+{
+ at91sam9x5_sckc_register(np, 500, &at91sam9x5_bits);
}
+CLK_OF_DECLARE(sama5d3_clk_sckc, "atmel,sama5d3-sckc",
+ of_sama5d3_sckc_setup);
-static const struct of_device_id sckc_clk_ids[] = {
- /* Slow clock */
- {
- .compatible = "atmel,at91sam9x5-clk-slow-osc",
- .data = of_at91sam9x5_clk_slow_osc_setup,
- },
- {
- .compatible = "atmel,at91sam9x5-clk-slow-rc-osc",
- .data = of_at91sam9x5_clk_slow_rc_osc_setup,
- },
- {
- .compatible = "atmel,at91sam9x5-clk-slow",
- .data = of_at91sam9x5_clk_slow_setup,
- },
- { /*sentinel*/ }
+static const struct clk_slow_bits at91sam9x60_bits = {
+ .cr_osc32en = BIT(1),
+ .cr_osc32byp = BIT(2),
+ .cr_oscsel = BIT(24),
};
-static int of_at91sam9x5_sckc_setup(struct device_node *np)
+static void __init of_sam9x60_sckc_setup(struct device_node *np)
{
- struct device_node *childnp;
- void (*clk_setup)(struct device_node *, void __iomem *);
- const struct of_device_id *clk_id;
void __iomem *regbase = of_iomap(np, 0);
+ struct clk_onecell_data *clk_data;
+ struct clk *slow_rc, *slow_osc;
+ const char *xtal_name;
+ const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
+ bool bypass;
+ int ret;
if (!regbase)
- return -ENOMEM;
-
- for_each_child_of_node(np, childnp) {
- clk_id = of_match_node(sckc_clk_ids, childnp);
- if (!clk_id)
- continue;
- clk_setup = clk_id->data;
- clk_setup(childnp, regbase);
- }
+ return;
- return 0;
+ slow_rc = clk_register_fixed_rate(parent_names[0], NULL, 0,
+ 32768);
+ if (IS_ERR(slow_rc))
+ return;
+
+ xtal_name = of_clk_get_parent_name(np, 0);
+ if (!xtal_name)
+ goto unregister_slow_rc;
+
+ bypass = of_property_read_bool(np, "atmel,osc-bypass");
+ slow_osc = at91_clk_register_slow_osc(regbase, parent_names[1],
+ xtal_name, 5000000, bypass,
+ &at91sam9x60_bits);
+ if (IS_ERR(slow_osc))
+ goto unregister_slow_rc;
+
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ goto unregister_slow_osc;
+
+ /* MD_SLCK and TD_SLCK. */
+ clk_data->clk_num = 2;
+ clk_data->clks = kcalloc(clk_data->clk_num,
+ sizeof(*clk_data->clks), GFP_KERNEL);
+ if (!clk_data->clks)
+ goto clk_data_free;
+
+ clk_data->clks[0] = clk_register_fixed_rate("md_slck",
+ parent_names[0],
+ 0, 32768);
+ if (IS_ERR(clk_data->clks[0]))
+ goto clks_free;
+
+ clk_data->clks[1] = at91_clk_register_sam9x5_slow(regbase, "td_slck",
+ parent_names, 2,
+ &at91sam9x60_bits);
+ if (IS_ERR(clk_data->clks[1]))
+ goto unregister_md_slck;
+
+ ret = of_clk_add_provider(np, of_clk_src_onecell_get, clk_data);
+ if (WARN_ON(ret))
+ goto unregister_td_slck;
+
+ return;
+
+unregister_td_slck:
+ at91_clk_unregister_sam9x5_slow(clk_data->clks[1]);
+unregister_md_slck:
+ clk_unregister(clk_data->clks[0]);
+clks_free:
+ kfree(clk_data->clks);
+clk_data_free:
+ kfree(clk_data);
+unregister_slow_osc:
+ at91_clk_unregister_slow_osc(slow_osc);
+unregister_slow_rc:
+ clk_unregister(slow_rc);
}
-CLK_OF_DECLARE(at91sam9x5_clk_sckc, "atmel,at91sam9x5-sckc",
- of_at91sam9x5_sckc_setup);
+CLK_OF_DECLARE(sam9x60_clk_sckc, "microchip,sam9x60-sckc",
+ of_sam9x60_sckc_setup);
static int clk_sama5d4_slow_osc_enable(struct clk *clk)
{
@@ -411,7 +515,7 @@ static int clk_sama5d4_slow_osc_enable(struct clk *clk)
* Assume that if it has already been selected (for example by the
* bootloader), enough time has aready passed.
*/
- if ((readl(osc->sckcr) & AT91_SCKC_OSCSEL)) {
+ if ((readl(osc->sckcr) & osc->bits->cr_oscsel)) {
osc->prepared = true;
return 0;
}
@@ -434,23 +538,24 @@ static const struct clk_ops sama5d4_slow_osc_ops = {
.is_enabled = clk_sama5d4_slow_osc_is_enabled,
};
-static int of_sama5d4_sckc_setup(struct device_node *np)
+static const struct clk_slow_bits at91sama5d4_bits = {
+ .cr_oscsel = BIT(3),
+};
+
+static void __init of_sama5d4_sckc_setup(struct device_node *np)
{
void __iomem *regbase = of_iomap(np, 0);
- struct clk *clk;
+ struct clk *slow_rc, *slowck;
struct clk_sama5d4_slow_osc *osc;
const char *parent_names[2] = { "slow_rc_osc", "slow_osc" };
- bool bypass;
int ret;
if (!regbase)
- return -ENOMEM;
-
- clk = clk_fixed(parent_names[0], 32768);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
+ return;
- bypass = of_property_read_bool(np, "atmel,osc-bypass");
+ slow_rc = clk_fixed(parent_names[0], 32768);
+ if (IS_ERR(slow_rc))
+ return;
osc = xzalloc(sizeof(*osc));
osc->parent_name = of_clk_get_parent_name(np, 0);
@@ -458,23 +563,36 @@ static int of_sama5d4_sckc_setup(struct device_node *np)
osc->clk.ops = &sama5d4_slow_osc_ops;
osc->clk.parent_names = &osc->parent_name;
osc->clk.num_parents = 1;
+
+ /* osc->clk.flags = CLK_IGNORE_UNUSED; */
+
osc->sckcr = regbase;
osc->startup_usec = 1200000;
-
- if (bypass)
- writel((readl(regbase) | AT91_SCKC_OSC32BYP), regbase);
+ osc->bits = &at91sama5d4_bits;
ret = clk_register(&osc->clk);
- if (ret) {
- kfree(osc);
- return ret;
- }
-
- clk = at91_clk_register_sam9x5_slow(regbase, "slowck", parent_names, 2);
- if (IS_ERR(clk))
- return PTR_ERR(clk);
-
- return of_clk_add_provider(np, of_clk_src_simple_get, clk);
+ if (ret)
+ goto free_slow_osc_data;
+
+ slowck = at91_clk_register_sam9x5_slow(regbase, "slowck",
+ parent_names, 2,
+ &at91sama5d4_bits);
+ if (IS_ERR(slowck))
+ goto unregister_slow_osc;
+
+ ret = of_clk_add_provider(np, of_clk_src_simple_get, slowck);
+ if (WARN_ON(ret))
+ goto unregister_slowck;
+
+ return;
+
+unregister_slowck:
+ at91_clk_unregister_sam9x5_slow(slowck);
+unregister_slow_osc:
+ clk_unregister(&osc->clk);
+free_slow_osc_data:
+ kfree(osc);
+ clk_unregister(slow_rc);
}
CLK_OF_DECLARE(sama5d4_clk_sckc, "atmel,sama5d4-sckc",
of_sama5d4_sckc_setup);
diff --git a/include/linux/clk/at91_pmc.h b/include/linux/clk/at91_pmc.h
index 08a07556568a..390437887b46 100644
--- a/include/linux/clk/at91_pmc.h
+++ b/include/linux/clk/at91_pmc.h
@@ -43,8 +43,10 @@
#define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */
+#define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */
#define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
+#define AT91_PMC_KEY_MASK (0xff << 16)
#define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */
#define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */
#define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */
@@ -68,6 +70,8 @@
#define AT91_PMC_USBDIV_4 (2 << 28)
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
+#define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */
+
#define AT91_PMC_MCKR 0x30 /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
@@ -151,6 +155,20 @@
#define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */
#define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */
+#define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */
+#define AT91_PMC_FSTT(n) BIT(n)
+#define AT91_PMC_RTTAL BIT(16)
+#define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */
+#define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */
+#define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */
+#define AT91_PMC_LPM BIT(20) /* Low-power Mode */
+#define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */
+#define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */
+
+#define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */
+
+#define AT91_PMC_FS_INPUT_MASK 0x7ff
+
#define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */
#define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */
@@ -168,16 +186,8 @@
#define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */
#define AT91_PMC_PCR_PID_MASK 0x3f
-#define AT91_PMC_PCR_GCKCSS_OFFSET 8
-#define AT91_PMC_PCR_GCKCSS_MASK (0x7 << AT91_PMC_PCR_GCKCSS_OFFSET)
-#define AT91_PMC_PCR_GCKCSS(n) ((n) << AT91_PMC_PCR_GCKCSS_OFFSET) /* GCK Clock Source Selection */
#define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */
-#define AT91_PMC_PCR_DIV_OFFSET 16
-#define AT91_PMC_PCR_DIV_MASK (0x3 << AT91_PMC_PCR_DIV_OFFSET)
-#define AT91_PMC_PCR_DIV(n) ((n) << AT91_PMC_PCR_DIV_OFFSET) /* Divisor Value */
-#define AT91_PMC_PCR_GCKDIV_OFFSET 20
-#define AT91_PMC_PCR_GCKDIV_MASK (0xff << AT91_PMC_PCR_GCKDIV_OFFSET)
-#define AT91_PMC_PCR_GCKDIV(n) ((n) << AT91_PMC_PCR_GCKDIV_OFFSET) /* Generated Clock Divisor Value */
+#define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20)
#define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */
#define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 21/21] clk: at91: sckc: fix off-by-1000 in udelay()
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (19 preceding siblings ...)
2020-04-13 7:52 ` [PATCH 20/21] clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock support Ahmad Fatoum
@ 2020-04-13 7:52 ` Ahmad Fatoum
2020-04-15 9:23 ` [PATCH 00/21] clk: at91: sync with Linux v5.6 Sascha Hauer
21 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-13 7:52 UTC (permalink / raw)
To: barebox
SECOND is the number of nanoseconds in a second, but we need
the number of microseconds for use in udelay. Use USEC_PER_SEC.
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/clk/at91/sckc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 3dc7843fcc11..1a33a64421fa 100644
--- a/drivers/clk/at91/sckc.c
+++ b/drivers/clk/at91/sckc.c
@@ -20,7 +20,7 @@
#define SLOW_CLOCK_FREQ 32768
#define SLOWCK_SW_CYCLES 5
-#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * SECOND) / \
+#define SLOWCK_SW_TIME_USEC ((SLOWCK_SW_CYCLES * USEC_PER_SEC) / \
SLOW_CLOCK_FREQ)
#define AT91_SCKC_CR 0x00
--
2.26.0.rc2
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/21] of: port Linux of_get_compatible_child helper
2020-04-13 7:51 ` [PATCH 07/21] of: port Linux of_get_compatible_child helper Ahmad Fatoum
@ 2020-04-14 6:46 ` Sascha Hauer
2020-04-14 7:29 ` Ahmad Fatoum
2020-04-14 15:41 ` [PATCH] fixup! " Ahmad Fatoum
0 siblings, 2 replies; 28+ messages in thread
From: Sascha Hauer @ 2020-04-14 6:46 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Mon, Apr 13, 2020 at 09:51:50AM +0200, Ahmad Fatoum wrote:
> Incoming Linux code port makes use of the helper. Add it now instead of
> having to open-code it later.
>
> Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
> ---
> drivers/of/base.c | 25 +++++++++++++++++++++++++
> include/of.h | 8 ++++++++
> 2 files changed, 33 insertions(+)
>
> diff --git a/drivers/of/base.c b/drivers/of/base.c
> index 346d72e1e09e..5a0374a82c5c 100644
> --- a/drivers/of/base.c
> +++ b/drivers/of/base.c
> @@ -1712,6 +1712,31 @@ int of_get_available_child_count(const struct device_node *parent)
> }
> EXPORT_SYMBOL(of_get_available_child_count);
>
> +/**
> + * of_get_compatible_child - Find compatible child node
> + * @parent: parent node
> + * @compatible: compatible string
> + *
> + * Lookup child node whose compatible property contains the given compatible
> + * string.
> + *
> + * Returns a node pointer with refcount incremented, use of_node_put() on it
> + * when done; or NULL if not found.
> + */
> +struct device_node *of_get_compatible_child(const struct device_node *parent,
> + const char *compatible)
> +{
> + struct device_node *child;
> +
> + for_each_child_of_node(parent, child) {
> + if (of_device_is_compatible(child, compatible))
> + break;
> + }
for_each_child_of_node() goes down to list_for_each_entry(). On an empty
list child will point to the list head after leaving the loop. Return
child explicitly when it's compatible and NULL when leaving the loop
which is better readable as well.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/21] of: port Linux of_get_compatible_child helper
2020-04-14 6:46 ` Sascha Hauer
@ 2020-04-14 7:29 ` Ahmad Fatoum
2020-04-14 9:44 ` Michael Tretter
2020-04-14 15:41 ` [PATCH] fixup! " Ahmad Fatoum
1 sibling, 1 reply; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-14 7:29 UTC (permalink / raw)
To: Sascha Hauer; +Cc: barebox, Michael Tretter
Hello Sascha,
On 4/14/20 8:46 AM, Sascha Hauer wrote:
> for_each_child_of_node() goes down to list_for_each_entry(). On an empty
> list child will point to the list head after leaving the loop. Return
> child explicitly when it's compatible and NULL when leaving the loop
> which is better readable as well.
argh, it looked fishy to me as well, but I didn't think about comparing
Linux and barebox implementation. I just reviewed the 70 instances
of for_each_child_of_node we have and it seems only one other instance
in the overlay code has made the same assumption as I did:
- drivers/of/resolver.c: of_resolve_phandles (grep for /if (!overlay_child)/)
I can send a fixup to make it more readable but I'd want to change
for_each_child_of_node to align it with Linux behavior as well.
Cheers
Ahmad
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 07/21] of: port Linux of_get_compatible_child helper
2020-04-14 7:29 ` Ahmad Fatoum
@ 2020-04-14 9:44 ` Michael Tretter
0 siblings, 0 replies; 28+ messages in thread
From: Michael Tretter @ 2020-04-14 9:44 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
Hello Ahmad,
On Tue, Apr 14, 2020 at 09:29:36AM +0200, Ahmad Fatoum wrote:
> Hello Sascha,
>
> On 4/14/20 8:46 AM, Sascha Hauer wrote:
> > for_each_child_of_node() goes down to list_for_each_entry(). On an empty
> > list child will point to the list head after leaving the loop. Return
> > child explicitly when it's compatible and NULL when leaving the loop
> > which is better readable as well.
>
> argh, it looked fishy to me as well, but I didn't think about comparing
> Linux and barebox implementation. I just reviewed the 70 instances
> of for_each_child_of_node we have and it seems only one other instance
> in the overlay code has made the same assumption as I did:
> - drivers/of/resolver.c: of_resolve_phandles (grep for /if (!overlay_child)/)
Thanks for reporting. I sent a patch.
Michael
>
> I can send a fixup to make it more readable but I'd want to change
> for_each_child_of_node to align it with Linux behavior as well.
>
> Cheers
> Ahmad
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^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH] fixup! of: port Linux of_get_compatible_child helper
2020-04-14 6:46 ` Sascha Hauer
2020-04-14 7:29 ` Ahmad Fatoum
@ 2020-04-14 15:41 ` Ahmad Fatoum
1 sibling, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-14 15:41 UTC (permalink / raw)
To: barebox; +Cc: Sascha Hauer
The barebox implementation of for_each_child_of_node doesn't set the
iterator to NULL, when the list of children is empty.
Fix of_get_compatible_child to deal with this.
Suggested-by: Sascha Hauer <sha@pengutronix.de>
Signed-off-by: Ahmad Fatoum <a.fatoum@pengutronix.de>
---
drivers/of/base.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index 5a0374a82c5c..1223e0ab558f 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1730,10 +1730,10 @@ struct device_node *of_get_compatible_child(const struct device_node *parent,
for_each_child_of_node(parent, child) {
if (of_device_is_compatible(child, compatible))
- break;
+ return child;
}
- return child;
+ return NULL;
}
EXPORT_SYMBOL(of_get_compatible_child);
--
2.20.1
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle
2020-04-13 7:51 ` [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle Ahmad Fatoum
@ 2020-04-15 9:15 ` Ahmad Fatoum
0 siblings, 0 replies; 28+ messages in thread
From: Ahmad Fatoum @ 2020-04-15 9:15 UTC (permalink / raw)
To: barebox
Hello Sascha,
On 4/13/20 9:51 AM, Ahmad Fatoum wrote:
> Since commit b36b7b72 ("mfd: syscon: clock peripheral if specified in
> device tree"), we now clock syscons during access if the device tree nodes
> indicate a clocks property. We haven't been doing this for
> syscon_base_lookup_by_phandle though, because we did this as part of the
> regmap access functions.
I've sent a v2 of only this patch here. Please consider taking the other one
and applying the rest of the series on top.
Cheers
Ahmad
--
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Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 00/21] clk: at91: sync with Linux v5.6
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
` (20 preceding siblings ...)
2020-04-13 7:52 ` [PATCH 21/21] clk: at91: sckc: fix off-by-1000 in udelay() Ahmad Fatoum
@ 2020-04-15 9:23 ` Sascha Hauer
21 siblings, 0 replies; 28+ messages in thread
From: Sascha Hauer @ 2020-04-15 9:23 UTC (permalink / raw)
To: Ahmad Fatoum; +Cc: barebox
On Mon, Apr 13, 2020 at 09:51:43AM +0200, Ahmad Fatoum wrote:
> During a bug hunt that ultimately turned out unrelated to the state
> of the barebox at91 clk driver, I synchronized its state with Linux v5.6.
>
> This imports it, after cleanup. It refactors other code a bit to reduce
> the diff for the final port and future ones. What we gain from this:
>
> - bug fixes that have been posted upstream in the meanwhile
> - sam9x60 (new Microchip ARM926EJ-S) clock support
> - sama5d2 audio PLL
> - Some more helpers to make code porting slightly easier
> - SPDX-License-Identifiers, not only for at91 clks, but for all of
> drivers/clk
Applied with the fixup and v2 of the first patch.
Sascha
--
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31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
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^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2020-04-15 9:23 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-13 7:51 [PATCH 00/21] clk: at91: sync with Linux v5.6 Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 01/21] mfd: syscon: enable specified clocks on syscon_base_lookup_by_phandle Ahmad Fatoum
2020-04-15 9:15 ` Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 02/21] mfd: syscon: refactor of_syscon_register compatible check Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 03/21] mfd: syscon: implement device_node_to_regmap Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 04/21] regmap: retire of_node_to_regmap in favor of device_node_to_regmap Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 05/21] ARM: include: remove unused <asm/processor.h> Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 06/21] treewide: use cpu_relax() where appropriate Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 07/21] of: port Linux of_get_compatible_child helper Ahmad Fatoum
2020-04-14 6:46 ` Sascha Hauer
2020-04-14 7:29 ` Ahmad Fatoum
2020-04-14 9:44 ` Michael Tretter
2020-04-14 15:41 ` [PATCH] fixup! " Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 08/21] clk: implement clk_register_fixed_rate Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 09/21] clk: add clk_unregister stub Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 10/21] include: linux/kernel.h: port DIV_ROUND_CLOSEST_ULL definition Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 11/21] clk: migrate to SPDX-License-Identifier use Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 12/21] clk: at91: fix masterck name Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 13/21] clk: at91: fix possible deadlock Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 14/21] clk: at91: delete no-longer required DT compat code Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 15/21] clk: at91: compile dt-compat for all platforms that require it Ahmad Fatoum
2020-04-13 7:51 ` [PATCH 16/21] clk: at91: add __init marker where appropriate Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 17/21] clk: at91: Mark struct clk_range as const Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 18/21] clk: at91: allow 24 Mhz clock as input for PLL Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 19/21] clk: at91: add sama5d2 audio PLL support Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 20/21] clk: at91: port Linux v5.6 SAM9X60 (new ARM926EJ-S) clock support Ahmad Fatoum
2020-04-13 7:52 ` [PATCH 21/21] clk: at91: sckc: fix off-by-1000 in udelay() Ahmad Fatoum
2020-04-15 9:23 ` [PATCH 00/21] clk: at91: sync with Linux v5.6 Sascha Hauer
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