[PATCH 2/2] ARM: sm.c: add the attribute 'volatile' to some asm() statements.

[PATCH 2/2] ARM: sm.c: add the attribute 'volatile' to some asm() statements.

[Giorgio Dal Molin]

Prevent the compiler to eventually cache register values read/written
to/from CP15.

Signed-off-by: Giorgio Dal Molin <giorgio.nicole@arcor.de>
---
 arch/arm/cpu/sm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
index cb33d9625..f5a1edbd4 100644
--- a/arch/arm/cpu/sm.c
+++ b/arch/arm/cpu/sm.c
@@ -26,7 +26,7 @@ static unsigned int read_id_pfr1(void)
 {
 	unsigned int reg;
 
-	asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
+	asm volatile ("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
 	return reg;
 }
 
@@ -34,18 +34,18 @@ static u32 read_nsacr(void)
 {
 	unsigned int reg;
 
-	asm("mrc p15, 0, %0, c1, c1, 2\n" : "=r"(reg));
+	asm volatile ("mrc p15, 0, %0, c1, c1, 2\n" : "=r"(reg));
 	return reg;
 }
 
 static void write_nsacr(u32 val)
 {
-	asm("mcr p15, 0, %0, c1, c1, 2" : : "r"(val));
+	asm volatile ("mcr p15, 0, %0, c1, c1, 2" : : "r"(val));
 }
 
 static void write_mvbar(u32 val)
 {
-	asm("mcr p15, 0, %0, c12, c0, 1" : : "r"(val));
+	asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r"(val));
 }
 
 static int cpu_is_virt_capable(void)
-- 
2.26.0


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Re: [PATCH 2/2] ARM: sm.c: add the attribute 'volatile' to some asm() statements.

[Sascha Hauer]

On Tue, Apr 07, 2020 at 05:32:17PM +0200, Giorgio Dal Molin wrote:
> Prevent the compiler to eventually cache register values read/written
> to/from CP15.
> 
> Signed-off-by: Giorgio Dal Molin <giorgio.nicole@arcor.de>
> ---
>  arch/arm/cpu/sm.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/arch/arm/cpu/sm.c b/arch/arm/cpu/sm.c
> index cb33d9625..f5a1edbd4 100644
> --- a/arch/arm/cpu/sm.c
> +++ b/arch/arm/cpu/sm.c
> @@ -26,7 +26,7 @@ static unsigned int read_id_pfr1(void)
>  {
>  	unsigned int reg;
>  
> -	asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
> +	asm volatile ("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg));
>  	return reg;
>  }
>  
> @@ -34,18 +34,18 @@ static u32 read_nsacr(void)
>  {
>  	unsigned int reg;
>  
> -	asm("mrc p15, 0, %0, c1, c1, 2\n" : "=r"(reg));
> +	asm volatile ("mrc p15, 0, %0, c1, c1, 2\n" : "=r"(reg));
>  	return reg;
>  }
>  
>  static void write_nsacr(u32 val)
>  {
> -	asm("mcr p15, 0, %0, c1, c1, 2" : : "r"(val));
> +	asm volatile ("mcr p15, 0, %0, c1, c1, 2" : : "r"(val));
>  }
>  
>  static void write_mvbar(u32 val)
>  {
> -	asm("mcr p15, 0, %0, c12, c0, 1" : : "r"(val));
> +	asm volatile ("mcr p15, 0, %0, c12, c0, 1" : : "r"(val));
>  }
>  
>  static int cpu_is_virt_capable(void)
> -- 
> 2.26.0
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

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