[PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9

[PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9

[Ahmad Fatoum]

`mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an
i.MX6Q forces boot from the ecspi1. This is because the BootROM reads
the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10
has its 28th bit set.

Teach barebox about this, so we don't end up with a wrong $bootsource
when putting SRC_GPR9 into use.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 arch/arm/mach-imx/boot.c | 25 +++++++++++++++++++------
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 7bce1c710c57..3ff297d46e47 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -320,10 +320,13 @@ void imx53_boot_save_loc(void)
 
 #define IMX6_SRC_SBMR1	0x04
 #define IMX6_SRC_SBMR2	0x1c
+#define IMX6_SRC_GPR9	0x40
+#define IMX6_SRC_GPR10	0x44
 #define IMX6_BMOD_SERIAL	0b01
 #define IMX6_BMOD_RESERVED	0b11
 #define IMX6_BMOD_FUSES		0b00
 #define BT_FUSE_SEL		BIT(4)
+#define GPR10_BOOT_FROM_GPR9	BIT(28)
 
 static bool imx6_bootsource_reserved(uint32_t sbmr2)
 {
@@ -388,11 +391,21 @@ static int imx6_boot_instance_mmc(uint32_t r)
 	return FIELD_GET(BOOT_CFG2(4, 3), r);
 }
 
+static u32 imx6_get_src_boot_mode(void __iomem *src_base)
+{
+	if (readl(src_base + IMX6_SRC_GPR10) & GPR10_BOOT_FROM_GPR9)
+		return readl(src_base + IMX6_SRC_GPR9);
+
+	return readl(src_base + IMX6_SRC_SBMR1);
+}
+
 void imx6_get_boot_source(enum bootsource *src, int *instance)
 {
 	void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR);
-	uint32_t sbmr1 = readl(src_base + IMX6_SRC_SBMR1);
 	uint32_t sbmr2 = readl(src_base + IMX6_SRC_SBMR2);
+	uint32_t bootmode;
+
+	bootmode = imx6_get_src_boot_mode(src_base);
 
 	if (imx6_bootsource_reserved(sbmr2))
 		return;
@@ -402,23 +415,23 @@ void imx6_get_boot_source(enum bootsource *src, int *instance)
 		return;
 	}
 
-	switch (imx53_bootsource_internal(sbmr1)) {
+	switch (imx53_bootsource_internal(bootmode)) {
 	case 2:
 		*src = BOOTSOURCE_HD;
 		break;
 	case 3:
-		*src = imx6_bootsource_serial_rom(sbmr1);
-		*instance = imx6_boot_instance_serial_rom(sbmr1);
+		*src = imx6_bootsource_serial_rom(bootmode);
+		*instance = imx6_boot_instance_serial_rom(bootmode);
 		break;
 	case 4:
 	case 5:
 	case 6:
 	case 7:
 		*src = BOOTSOURCE_MMC;
-		*instance = imx6_boot_instance_mmc(sbmr1);
+		*instance = imx6_boot_instance_mmc(bootmode);
 		break;
 	default:
-		if (imx53_bootsource_nand(sbmr1))
+		if (imx53_bootsource_nand(bootmode))
 			*src = BOOTSOURCE_NAND;
 		break;
 	}
-- 
2.20.1


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[PATCH 2/3] ARM: i.MX: boot: interpret reserved boot as forced serial

[Ahmad Fatoum]

`mw 0x20d8040 0x00000010; mw 0x20d8044 0x10000000; reset` issued on an
i.MX6Q forces serial download mode, but there is no indication of that
in the sbmr2 register, so barebox reports $bootsource=unknown.

Similarly, `mw 0x20d8040 0x00000020; mw 0x20d8044 0x10000000; reset`
forces an i.MX6UL into recovery mode after reset.

Do as U-Boot does and interpret the (reserved) value in BOOT_CFG1(7, 4)
for each SoC as serial download.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 arch/arm/mach-imx/boot.c | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index 3ff297d46e47..f8d4f8cfa27f 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -31,6 +31,7 @@
 #include <mach/imx8mq-regs.h>
 #include <mach/vf610-regs.h>
 #include <mach/imx8mq.h>
+#include <mach/imx6.h>
 
 
 static void
@@ -345,6 +346,13 @@ static bool imx6_bootsource_serial(uint32_t sbmr2)
 		!(sbmr2 & BT_FUSE_SEL));
 }
 
+static bool imx6_bootsource_serial_forced(uint32_t bootmode)
+{
+	if (cpu_is_mx6ul() || cpu_is_mx6ull())
+		return bootmode == 2;
+	return bootmode == 1;
+}
+
 static int __imx6_bootsource_serial_rom(uint32_t r)
 {
 	return FIELD_GET(BOOT_CFG4(2, 0), r);
@@ -403,20 +411,23 @@ void imx6_get_boot_source(enum bootsource *src, int *instance)
 {
 	void __iomem *src_base = IOMEM(MX6_SRC_BASE_ADDR);
 	uint32_t sbmr2 = readl(src_base + IMX6_SRC_SBMR2);
-	uint32_t bootmode;
+	uint32_t bootmode, bootsrc;
 
 	bootmode = imx6_get_src_boot_mode(src_base);
 
 	if (imx6_bootsource_reserved(sbmr2))
 		return;
 
-	if (imx6_bootsource_serial(sbmr2)) {
+	bootsrc = imx53_bootsource_internal(bootmode);
+
+	if (imx6_bootsource_serial(sbmr2) ||
+	    imx6_bootsource_serial_forced(bootsrc)) {
 		*src = BOOTSOURCE_SERIAL;
 		return;
 	}
 
-	switch (imx53_bootsource_internal(bootmode)) {
-	case 2:
+	switch (bootsrc) {
+	case 2: /* unreachable for i.MX6UL(L) */
 		*src = BOOTSOURCE_HD;
 		break;
 	case 3:
-- 
2.20.1


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[PATCH 3/3] ARM: i.MX6: boot: handle i.MX6UL differences

[Ahmad Fatoum]

The i.MX6UL differs from the i.MX6Q in the interpretation of the first
two values for BOOT_CFG(7, 4):

+--------------+----------+----------+
|BOOT_CFG1(7,4)|   0x01   |   0x02   |
|==============+==========+==========|
| MX6Q         | reserved |   SATA   |
|--------------+----------+----------|
| MX6UL        |   QSPI   | reserved |
+--------------+----------+----------+

The reserved (forced serial) values are handled in the previous commit.
Add QSPI boot source detection now.

Signed-off-by: Ahmad Fatoum <ahmad@a3f.at>
---
 arch/arm/mach-imx/boot.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/boot.c b/arch/arm/mach-imx/boot.c
index f8d4f8cfa27f..dcca3a5c4a97 100644
--- a/arch/arm/mach-imx/boot.c
+++ b/arch/arm/mach-imx/boot.c
@@ -427,6 +427,9 @@ void imx6_get_boot_source(enum bootsource *src, int *instance)
 	}
 
 	switch (bootsrc) {
+	case 1: /* only reachable for i.MX6UL(L) */
+		*src = BOOTSOURCE_SPI; /* Really: qspi */
+		return;
 	case 2: /* unreachable for i.MX6UL(L) */
 		*src = BOOTSOURCE_HD;
 		break;
-- 
2.20.1


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Re: [PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9

[Sascha Hauer]

On Mon, Apr 27, 2020 at 09:13:49AM +0200, Ahmad Fatoum wrote:
> `mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an
> i.MX6Q forces boot from the ecspi1. This is because the BootROM reads
> the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10
> has its 28th bit set.

Is this documented somewhere? The reference Manual marks SRC_GPR9 and
SRC_GPR10 as

| This register is used by the ROM code and should not be used
| by application software.

And why do you depend on this behaviour?

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
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Re: [PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9

[Ahmad Fatoum]

Hello,

On 4/27/20 10:07 AM, Sascha Hauer wrote:
> On Mon, Apr 27, 2020 at 09:13:49AM +0200, Ahmad Fatoum wrote:
>> `mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an
>> i.MX6Q forces boot from the ecspi1. This is because the BootROM reads
>> the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10
>> has its 28th bit set.
> 
> Is this documented somewhere? The reference Manual marks SRC_GPR9 and
> SRC_GPR10 as
> 
> | This register is used by the ROM code and should not be used
> | by application software.

Not documented anywhere, except for U-Boot's bmode command and boot
source determination code:

https://github.com/trini/u-boot/blob/v2020.04/arch/arm/mach-imx/mx6/soc.c#L560
https://github.com/trini/u-boot/blob/v2020.04/arch/arm/mach-imx/init.c#L104

> And why do you depend on this behaviour?

It's a useful debugging aid, when strap pins aren't easily accessible,
because then your only other option is then to fuse to affect the boot
(or short your SPI I/O pins).

I am preparing code to provide a generic reboot mode functionality
in barebox. This would among others cover the functionality of
the U-Boot bmode command and these patches here are prerequisites,
so the boot source detection remains accurate.

Cheers


> 
> Sascha
> 

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Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9

[Ahmad Fatoum]

Hello,

On 4/27/20 10:28 AM, Ahmad Fatoum wrote:
> Hello,
> 
> On 4/27/20 10:07 AM, Sascha Hauer wrote:
>> On Mon, Apr 27, 2020 at 09:13:49AM +0200, Ahmad Fatoum wrote:
>>> `mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an
>>> i.MX6Q forces boot from the ecspi1. This is because the BootROM reads
>>> the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10
>>> has its 28th bit set.
>>
>> Is this documented somewhere? The reference Manual marks SRC_GPR9 and
>> SRC_GPR10 as
>>
>> | This register is used by the ROM code and should not be used
>> | by application software.

Seems it's indeed documented in the IMX6ULRM (Rev.2 03/27).
See Table 8-6. Persistent bits.

Can the patches be applied or do you need me to change something?

> 
> Not documented anywhere, except for U-Boot's bmode command and boot
> source determination code:
> 
> https://github.com/trini/u-boot/blob/v2020.04/arch/arm/mach-imx/mx6/soc.c#L560
> https://github.com/trini/u-boot/blob/v2020.04/arch/arm/mach-imx/init.c#L104
> 
>> And why do you depend on this behaviour?
> 
> It's a useful debugging aid, when strap pins aren't easily accessible,
> because then your only other option is then to fuse to affect the boot
> (or short your SPI I/O pins).
> 
> I am preparing code to provide a generic reboot mode functionality
> in barebox. This would among others cover the functionality of
> the U-Boot bmode command and these patches here are prerequisites,
> so the boot source detection remains accurate.
> 
> Cheers
> 
> 
>>
>> Sascha
>>
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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Re: [PATCH 1/3] ARM: i.MX: boot: correctly handle SRC_SBMR1 override via SRC_GPR9

[Sascha Hauer]

On Fri, May 08, 2020 at 08:41:41AM +0200, Ahmad Fatoum wrote:
> Hello,
> 
> On 4/27/20 10:28 AM, Ahmad Fatoum wrote:
> > Hello,
> > 
> > On 4/27/20 10:07 AM, Sascha Hauer wrote:
> >> On Mon, Apr 27, 2020 at 09:13:49AM +0200, Ahmad Fatoum wrote:
> >>> `mw 0x20d8040 0x08000030; mw 0x20d8044 0x10000000; reset` issued on an
> >>> i.MX6Q forces boot from the ecspi1. This is because the BootROM reads
> >>> the boot mode out of SRC_GPR9 instead of SRC_SBMR1 whenever SRC_GPR10
> >>> has its 28th bit set.
> >>
> >> Is this documented somewhere? The reference Manual marks SRC_GPR9 and
> >> SRC_GPR10 as
> >>
> >> | This register is used by the ROM code and should not be used
> >> | by application software.
> 
> Seems it's indeed documented in the IMX6ULRM (Rev.2 03/27).
> See Table 8-6. Persistent bits.
> 
> Can the patches be applied or do you need me to change something?

I just merged them

Sascha


-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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