mail archive of the barebox mailing list
 help / color / mirror / Atom feed
* [PATCH] net: designware: eqos: attach PHY earlier
@ 2020-05-11 16:50 Lucas Stach
  2020-05-12  5:44 ` Ahmad Fatoum
  2020-05-12  7:52 ` Sascha Hauer
  0 siblings, 2 replies; 3+ messages in thread
From: Lucas Stach @ 2020-05-11 16:50 UTC (permalink / raw)
  To: barebox

If the PHY isn't driving the refclock, the software reset of the
controller will time out. Some PHYs need some board specific
configuration to properly drive the reflock. Attach the PHY before
attempting the software reset, so PHY fixups have a chance to run.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
 drivers/net/designware_eqos.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/net/designware_eqos.c b/drivers/net/designware_eqos.c
index cb52f3942d86..d2baaeaf6372 100644
--- a/drivers/net/designware_eqos.c
+++ b/drivers/net/designware_eqos.c
@@ -360,6 +360,11 @@ static int eqos_start(struct eth_device *edev)
 	int ret;
 	int i;
 
+	ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
+				 eqos->ops->adjust_link, 0, eqos->interface);
+	if (ret)
+		return ret;
+
 	setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
 
 	ret = readl_poll_timeout(&eqos->dma_regs->mode, mode_set,
@@ -379,11 +384,6 @@ static int eqos_start(struct eth_device *edev)
 	val = (rate / USEC_PER_SEC) - 1; /* -1 because the data sheet says so */
 	writel(val, &eqos->mac_regs->us_tic_counter);
 
-	ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
-				 eqos->ops->adjust_link, 0, eqos->interface);
-	if (ret)
-		return ret;
-
 	/* Before we reset the mac, we must insure the PHY is not powered down
 	 * as the dw controller needs all clock domains to be running, including
 	 * the PHY clock, to come out of a mac reset.  */
-- 
2.20.1


_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] net: designware: eqos: attach PHY earlier
  2020-05-11 16:50 [PATCH] net: designware: eqos: attach PHY earlier Lucas Stach
@ 2020-05-12  5:44 ` Ahmad Fatoum
  2020-05-12  7:52 ` Sascha Hauer
  1 sibling, 0 replies; 3+ messages in thread
From: Ahmad Fatoum @ 2020-05-12  5:44 UTC (permalink / raw)
  To: Lucas Stach, barebox

On 5/11/20 6:50 PM, Lucas Stach wrote:
> If the PHY isn't driving the refclock, the software reset of the
> controller will time out. Some PHYs need some board specific
> configuration to properly drive the reflock. Attach the PHY before
> attempting the software reset, so PHY fixups have a chance to run.
Tested-by: Ahmad Fatoum <a.fatoum@pengutronix.de>

> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/net/designware_eqos.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/designware_eqos.c b/drivers/net/designware_eqos.c
> index cb52f3942d86..d2baaeaf6372 100644
> --- a/drivers/net/designware_eqos.c
> +++ b/drivers/net/designware_eqos.c
> @@ -360,6 +360,11 @@ static int eqos_start(struct eth_device *edev)
>  	int ret;
>  	int i;
>  
> +	ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
> +				 eqos->ops->adjust_link, 0, eqos->interface);
> +	if (ret)
> +		return ret;
> +
>  	setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
>  
>  	ret = readl_poll_timeout(&eqos->dma_regs->mode, mode_set,
> @@ -379,11 +384,6 @@ static int eqos_start(struct eth_device *edev)
>  	val = (rate / USEC_PER_SEC) - 1; /* -1 because the data sheet says so */
>  	writel(val, &eqos->mac_regs->us_tic_counter);
>  
> -	ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
> -				 eqos->ops->adjust_link, 0, eqos->interface);
> -	if (ret)
> -		return ret;
> -
>  	/* Before we reset the mac, we must insure the PHY is not powered down
>  	 * as the dw controller needs all clock domains to be running, including
>  	 * the PHY clock, to come out of a mac reset.  */
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 3+ messages in thread
* Re: [PATCH] net: designware: eqos: attach PHY earlier
  2020-05-11 16:50 [PATCH] net: designware: eqos: attach PHY earlier Lucas Stach
  2020-05-12  5:44 ` Ahmad Fatoum
@ 2020-05-12  7:52 ` Sascha Hauer
  1 sibling, 0 replies; 3+ messages in thread
From: Sascha Hauer @ 2020-05-12  7:52 UTC (permalink / raw)
  To: Lucas Stach; +Cc: barebox

On Mon, May 11, 2020 at 06:50:38PM +0200, Lucas Stach wrote:
> If the PHY isn't driving the refclock, the software reset of the
> controller will time out. Some PHYs need some board specific
> configuration to properly drive the reflock. Attach the PHY before
> attempting the software reset, so PHY fixups have a chance to run.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  drivers/net/designware_eqos.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)

Applied, thanks

Sascha

> 
> diff --git a/drivers/net/designware_eqos.c b/drivers/net/designware_eqos.c
> index cb52f3942d86..d2baaeaf6372 100644
> --- a/drivers/net/designware_eqos.c
> +++ b/drivers/net/designware_eqos.c
> @@ -360,6 +360,11 @@ static int eqos_start(struct eth_device *edev)
>  	int ret;
>  	int i;
>  
> +	ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
> +				 eqos->ops->adjust_link, 0, eqos->interface);
> +	if (ret)
> +		return ret;
> +
>  	setbits_le32(&eqos->dma_regs->mode, EQOS_DMA_MODE_SWR);
>  
>  	ret = readl_poll_timeout(&eqos->dma_regs->mode, mode_set,
> @@ -379,11 +384,6 @@ static int eqos_start(struct eth_device *edev)
>  	val = (rate / USEC_PER_SEC) - 1; /* -1 because the data sheet says so */
>  	writel(val, &eqos->mac_regs->us_tic_counter);
>  
> -	ret = phy_device_connect(edev, &eqos->miibus, eqos->phy_addr,
> -				 eqos->ops->adjust_link, 0, eqos->interface);
> -	if (ret)
> -		return ret;
> -
>  	/* Before we reset the mac, we must insure the PHY is not powered down
>  	 * as the dw controller needs all clock domains to be running, including
>  	 * the PHY clock, to come out of a mac reset.  */
> -- 
> 2.20.1
> 
> 
> _______________________________________________
> barebox mailing list
> barebox@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/barebox
> 

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
barebox@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/barebox

^ permalink raw reply	[flat|nested] 3+ messages in thread
end of thread, other threads:[~2020-05-12  7:52 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-11 16:50 [PATCH] net: designware: eqos: attach PHY earlier Lucas Stach
2020-05-12  5:44 ` Ahmad Fatoum
2020-05-12  7:52 ` Sascha Hauer

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox