[PATCH 1/3] ARM: i.MX6 dtsi: add enet_out clock

[PATCH 1/3] ARM: i.MX6 dtsi: add enet_out clock

[Marco Felsch]

The barebox fec driver supports enet_clk out since commit 2de277264c
("i.MX: fec: Enable all clocks specified for FEC") but unfortunately
this clock is not specified upstream. Enable it here till we can use it
from upstream to make it clear that IMX6QDL_CLK_ENET_REF should be used
as enet_out clock.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/dts/imx6qdl.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi
index 828be9ce0d..9d37133bbf 100644
--- a/arch/arm/dts/imx6qdl.dtsi
+++ b/arch/arm/dts/imx6qdl.dtsi
@@ -8,3 +8,11 @@
 		ipu0 = &ipu1;
 	};
 };
+
+&fec {
+	clocks = <&clks IMX6QDL_CLK_ENET>,
+		 <&clks IMX6QDL_CLK_ENET>,
+		 <&clks IMX6QDL_CLK_ENET_REF>;
+		 <&clks IMX6QDL_CLK_ENET_REF>;
+	clock-names = "ipg", "ahb", "ptp", "enet_out";
+};
-- 
2.20.1


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[PATCH 2/3] ARM: imx6ul: add fec bits to GPR syscon definition

[Marco Felsch]

The commit is based on linux commit:
8<-----------------------------------------------------------
commit 9f55eb92441883a1afca48dc8d32bf62c4d8e833
Author: Fugang Duan <b38611@freescale.com>
Date:   Tue Jul 28 15:30:39 2015 +0800

    ARM: imx6ul: add fec bits to GPR syscon definition

    FEC requires additional bits to select refrence clock.

    Signed-off-by: Fugang Duan <B38611@freescale.com>
    Signed-off-by: Shawn Guo <shawnguo@kernel.org>
8<-----------------------------------------------------------

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 include/mfd/imx6q-iomuxc-gpr.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/include/mfd/imx6q-iomuxc-gpr.h b/include/mfd/imx6q-iomuxc-gpr.h
index b2c9da6579..16c83a778c 100644
--- a/include/mfd/imx6q-iomuxc-gpr.h
+++ b/include/mfd/imx6q-iomuxc-gpr.h
@@ -344,4 +344,12 @@
 #define IMX6Q_GPR13_SATA_PHY_1_MED		(0x1 << 0)
 #define IMX6Q_GPR13_SATA_PHY_1_SLOW		(0x2 << 0)
 
+/* For imx6ul iomux gpr register field define */
+#define IMX6UL_GPR1_ENET1_CLK_DIR		(0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_DIR		(0x1 << 18)
+#define IMX6UL_GPR1_ENET1_CLK_OUTPUT		(0x1 << 17)
+#define IMX6UL_GPR1_ENET2_CLK_OUTPUT		(0x1 << 18)
+#define IMX6UL_GPR1_ENET_CLK_DIR		(0x3 << 17)
+#define IMX6UL_GPR1_ENET_CLK_OUTPUT		(0x3 << 17)
+
 #endif /* __LINUX_IMX6Q_IOMUXC_GPR_H */
-- 
2.20.1


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[PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d

[Marco Felsch]

Setup the ENET TX reference clk to get it from the internal clock from
anatop. This is the default value for newer imx6 processors like: 6sx,
6ul, 6ull. So it should be safe to set it as default for imx6q/d too.

It will be output on the pad if ENET_REF_CLK is muxed which can be used
to clock a phy.

While on it replace the current 'magic' value by the new introduced
definition.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
---
 arch/arm/mach-imx/imx6.c | 24 ++++++++++++++++++------
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/arch/arm/mach-imx/imx6.c b/arch/arm/mach-imx/imx6.c
index 6a9ea23c71..f325e698fa 100644
--- a/arch/arm/mach-imx/imx6.c
+++ b/arch/arm/mach-imx/imx6.c
@@ -160,16 +160,28 @@ static void imx6_setup_ipu_qos(void)
 	}
 }
 
-static void imx6ul_enet_clk_init(void)
+static void imx6_enet_clk_init(void)
 {
-	void __iomem *gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
-	uint32_t val;
+	void __iomem *gprbase;
+	uint32_t val, bitmask;
 
-	if (!cpu_mx6_is_mx6ul() && !cpu_mx6_is_mx6ull())
+	switch (imx6_cpu_type()) {
+	case IMX6_CPUTYPE_IMX6D:
+	case IMX6_CPUTYPE_IMX6Q:
+		gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR);
+		bitmask = IMX6Q_GPR1_ENET_CLK_SEL_ANATOP;
+		break;
+	case IMX6_CPUTYPE_IMX6UL:
+	case IMX6_CPUTYPE_IMX6ULL:
+		gprbase = IOMEM(MX6_IOMUXC_BASE_ADDR) + 0x4000;
+		bitmask = IMX6UL_GPR1_ENET_CLK_OUTPUT;
+		break;
+	default:
 		return;
+	}
 
 	val = readl(gprbase + IOMUXC_GPR1);
-	val |= (0x3 << 17);
+	val |= bitmask;
 	writel(val, gprbase + IOMUXC_GPR1);
 }
 
@@ -264,7 +276,7 @@ int imx6_init(void)
 	pr_info("%s unique ID: %llx\n", cputypestr, mx6_uid);
 
 	imx6_setup_ipu_qos();
-	imx6ul_enet_clk_init();
+	imx6_enet_clk_init();
 
 	pfuze_register_init_callback(imx6_register_poweroff_init);
 
-- 
2.20.1


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Re: [PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d

[Sascha Hauer]

Hi Marco,

On Thu, Aug 06, 2020 at 11:29:19AM +0200, Marco Felsch wrote:
> Setup the ENET TX reference clk to get it from the internal clock from
> anatop. This is the default value for newer imx6 processors like: 6sx,
> 6ul, 6ull. So it should be safe to set it as default for imx6q/d too.

I don't follow this reasoning. We only ever know the boards that are
unhappy with the reset default, because these are the ones that change
it. Now if we change the register default we can't know which boards
stop working because they relied on the previous reset default value.

Here is an example from U-Boot where this bit is explicitly cleared:

board/tqc/tqma6/tqma6_mba6.c:85: clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);

We support this board in barebox as well and it might break with your
change, so I don't think this patch is a good idea.

Sascha

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Re: [PATCH 3/3] ARM: i.MX: setup ENET_CLK_SEL in imx6_init for every imx6q/imx6d

[Marco Felsch]

On 20-08-10 09:16, Sascha Hauer wrote:
> Hi Marco,
> 
> On Thu, Aug 06, 2020 at 11:29:19AM +0200, Marco Felsch wrote:
> > Setup the ENET TX reference clk to get it from the internal clock from
> > anatop. This is the default value for newer imx6 processors like: 6sx,
> > 6ul, 6ull. So it should be safe to set it as default for imx6q/d too.
> 
> I don't follow this reasoning. We only ever know the boards that are
> unhappy with the reset default, because these are the ones that change
> it. Now if we change the register default we can't know which boards
> stop working because they relied on the previous reset default value.
> 
> Here is an example from U-Boot where this bit is explicitly cleared:
> 
> board/tqc/tqma6/tqma6_mba6.c:85: clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
> 
> We support this board in barebox as well and it might break with your
> change, so I don't think this patch is a good idea.

Okay, after talking with Oleksij I thought this would be the common
case instead of using an external osc and it would drop confusions
why it's working 'magicaly' out of the box for all other imx devices.

Anyway got your point.

Regards,
  Marco

> Sascha

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