* [PATCH 1/2] drivers/ddr/imx8: remove leftover DEBUG defines @ 2020-09-30 13:24 Lucas Stach 2020-09-30 13:24 ` [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order Lucas Stach 0 siblings, 1 reply; 5+ messages in thread From: Lucas Stach @ 2020-09-30 13:24 UTC (permalink / raw) To: barebox This produces quite a bit of log noise and should not be enabled by default. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- drivers/ddr/imx8m/ddr_init.c | 2 +- drivers/ddr/imx8m/ddrphy_train.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ddr/imx8m/ddr_init.c b/drivers/ddr/imx8m/ddr_init.c index 374601b786c2..093b9ea905db 100644 --- a/drivers/ddr/imx8m/ddr_init.c +++ b/drivers/ddr/imx8m/ddr_init.c @@ -2,7 +2,7 @@ /* * Copyright 2018-2019 NXP */ -#define DEBUG + #include <common.h> #include <errno.h> #include <io.h> diff --git a/drivers/ddr/imx8m/ddrphy_train.c b/drivers/ddr/imx8m/ddrphy_train.c index c2238cc66b3b..2563b809467a 100644 --- a/drivers/ddr/imx8m/ddrphy_train.c +++ b/drivers/ddr/imx8m/ddrphy_train.c @@ -2,7 +2,7 @@ /* * Copyright 2018 NXP */ -#define DEBUG + #include <common.h> #include <linux/kernel.h> #include <soc/imx8m/ddr.h> -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order 2020-09-30 13:24 [PATCH 1/2] drivers/ddr/imx8: remove leftover DEBUG defines Lucas Stach @ 2020-09-30 13:24 ` Lucas Stach 2020-10-02 4:21 ` Sascha Hauer 2020-10-07 8:05 ` Sascha Hauer 0 siblings, 2 replies; 5+ messages in thread From: Lucas Stach @ 2020-09-30 13:24 UTC (permalink / raw) To: barebox This way we end up with the fastest DDR speed when training is finished and don't need to rely on TF-A to switch into a higher DDR speed. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> --- arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c index b164bdec07f1..33ef5542a364 100644 --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { { DDRC_FREQ2_INIT7(0), 0x0006004a }, /* boot start point */ - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 + { DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2 }; /* PHY Initialize Configuration */ @@ -1940,12 +1940,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = lpddr4_fsp0_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), - }, { - /* P0 3000mts 2D */ - .drate = 3000, - .fw_type = FW_2D_IMAGE, - .fsp_cfg = lpddr4_fsp0_2d_cfg, - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), }, { /* P1 400mts 1D */ .drate = 400, @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { .fw_type = FW_1D_IMAGE, .fsp_cfg = lpddr4_fsp2_cfg, .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), + }, { + /* P0 3000mts 2D */ + .drate = 3000, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), }, }; -- 2.20.1 _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order 2020-09-30 13:24 ` [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order Lucas Stach @ 2020-10-02 4:21 ` Sascha Hauer 2020-10-02 8:19 ` Lucas Stach 2020-10-07 8:05 ` Sascha Hauer 1 sibling, 1 reply; 5+ messages in thread From: Sascha Hauer @ 2020-10-02 4:21 UTC (permalink / raw) To: Lucas Stach; +Cc: barebox Hi Lucas, On Wed, Sep 30, 2020 at 03:24:17PM +0200, Lucas Stach wrote: > This way we end up with the fastest DDR speed when training is finished > and don't need to rely on TF-A to switch into a higher DDR speed. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > index b164bdec07f1..33ef5542a364 100644 > --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { > { DDRC_FREQ2_INIT7(0), 0x0006004a }, > > /* boot start point */ > - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 > + { DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2 What's this change about? Sascha > }; > > /* PHY Initialize Configuration */ > @@ -1940,12 +1940,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > .fw_type = FW_1D_IMAGE, > .fsp_cfg = lpddr4_fsp0_cfg, > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), > - }, { > - /* P0 3000mts 2D */ > - .drate = 3000, > - .fw_type = FW_2D_IMAGE, > - .fsp_cfg = lpddr4_fsp0_2d_cfg, > - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > }, { > /* P1 400mts 1D */ > .drate = 400, > @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > .fw_type = FW_1D_IMAGE, > .fsp_cfg = lpddr4_fsp2_cfg, > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), > + }, { > + /* P0 3000mts 2D */ > + .drate = 3000, > + .fw_type = FW_2D_IMAGE, > + .fsp_cfg = lpddr4_fsp0_2d_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > }, > }; > > -- > 2.20.1 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order 2020-10-02 4:21 ` Sascha Hauer @ 2020-10-02 8:19 ` Lucas Stach 0 siblings, 0 replies; 5+ messages in thread From: Lucas Stach @ 2020-10-02 8:19 UTC (permalink / raw) To: Sascha Hauer; +Cc: barebox On Fr, 2020-10-02 at 06:21 +0200, Sascha Hauer wrote: > Hi Lucas, > > On Wed, Sep 30, 2020 at 03:24:17PM +0200, Lucas Stach wrote: > > This way we end up with the fastest DDR speed when training is finished > > and don't need to rely on TF-A to switch into a higher DDR speed. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > --- > > arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 14 +++++++------- > > 1 file changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > > index b164bdec07f1..33ef5542a364 100644 > > --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > > +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > > @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { > > { DDRC_FREQ2_INIT7(0), 0x0006004a }, > > > > /* boot start point */ > > - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 > > + { DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2 > > What's this change about? That's the initial timing set being used. Without this change we would end up with the PLL set for 3000MT/s, but the timing set for 100MT/s being used by the controller, which obviously will not work. Regards, Lucas > Sascha > > > }; > > > > /* PHY Initialize Configuration */ > > @@ -1940,12 +1940,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > > .fw_type = FW_1D_IMAGE, > > .fsp_cfg = lpddr4_fsp0_cfg, > > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), > > - }, { > > - /* P0 3000mts 2D */ > > - .drate = 3000, > > - .fw_type = FW_2D_IMAGE, > > - .fsp_cfg = lpddr4_fsp0_2d_cfg, > > - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > > }, { > > /* P1 400mts 1D */ > > .drate = 400, > > @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > > .fw_type = FW_1D_IMAGE, > > .fsp_cfg = lpddr4_fsp2_cfg, > > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), > > + }, { > > + /* P0 3000mts 2D */ > > + .drate = 3000, > > + .fw_type = FW_2D_IMAGE, > > + .fsp_cfg = lpddr4_fsp0_2d_cfg, > > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > > }, > > }; > > > > -- > > 2.20.1 > > > > > > _______________________________________________ > > barebox mailing list > > barebox@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/barebox > > _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order 2020-09-30 13:24 ` [PATCH 2/2] ARM: i.MX: nxp-imx8mm-evk: adjust DDR training order Lucas Stach 2020-10-02 4:21 ` Sascha Hauer @ 2020-10-07 8:05 ` Sascha Hauer 1 sibling, 0 replies; 5+ messages in thread From: Sascha Hauer @ 2020-10-07 8:05 UTC (permalink / raw) To: Lucas Stach; +Cc: barebox On Wed, Sep 30, 2020 at 03:24:17PM +0200, Lucas Stach wrote: > This way we end up with the fastest DDR speed when training is finished > and don't need to rely on TF-A to switch into a higher DDR speed. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) Applied, thanks Sascha > > diff --git a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > index b164bdec07f1..33ef5542a364 100644 > --- a/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > +++ b/arch/arm/boards/nxp-imx8mm-evk/lpddr4-timing.c > @@ -118,7 +118,7 @@ static struct dram_cfg_param lpddr4_ddrc_cfg[] = { > { DDRC_FREQ2_INIT7(0), 0x0006004a }, > > /* boot start point */ > - { DDRC_MSTR2(0), 0x2 }, //DDRC_MSTR2 > + { DDRC_MSTR2(0), 0x0 }, //DDRC_MSTR2 > }; > > /* PHY Initialize Configuration */ > @@ -1940,12 +1940,6 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > .fw_type = FW_1D_IMAGE, > .fsp_cfg = lpddr4_fsp0_cfg, > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), > - }, { > - /* P0 3000mts 2D */ > - .drate = 3000, > - .fw_type = FW_2D_IMAGE, > - .fsp_cfg = lpddr4_fsp0_2d_cfg, > - .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > }, { > /* P1 400mts 1D */ > .drate = 400, > @@ -1958,6 +1952,12 @@ static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { > .fw_type = FW_1D_IMAGE, > .fsp_cfg = lpddr4_fsp2_cfg, > .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg), > + }, { > + /* P0 3000mts 2D */ > + .drate = 3000, > + .fw_type = FW_2D_IMAGE, > + .fsp_cfg = lpddr4_fsp0_2d_cfg, > + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), > }, > }; > > -- > 2.20.1 > > > _______________________________________________ > barebox mailing list > barebox@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/barebox > -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ barebox mailing list barebox@lists.infradead.org http://lists.infradead.org/mailman/listinfo/barebox ^ permalink raw reply [flat|nested] 5+ messages in thread
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